WO1992022131A1 - Amplificateur operationnel classe ab - Google Patents

Amplificateur operationnel classe ab Download PDF

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Publication number
WO1992022131A1
WO1992022131A1 PCT/NL1992/000092 NL9200092W WO9222131A1 WO 1992022131 A1 WO1992022131 A1 WO 1992022131A1 NL 9200092 W NL9200092 W NL 9200092W WO 9222131 A1 WO9222131 A1 WO 9222131A1
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WO
WIPO (PCT)
Prior art keywords
output
stage
class
pmos
amplifier
Prior art date
Application number
PCT/NL1992/000092
Other languages
English (en)
Inventor
Petrus Hendrikus Seesink
Original Assignee
Sierra Semiconductor B.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sierra Semiconductor B.V. filed Critical Sierra Semiconductor B.V.
Publication of WO1992022131A1 publication Critical patent/WO1992022131A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3217—Modifications of amplifiers to reduce non-linear distortion in single ended push-pull amplifiers

Definitions

  • the present invention relates to a class AB amplifier com ⁇ prising at least a CMOS inverter output stage of a series connec- tion of a first NMOS transistor and a first PMOS transistor.
  • Such a class AB amplifier is known from US-A-4.335.355.
  • Said known class amplifier comprises essentially three stages: an input stage, a source follower stage and a CMOS inverter output stage.
  • a disadvantage of the prior art amplifier is that the current through the source follower stage is difficult to control and is very sus ⁇ ceptible for variations in manufacturing method and in the supply voltage. Variations of the supply voltage between 4,5 and 5,5 Volt may, depending on the manufacturing method and the temperature, even lead to variations in said source follower stage current by a factor cf 10. For many applications this not acceptable.
  • the source follower stage current has to be controlled on a very small value the speed of the amplifier may be affected. In circuits having critical speed requirements, therefore, the prior art ampli ⁇ bomb from US-A- .335.355 cannot be used. It is an object of the present invention to provide a class AB amplifier that solves the problems mentioned above.
  • a class AB amplifier comprising a current source connected to the output of the inverter stage, to control the turn-over point of the amplifier and wherein the gates of said first PMOS and said first NMOS tran ⁇ sistor are connected together, said gates constituting the input of said inverter output stage.
  • the amplifier according to the invention may be applied in high frequency CMOS amplifiers and may be realized on a very small chip area.
  • said current source comprises a MOS transistor parallel to either said first PMOS or NMOS transistor and a gate voltage control circuit to con ⁇ trol the gate voltage of said MOS transistor.
  • said gate voltage control circuit comprises a second PMOS transistor having its drain connected tc both the dram of a second NMOS transistor and to the non-invertmg inpuc of an operational amplifier, the gates of sa d second PMOS transistor and said second NMOS transis ⁇ tor being connected together, a third NMOS transistor the drain of which being connected to both a current source and to the gates of said second PMOS and said second NMOS transistor, the inverting input of said operational amplifier receiving a reference voltage, and a third PMOS transistor having its gate connected to the output of said operational amplifier and its dram connected to the non- inverting input of said operational amplifier, wherein the output of said operational amplifier constitutes the output of said gate voltage control circui .
  • said first PMOS and said first NMOS transistor have equal, minimum dimensions.
  • Fig. 2 shows a prior art inverter stage m which the turn ⁇ over point is controlled by current infection
  • Fig. 3 shows a NAND-circuit in which the turn-over point is controlled by current injection
  • Fig. 6 shows a prior art two-stage class AB Miller oper ⁇ ational amplifier
  • the basic idea of the present invention is to control the turn-over point of a CMOS inverter output stage of class AB ampli ⁇ bombs by current injection into the output of the inverter output stage.
  • An example of a prior art class AB amplifier comprising a CMOS inverter output stage is shown in fig. 6.
  • the class AB operational amplifier of fig. 6 comprises essen ⁇ tially three stages: an input stage, a source follower stage, and an inverter output stage.
  • the input stage comprises a current source 11, and four MOS transistors M3, M4, M5, and M6 connected in a way knovm to a person skilled in the art, which need no further explanation.
  • the output of the input stage is connected to the source follower stage comprising a series connection of a current source 12 and a PMOS transistor M7.
  • the point of connection of the PMOS transistor M7 and the current source 12 is connected to the gate of a PMOS transistor M1.
  • the gate of PMOS transistor M7 being the input of the source follower stage is connected to the output of the input stage as well as to the gate of a NMOS transistor M2.
  • PMOS transistor M1 and NMOS transistor M2 are connected in series in order to form a CMOS inverter output stage.
  • the inverter output stage comprises a series connection of a capacitor C and a resistor R which series connection is connected between the output OUT of the inverter output stage and the gate of NMOS transistor M2.
  • Series connection R, C functions as a feed back frequency compensation.
  • the source follower stage 12 M7 may be left out, while still control ⁇ ling the turn-over point of the output stage.
  • a current source injects current into the output of the output ' stage, e.g. in the way as shown in fig. 7, which will be discussed later.
  • Fig. 1 shows a prior art inverting single gain stage realized in CMOS-technology.
  • the gates of the complementary PMOS-transistor M1 and NMOS-transistor M2 are connected to each other and consti- tute the input of the inverter circuit.
  • the source of transistor M1 is connected to the power supply voltage V DD , while its drain is connected to the drain of transistor M2, being at the same time the output of the inverter circuit.
  • the source of M2 is con ⁇ nected to the other power supply voltage V ss .
  • the turn-over point of the inverter circuit is equal to the mid-supply voltage, in order to realize this in case of the prior art circuit of fig. 1 the PMOS- and NMOS-transistor cannot have equal dimensions and hence both transistors cannot have minimum dimensions.
  • One of the consequences of that is an increased input capacitance.
  • Fig. 2 shows an inverting circuit having current injection into its output.
  • the inverter circuit shown is identical to that of fig. 1, except that its output is connected to a current source, which injects a control current l cu ⁇ -i into the inverter circuit.
  • I ctrl By adjusting the magnitude of control current I ctrl the turn-over point can be varied.
  • I ctl-1 is positive the turn-over point will increase when I ctr . increases.
  • the turn-over point will decrease when l etrl decreases. This also applies to negative values
  • Fig. 3 shows an application thereof m a NAND-circuit, where ⁇ as fig. 4 shows an application in a NOR-circuit.
  • Fig. 3 and 4 com ⁇ prise circuits having two inputs (A and B;, but basically the num- ber of inputs may have any arbitrary value (shown with dotted lines) .
  • the operational amplifier A Dependent on the non-inverting input voltage level of the operational amplifier A, which itself is determined by the input voltage (POS) of one of the CMOS-inverter circuits, the operational amplifier A will have a predetermined output voltage. Usually, the reference voltage V_ ⁇ £ will be equal to the mid-supply voltage.
  • the circuit of fig. 5 has the following advantages:
  • CMOS inverter stage is used in linear applications.
  • One prominent example of such a linear application is in a class AB operational amplifier..
  • the class AB operational amplifier of fig. 7 constitutes essentially of only two stages: an input stage and an inverter output stage.
  • the input stage comprises a current source l ⁇ , and four MOS transistors M3, M4, M5, and M6 connected in a way known to a person skilled in the art, which need no further explanation.
  • the output of the input stage is connected to the input stage of the inverter output stage, i.e. the gates of a PMOS transistor M1 and a NMOS transistor M2.
  • the inverter output stage comprises a series connection of a capacitor C and a resistor R which series connection is connected between the output OUT of the inverter output stage and the input of the inver ⁇ ter output stage.
  • Series connection R, C functions as a feed back frequency compensation.
  • the turn-over point of the output stage is controlled by current injection.
  • any appropriate current source I ctr . injecting a control current can be used to carry out the teaching of the present invention.
  • a preferred embodiment of a current source according to the invention is shown in fig. 7.
  • a PMOS transistor M1A is connected parallel to PMOS transistor K1.
  • a gate voltage control circuit controls the gate voltage cf PMOS transistor MIA and therefore the current in ected into the output of the class AB operational amplifier.
  • Sa d gate voltage control circuit comprises an inverter stage comprising a PMOS transistor MB1 and a NMOS transistor MB2 con- nected in series and having their gates connected together.
  • a PMOS transistor MB1A is connected parallel to PMOS transistor MB1.
  • the output of the inverter stage MB ⁇ , MB2 is connected to the non-in ⁇ verting input of an operational amplifier A, while the inverting input of operational amplifier A receives a reference voltage Vref and the output of the operational amplifier A is connected to both the gate of PMOS transistor MB1 and the gate cf PMOS transistor M1A.
  • a series connection of a current source IB and a NMOS transis ⁇ tor MB3 controls the input voltage cf the inverter stage MB1 , MB2 by way of a connection of the point of connection of the current source IB and NMOS transistor MB3 both to the input of the inverter stage MB1, MB2, and to the gate of NMOS transistor MB3.
  • voltage Vref will be chosen equal to the mid-supply voltage.
  • the input stage of the class AB amplifier of fig. 7 is a standard differential amplifier stage. To obtain a class AB ampli- bomb this differential amplifier stage may be left out. Leaving out the differential amplifier stage would result in a single stage class AB amplifier, the input of which is the input cf the CMOS inverter stage M1 , M2, i.e. the gates of both MOS transistors M1 , M2 being connected together, and the output of which is the output of the CMOS inverter stage M1 , M2.
  • Such single stage class AB amplifier may be seen as the basic linear embodiment of the present invention.
  • the field of application of the present invention is in switched-capacitor circuits, because the amplifier according to fig. 7 can only have a capacitive load.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

Amplificateur classe AB comprenant au moins un étage de sortie d'inverseur à NOS complémentaire pour la connexion en série avec un transistor MOS à canal N (M2) et un transistor MOS à canal P (M1) comprenant une source de courant connectée à la sortie de l'étage inverseur, afin de contrôler le point de rotation de l'amplificateur, les portes du transistor du MOS à canal P (M1) et du transistor MOS à canal N (M2) sont connectées ensemble, lesdites portes constituant l'entrée dudit étage de sortie de l'inverseur.
PCT/NL1992/000092 1991-05-31 1992-05-27 Amplificateur operationnel classe ab WO1992022131A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL9100947 1991-05-31
NL9100947A NL9100947A (nl) 1991-05-31 1991-05-31 Inrichting voor superhogesnelheid-cmos-circuits.

Publications (1)

Publication Number Publication Date
WO1992022131A1 true WO1992022131A1 (fr) 1992-12-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/NL1992/000092 WO1992022131A1 (fr) 1991-05-31 1992-05-27 Amplificateur operationnel classe ab

Country Status (2)

Country Link
NL (1) NL9100947A (fr)
WO (1) WO1992022131A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1983000785A1 (fr) * 1981-08-14 1983-03-03 Motorola Inc Circuit comparateur cmos a haute vitesse
US4587491A (en) * 1985-04-29 1986-05-06 National Semiconductor Corporation IC class AB amplifier output stage
EP0365291A2 (fr) * 1988-10-18 1990-04-25 Hewlett-Packard Company Amplificateur à transistor pour hautes vitesses de balayage et charges capacitives
EP0412567A2 (fr) * 1989-08-10 1991-02-13 Siemens Aktiengesellschaft Etage de commutation à transistor intégrable à seuil ajustable

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1983000785A1 (fr) * 1981-08-14 1983-03-03 Motorola Inc Circuit comparateur cmos a haute vitesse
US4587491A (en) * 1985-04-29 1986-05-06 National Semiconductor Corporation IC class AB amplifier output stage
EP0365291A2 (fr) * 1988-10-18 1990-04-25 Hewlett-Packard Company Amplificateur à transistor pour hautes vitesses de balayage et charges capacitives
EP0412567A2 (fr) * 1989-08-10 1991-02-13 Siemens Aktiengesellschaft Etage de commutation à transistor intégrable à seuil ajustable

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IEE PROCEEDINGS vol. 137, no. 6, December 1990, STEVENAGE,HERTS. (GB) pages 470 - 474; SINGH ET AL: 'simple high-frequency cmos transconductor' *
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. vol. CAS33, no. 11, November 1986, NEW YORK US pages 1132 - 1138; PARK ET AL: 'a high-frequency cmos linear transconductance element' *

Also Published As

Publication number Publication date
NL9100947A (nl) 1992-12-16

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