WO1992013331A1 - Appareil d'affichage pour ordinateur et procede de defilement haute resolution - Google Patents

Appareil d'affichage pour ordinateur et procede de defilement haute resolution Download PDF

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Publication number
WO1992013331A1
WO1992013331A1 PCT/US1991/007058 US9107058W WO9213331A1 WO 1992013331 A1 WO1992013331 A1 WO 1992013331A1 US 9107058 W US9107058 W US 9107058W WO 9213331 A1 WO9213331 A1 WO 9213331A1
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WIPO (PCT)
Prior art keywords
data
screen
screen view
block
register
Prior art date
Application number
PCT/US1991/007058
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English (en)
Inventor
Alberto C. Moreira
Original Assignee
Wang Laboratories, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wang Laboratories, Inc. filed Critical Wang Laboratories, Inc.
Publication of WO1992013331A1 publication Critical patent/WO1992013331A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/34—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling
    • G09G5/346—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling for systems having a bit-mapped display memory

Definitions

  • a display subsystem is the component part responsible for displaying processor generated output on a video display unit screen.
  • the display subsystem receives screen view signals output from the host computer.
  • a graphics controller employed by the display subsystem holds the signals in a memory area, reformats the signals, forms a bit map from the reformatted signals and holds the bit map in video memory. From the bit map, a display driver continually refreshes the screen of the video display unit to display the output generated by the host processor.
  • the typical display subsystem rewrites the original bit map by copying the contents of the video memory into itself displaced by one row. For example, with upward scrolling, the entire bit map is copied starting with the old bit map second row copied as the first row of the new bit map for the scrolled screen view. After copying to the second row from the bottom of the new bit map (i.e. the last row of the old bit map), the display subsystem erases the bottom row of the working bit map and substitutes therein a new bottom row for the scrolled screen view.
  • full screen scrolling requires a large amount of information (i.e. a large number of pixel data) to be physically moved. Such transfers of large amounts of data often result in reduced performance in high resolution graphics display subsystems.
  • VGA Video Graphics Array Subsystem
  • the VGA subsystem provides different modes of display (e.g. text, graphics, color, gray scale and high resolution) at different resolutions.
  • High resolution is generally defined as 1024 pixels horizontal by 768 pixels vertical per screen view. Full screen scrolling in high resolution modes tends to be slow due to the large amounts of information having to be physically moved and recopied into the video memory bit map.
  • the present invention solves the prior art problems of full screen scrolling in high resolution graphics displays .
  • the present invention provides time and memory efficient full screen scrolling of high resolution graphics displays by avoiding physical transfers of large amounts of display data.
  • the present invention employs a memory for holding data to be displayed, a start register, a split screen register and computer means for changing the start register and the split screen register.
  • the memory holds data to be displayed in screen views on the display unit.
  • the memory capacity exceeds that required for one screen view.
  • One block of data at a time from a contiguous portion of the memory provides a screen view.
  • the start register provides an indication of starting memory address of the block of data to be displayed in a screen view.
  • a display driver coupled to the memory and start register drives the display unit with the block of data indicated by the start register.
  • the computer means changes the start register indication from starting memory address of one block of data to starting memory address of a succeeding block of data, as by a one row change in the indication.
  • the display driver drives the display unit to display data being scrolled from one screen view to a succeeding screen view.
  • the present invention utilizes the split screen register, heretofore only known for supporting windowing. Specifically, the present invention further employs the split screen register for instances where the block of data to be displayed in a screen view bridges across the last display data holding memory address to the first data holding memory address of the memory.
  • the split screen register identifies a beginning block of data in memory which is conventionally displayed as a second view such as in a window. The window may be located at the bottom of the display.
  • the split screen register provides an indication of a division in the block of data to be displayed in a single screen view.
  • the block of data is divided into (a) a first portion beginning at the starting memory address indicated by the start register and ending at the last memory address holding display data and (b) a second portion beginning at the first data holding memory address of the memory.
  • the display driver combines the first and second portions of data by driving a first portion of the screen view from the first portion of the split block of data and driving a second portion of the screen view from the second portion of the split block of data.
  • the display driver drives the first and second portions of the screen view in cooperation with each other to provide the appearance of a single full screen view.
  • the start register indication is changed toward the last memory address, and the split screen register is incremented to increase the size of the split view to thus add new rows to the end of the combined display. Again, no shifting of data in memory is required.
  • Figure 1 is a schematic diagram of a display subsystem embodying the present invention.
  • FIGS 2a-2g are schematic illustrations of operation of the video memory in the embodiment of Figure 1 to provide full screen scrolling.
  • FIG. 1 Illustrated in Figure 1 is a display subsystem 11 embodying the present invention.
  • the display subsystem 11 employs a graphics controller 15, a video (bit map) memory 21, and a display driver 19.
  • the graphics controller 15 and display driver 19 are coupled in series between a host processor 13 and video display monitor 25.
  • the host processor 13 is a digital processor of the micro or mini computer type, for example an Intel 8086, 80286, 80386 or 80486 processor.
  • the display monitor 25 is any video display or CRT (cathode ray tube) common in the art such as a IBM 8513 or Wang 1413.
  • CTR cathode ray tube
  • the host processor 13 transmits display pixel data on bus 23 to graphics controller 15.
  • Graphics controller 15 employs a bit map memory 21 for holding received display data.
  • memory 21 is a video RAM (random access memory) such as a Texas Instrument SMJ4461 which has a memory matrix for holding display data and a cooperating high-speed serial interface that transfers a multiplicity of pixel data at a time. To that end, the video RAM is freed for access while simultaneously transmitting screen view signals corresponding to the display data.
  • video RAM random access memory
  • other buffering means are suitable, including use of standard Dynamic RAMs such as the Texas Instruments SMJ4256.
  • screen graphics patterns are output from the host processor 13 to bit map memory 21 of graphics controller 15.
  • Address generator 29 provides the proper memory address source of the screen graphics patterns being output by the host processor 13.
  • Screen graphics patterns are output to, and thus, written in bit map memory 21 in the order in which corresponding pixels are to be displayed in a screen view and hence in raster scanning order of display monitor 25.
  • the video memory 21 capacity exceeds that required for one screen view 31.
  • the screen graphics patterns are stored in the video memory 21 in a manner which forms an extended bit map of screen view 31.
  • address generator 29 is of the VGA Graphics Controller type.
  • Display driver 19 receives control signals transmitted from graphics controller 15 which indicate that screen view signals are stored in the video memory 21 and hence that a bit map on screen view 31 is currently set. Read/write operations between graphics controller 15 and display driver 19 are then coordinated by timing generator 27.
  • Timing generator 27 is for example a VGA sequencer or of a similar type.
  • display driver 19 and corresponding graphics controller 15 are those of a VGA (Video Graphics Array) chip by IBM modified and adapted for use in the present invention. Other similar graphics array chips or display drivers and video memories are suitable.
  • a start register provides an indication of the video memory address at which the display signal for the beginning screen view pixel is stored.
  • the display driver drives pixels of the screen view beginning with display signals stored at the video memory address indicated by the start register.
  • the VGA display subsystem copies into the video memory beginning at the address indicated by the start register, the bit map displaced by one display line and adds a new (top or bottom) display line as described previously.
  • the display driver rescans the entire screen view with the updated bit map located at the effectively static memory address indicated by the start register.
  • the VGA display subsystem utilizes a split screen register which indicates beginning video memory address of a block of data to be displayed in a second view portion or a separate, independent window.
  • the video memory addresses which hold display data do not change from screen view to screen view, rather the data contents stored at these addresses are made to change.
  • the video memory may be divided into a display-data-holding segment and a character-generation-information segment. The latter segment generally occupies the last addresses of the video memory and stores font specifications and the like.
  • start address registers 33 point to or indicate the video memory address at which the display signal for the beginning screen view pixel is stored. Successive screen view pixels are stored at video memory addresses succeeding the starting memory address indicated by registers 33.
  • display driver 19 drives pixels of screen view 31 by converting the corresponding bit map stored display signals to respective voltage signals. Display driver 19 accomplishes this with common means and methods such as a digital to analog converter 40. Display driver 19 outputs the voltage signals over line 37 to display monitor 25 in a time and space order such that each line (row) of pixels in screen view 31 is scanned and updated. The foregoing is repeated to constantly refresh screen view 31.
  • the present invention provides full screen scrolling in high resolution modes at a performance rate as fast as text mode scrolling.
  • the present invention accomplishes this as follows. Instead of moving pixels (display signals corresponding thereto) in the video memory bit map as in the prior art, the present invention takes advantage of the fact that the video memory 21 retains an extended bit map of screen view 31. That is, screen view signals for display lines preceeding the currently displayed first line are located in memory addresses preceeding the current bit map and screen view signals for displaying lines succeeding the currently displayed last line are located in memory addresses succeeding the current bit map.
  • scrolling the displayed screen view upwardly corresponds to adjusting memory location of the bit map to include succeeding memory addresses.
  • scrolling the displayed screen viewed downwardly corresponds to adjusting memory location of the bit map to include preceeding memory addresses.
  • bit map 41 for screen view 31 of Figure 1 is shown to comprise memory rows A, B, C, and D of video memory 21.
  • each memory row (address) in Figures 2a-2d is illustrated to support an integer number of (in particular, one) display lines of the screen view 31.
  • Start address registers 33 indicate memory row (address) A to be the beginning point of the bit map contents ( Figure 2a) .
  • To scroll one display line up, start address registers 33 are advanced to indicate video memory row (address) B as the starting point for bit map 41.
  • bit map 41 comprises video memory rows (addresses) B, C, D, and E shown in Figure 2b. Scrolling another line up is effected similarly.
  • bit map 41 As can be seen, continued scrolling one line at a time eventually provides starting address registers 33 indicating memory row (address) E as the beginning point of bit map 41 as shown in Figure 2c. And the contents of bit map 41 include video memory rows (addresses) E through H, the illustrated last row (address) of the video memory 21.
  • the present invention employs the VGA split screen capability to locate the portion of the bit map 41 that overflows the video memory 21.
  • the overflow portion is located from the first data holding address or beginning of the video memory 21 as illustrated in Figure 2d.
  • start address registers 33 are set to indicate the beginning memory address for the contents of a first portion 41a of the bit map.
  • That first portion of the bit map includes the memory row from that address pointed to by registers 33 (row F) through the last address of the video memory 21 (row H) .
  • the split screen register 35 is then set to split the bit map after the memory row corresponding to the last line of pixels of the bit map portion 41a.
  • bit map 41 This in turn locates the remainder of bit map 41 to the beginning of the video memory 21 and thus effectively provides a wrap-around capability to the beginning of the video memory 21.
  • a second bit map portion 41b is provided from the beginning addresses of the video memory 21 (e.g. memory row A) .
  • the bit map first portion 41a supports display of an upper portion of screen view 31, and the bit map second portion 41b supports display of a lower portion of screen view 31.
  • the screen view is being supported by two bit map portions 41a, 41b, the user sees a composite, single view.
  • the screen view remains as a single view but is defined in part by start registers 33 and in part by the split screen function (heretofore limited to windowing) .
  • the present invention operates the start registers 33 and split screen register 35 in a dynamic (changeable) fashion to redefine the bit map from various contiguous blocks of data in video memory 21, to support full screen scrolling of screen view 31.
  • the split screen register 35 is set to split the screen view 31 at a computed corresponding scan line.
  • the computed scan line is the subject character line (i.e. 47) multiplied by 16 (again, assuming a 16 point font) .
  • a split screen value is computed every time the screen view is scrolled. Further, if the video memory 21 holds other information in addition to display data, wrapping around is from a bottom end of the memory segment holding display data to the beginning of that segment of the video memory 21. And it is that segment of memory along which the bit map can continually slide.
  • Figures 2c-2g are illustrative of the foregoing, where bit map 41 is shown sliding down and wrapping around video memory 21 (or the display data holding segment thereof) .
  • the size of the bit map is indicated as 41s and is constant since the screen view 31 is of a constant size.
  • the amount of overflow portion of bit map 41 which overflows the end of the video memory segment holding display data
  • OV The amount of overflow (portion of bit map 41 which overflows the end of the video memory segment holding display data) is indicated OV and is illustrated to equal the amount by which the bit map must wrap around video memory 21 and be displayed in a second portion of the split screen operation.
  • the amount of the wraparound portion and hence the second or lower portion of the split screen is indicated as Sp.
  • OV Sp.
  • bit map 41 sliding down from the beginning to ending of the display-data-holding segment of video memory 21 without overflow computation of a split screen value is insignificant (i.e., null) as can be seen by Figures 2a through 2c.
  • the first significant computation of a split screen value is illustrated in Figure 2d, where the bit map first begins to overflow video memory 21.
  • the video memory portion corresponding to the second part of the split screen is the beginning addresses of video memory 21.
  • bit map 41 progresses along the end of video memory 21 and overflows more.
  • bit map 41 is at the last address of the display holding segment of video memory 21.
  • the remaining bit map portion (second half of the split screen) is supported by the first several addresses of video memory 21.
  • bit map 41 is shown totally overflowing video memory 21 and wrapped around to the beginning addresses of video memory 21.
  • the screen view is supported by the beginning memory addresses of video memory 21 which hold the first screen full of display data.
  • the start address register is set to the first address of memory 21, and the split screen register is set to zero.
  • the present invention display subsystem 11 thus operates as follows. Data signals from host processor 13 are transmitted and stored in video memory 21. Host processor 13 sets start address registers 33 to indicate the beginning address of a block of data to be displayed on the next view 31 of display monitor 25 and also sets the split address registers 35 accordingly. Host processor 13 transmits signals to display driver 19 to signify that a block of data to be currently displayed is indicated by start address registers 33 and split address registers 35. In response, diplay driver 19 reads the indicated block of data from video memory 21 and enables raster scanning of the screen view 31. If the split address register 35 is set to a valid value then display driver 19 raster scans an upper portion of the screen view 31 beginning with the.
  • start address registers 33 a video memory address 21 indicated by start address registers 33
  • Host processor 13 updates the start address registers 33 to indicate a succeeding block of data for the next screen view 31 (current screen view scrolled) and also updates split address registers 35 accordingly.
  • Display driver 19 continues to drive the display monitor 25 with a series of screen views 31 according to the indications of start address registers 33 and split address registers 35, which in turn, displays full screen scrolling on display monitor 25.
  • start address registers 33 comprise a first byte register, a second byte register, and extension registers 39 for any bits of the video memory address beyond the 17th bit, as illustrated in Figure 1. If extension registers 39 are not employed, the present invention method of scrolling will only work for modes that use a video memory visibility smaller than 64k bytes.
  • split address registers 35 include two one-byte registers.
  • the lower eight bits of the split screen value are located in a controller register of the display monitor 25, and the remaining two most significant bits are located in an overflow register of display monitor 25. This allows up to 1024 scan lines resolution, which will enable resolutions up to or comparable to 1280 pixels vertical by 1204 pixels horizontal.
  • scrolling of the present invention requires a contiguous visibility for the video memory 21.
  • the present invention scrolling can be used with any resolution in either text, plane or byte modes, but is particularly advantageous for 800 x 600 or 1024 x 768 4-plane modes where the video memory is organized as two 4-plane visibilities spanning two working segments (A000 and B000) or one visibility (A000) of the split screen operation.
  • Further scrolling of the present invention may be used when applications require their own fast screen handling and may bypass the basic I/O system or operate their own screen access methods (for example, via C subroutines written in assembly language) or windows drivers.
  • the basic I/O system is required to take the current screen start address into consideration. For example, in a typical 16-color high resolution mode, 128k bytes of visibility are used, and requires a 17-bit address. To compute the address, it is necessary first to compute the "local coordinates" address, that is, the distance from the current start of the screen to the memory byte where the pixel is stored. Then, one must wrap around the 128k boundary to account for the split screen. Finally the address must be added to the address of the working memory segment (A000) corresponding to the first half of the split screen operation, to yield the real location of the byte.
  • the "local coordinates" address that is, the distance from the current start of the screen to the memory byte where the pixel is stored.
  • the address must be added to the address of the working memory segment (A000) corresponding to the first half of the split screen operation, to yield the real location of the byte.
  • BPR is the number of bytes per row
  • Col is the column
  • ChW is the character width which is the number of pixels per character scan line, typically eight;
  • BPC is the bytes per column and is the number of bytes required to hold one character scan line. This will be one byte for 16-color modes or 8 bytes for 256-color modes.
  • ScrnSt is the screen start address indicated by start address registers 33.
  • each scan line has 1024 pixels, or 128 bytes.
  • BPR is thus 128, and to multiple by 128 one needs only to shift a register (or bytes therein) left seven places.
  • the pixel can be written or read using standard plane mode VGA routines, identical to those required for modes lOh, llh, or 12h.
  • the screen start registers 33 In order to scroll, the screen start registers 33 must be updated to start at the beginning of the next memory row as previously described.
  • the start address In plane mode, the start address is a real visibility address so that the computation is as follows:
  • StartAddress (StartAddress + BPR) & lffffh.
  • BPR The bytes per row (BPR) must be computed by multiplying the number of character points (ChPts) by the number of bytes per scan line.
  • ChPts character points
  • ChW is character width
  • Second byte Register of start address Registers 33 Second byte Register + 8;
  • Second most significant bit of the Second byte Register Second most significant bit of Second byte Register + Carry;
  • split address registers 35 must be set to their rightful values. If there are 512k bytes in video memory 21, 1024 scan lines may be accommodated. The computation of the split screen value is as follows:
  • the scan line of screen start (ScrnSt) is simply computed by dividing the screen start by the number of bytes per scan line.
  • the screen is 768 scan lines deep. Each scan line has 128 bytes, and the character width (ChW) is one. Dividing the start address by 128 yields the scan line of screen start. This division is the same as multiplying the upper ten bits of the start address registers 33 by two. As a result, whenever start address register 33 indicate a screen start beyond the video memory address corresponding to scan line 256, the screen will be split and the present invention will utilize the split screen capability for scrolling screen views.
  • routines illustrate implementation of the present invention display subsystem on an Intel 80286 processor using an IBM VGA chip.
  • Memory references and nomenclature follow IBM VGA standards.
  • this routine uses the "Start of Screen" field in location 0:44eh of the basic I/O system low memory to hold the paragraph of the screen start. This is not strictly necessary, as the paragraph can be read from the start address registers, but it is much simpler; extracting the screen start from start address (or VGA) registers requires isolating bits 8 and 9 from the extension register (display monitor Controller Overflow Register) , and is considerably slower than just moving the start address from the basic I/O system data area.
  • Scroll lkx768 modes To be called from inside the Write TTY function Oeh whenever a line feed requires a scroll. This is a full screen scroll only and should not be used for function 06h or 07h.
  • mov al,7 bit 8 goes to crtc 7 select crtc 7 read it into ah bl has bits 8-9 bl has bit 8 align to go in crtc 7 bit 4 wipe out crtc 7 bit 4 insert new bit 4 write crtc 7 back
  • extension register Oeh ah has register contents call closext ; close extension registers pop dx ; restore dx ret higet endp

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

Un défilement plein écran dans un sous-système d'affichage, en particulier des sous-systèmes VGA, est décrit. Le procédé et l'appareil de défilement utilisent le registre de départ de l'écran VGA et le fonctionnement à écran divisé pour effectuer le défilement sans déplacer physiquement des données. Le défilement plein écran permet d'obtenir des performances élevées dans des modes graphiques à haute résolution. Des indications d'adresse de mémoire vidéo provenant du registre de départ de l'écran et du registre d'écran divisé effectuent le défilement et le bouclage de la mémoire vidéo. Le registre d'écran divisé permet d'obtenir un affichage à écran plein et unifié à partir de données provenant de deux parties de la mémoire vidéo.
PCT/US1991/007058 1991-01-24 1991-09-26 Appareil d'affichage pour ordinateur et procede de defilement haute resolution WO1992013331A1 (fr)

Applications Claiming Priority (2)

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US64539091A 1991-01-24 1991-01-24
US645,390 1991-01-24

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5754161A (en) * 1995-01-30 1998-05-19 Mitsubishi Denki Kabushiki Kaisha Graphic display scrolling apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0145529A2 (fr) * 1983-10-18 1985-06-19 Digital Equipment Corporation Dispositif à décalage régulier à écran partagé
US5045845A (en) * 1986-10-31 1991-09-03 Yamaha Corporation Image processing apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0145529A2 (fr) * 1983-10-18 1985-06-19 Digital Equipment Corporation Dispositif à décalage régulier à écran partagé
US5045845A (en) * 1986-10-31 1991-09-03 Yamaha Corporation Image processing apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5754161A (en) * 1995-01-30 1998-05-19 Mitsubishi Denki Kabushiki Kaisha Graphic display scrolling apparatus

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