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Semiconductor device

Info

Publication number
WO1992008188A1
WO1992008188A1 PCT/JP1991/001496 JP9101496W WO1992008188A1 WO 1992008188 A1 WO1992008188 A1 WO 1992008188A1 JP 9101496 W JP9101496 W JP 9101496W WO 1992008188 A1 WO1992008188 A1 WO 1992008188A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
data
processing
device
length
flag
Prior art date
Application number
PCT/JP1991/001496
Other languages
French (fr)
Inventor
Hidenori Nagao
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 - G06F7/556 or for performing logical operations
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/3808Details concerning the type of numbers or the way they are handled
    • G06F2207/3812Devices capable of handling different types of numbers
    • G06F2207/3816Accepting numbers of variable word length

Abstract

A semiconductor device capable of easily processing data different in length, and an electronic arrangement incorporating the semiconductor device. The semiconductor device comprises input means for fetching unpacked input data, a register having a flag to be set at the processing of unpacked data, and an ALU capable of processing data, different in length. When the flag is set to the above register and the current instruction indicates the processing of short-length data, the ALU processes data having half the length of the input data and sets a carry signal for high-order bits of the data to a carry flag. For example, even when the ALU has the function to process 16- and 8-bit data, it is able to process 4-bit data when the 8-bit data processing is selected and an unpacking flag is set.
PCT/JP1991/001496 1990-11-02 1991-11-01 Semiconductor device WO1992008188A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP29767790 1990-11-02
JP2/297677 1990-11-02

Publications (1)

Publication Number Publication Date
WO1992008188A1 true true WO1992008188A1 (en) 1992-05-14

Family

ID=17849714

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1991/001496 WO1992008188A1 (en) 1990-11-02 1991-11-01 Semiconductor device

Country Status (1)

Country Link
WO (1) WO1992008188A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7966482B2 (en) 1994-12-02 2011-06-21 Intel Corporation Interleaving saturated lower half of data elements from two source registers of packed data

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6222144A (en) * 1985-07-23 1987-01-30 Nec Corp Decimal arithmetic circuit
JPS63175927A (en) * 1987-01-12 1988-07-20 American Telephone & Telegraph Method and apparatus for processing binary coded dicimal/backed data
JPS6462727A (en) * 1987-09-03 1989-03-09 Fujitsu Ltd Adder-subtracter
JPS6462726A (en) * 1987-09-03 1989-03-09 Fujitsu Ltd Adder-subtracter

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6222144A (en) * 1985-07-23 1987-01-30 Nec Corp Decimal arithmetic circuit
JPS63175927A (en) * 1987-01-12 1988-07-20 American Telephone & Telegraph Method and apparatus for processing binary coded dicimal/backed data
JPS6462727A (en) * 1987-09-03 1989-03-09 Fujitsu Ltd Adder-subtracter
JPS6462726A (en) * 1987-09-03 1989-03-09 Fujitsu Ltd Adder-subtracter

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7966482B2 (en) 1994-12-02 2011-06-21 Intel Corporation Interleaving saturated lower half of data elements from two source registers of packed data
US8190867B2 (en) 1994-12-02 2012-05-29 Intel Corporation Packing two packed signed data in registers with saturation
US8495346B2 (en) 1994-12-02 2013-07-23 Intel Corporation Processor executing pack and unpack instructions
US8521994B2 (en) 1994-12-02 2013-08-27 Intel Corporation Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation
US8601246B2 (en) 1994-12-02 2013-12-03 Intel Corporation Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register
US8639914B2 (en) 1994-12-02 2014-01-28 Intel Corporation Packing signed word elements from two source registers to saturated signed byte elements in destination register
US8793475B2 (en) 1994-12-02 2014-07-29 Intel Corporation Method and apparatus for unpacking and moving packed data
US8838946B2 (en) 1994-12-02 2014-09-16 Intel Corporation Packing lower half bits of signed data elements in two source registers in a destination register with saturation
US9015453B2 (en) 1994-12-02 2015-04-21 Intel Corporation Packing odd bytes from two source registers of packed data
US9116687B2 (en) 1994-12-02 2015-08-25 Intel Corporation Packing in destination register half of each element with saturation from two source packed data registers
US9141387B2 (en) 1994-12-02 2015-09-22 Intel Corporation Processor executing unpack and pack instructions specifying two source packed data operands and saturation
US9182983B2 (en) 1994-12-02 2015-11-10 Intel Corporation Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers
US9223572B2 (en) 1994-12-02 2015-12-29 Intel Corporation Interleaving half of packed data elements of size specified in instruction and stored in two source registers
US9361100B2 (en) 1994-12-02 2016-06-07 Intel Corporation Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements
US9389858B2 (en) 1994-12-02 2016-07-12 Intel Corporation Orderly storing of corresponding packed bytes from first and second source registers in result register

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