JPS6462726A - Adder-subtracter - Google Patents

Adder-subtracter

Info

Publication number
JPS6462726A
JPS6462726A JP22069987A JP22069987A JPS6462726A JP S6462726 A JPS6462726 A JP S6462726A JP 22069987 A JP22069987 A JP 22069987A JP 22069987 A JP22069987 A JP 22069987A JP S6462726 A JPS6462726 A JP S6462726A
Authority
JP
Japan
Prior art keywords
zone
data
arithmetic
format
executing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22069987A
Other languages
Japanese (ja)
Inventor
Toshimitsu Nagata
Shigemi Uemoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22069987A priority Critical patent/JPS6462726A/en
Publication of JPS6462726A publication Critical patent/JPS6462726A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To operate data of a zone format in a state that is remains at a zone format, by executing a binary coded decimal operation in a numerical value part, executing a binary operation in a zone part, and also, executing a carry between the numerical value part and the zone part being adjacent to each other. CONSTITUTION:A zone part of a data d1 is set to '0' by a zone part setting control part 5, and data d2 adder or subtracted to or from the data d1 is supplied to an arithmetic part 1 together with the data d1 in a form as it is. The arithmetic part 1 executes a decimal operation with regard to each digit of the numerical value part of the data d1, d2, and a carry is brought to carry as it is to the zone part of the upper side. On the other hand, the arithmetic part 1 executes a binary operation with regard to each digit of the zone part of the data d1, d2, based on a zone part arithmetic control signal CNTL from a zone part arithmetic control part 7. A zone part setting control part 6 sets the zone part of an output of the arithmetic part 1 to '1'. In such a way, by operating data of a zone format by the zone format as it is, it becomes unnecessary to convert a data format, and the arithmetic can be executed at a high speed.
JP22069987A 1987-09-03 1987-09-03 Adder-subtracter Pending JPS6462726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22069987A JPS6462726A (en) 1987-09-03 1987-09-03 Adder-subtracter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22069987A JPS6462726A (en) 1987-09-03 1987-09-03 Adder-subtracter

Publications (1)

Publication Number Publication Date
JPS6462726A true JPS6462726A (en) 1989-03-09

Family

ID=16755105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22069987A Pending JPS6462726A (en) 1987-09-03 1987-09-03 Adder-subtracter

Country Status (1)

Country Link
JP (1) JPS6462726A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992008188A1 (en) * 1990-11-02 1992-05-14 Seiko Epson Corporation Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992008188A1 (en) * 1990-11-02 1992-05-14 Seiko Epson Corporation Semiconductor device

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