WO1992008188A1 - Dispositif a semi-conducteur - Google Patents

Dispositif a semi-conducteur Download PDF

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Publication number
WO1992008188A1
WO1992008188A1 PCT/JP1991/001496 JP9101496W WO9208188A1 WO 1992008188 A1 WO1992008188 A1 WO 1992008188A1 JP 9101496 W JP9101496 W JP 9101496W WO 9208188 A1 WO9208188 A1 WO 9208188A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
bit
flag
register
alu
Prior art date
Application number
PCT/JP1991/001496
Other languages
English (en)
Japanese (ja)
Inventor
Hidenori Nagao
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corporation filed Critical Seiko Epson Corporation
Publication of WO1992008188A1 publication Critical patent/WO1992008188A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/3816—Accepting numbers of variable word length

Definitions

  • the present invention relates to a semiconductor device, and particularly to an arithmetic and logic unit therefor.
  • ALU inputs two operation terms, respectively, and adds or subtracts, for example, 8-bit data. Then, of the 9-bit operation result, the lower 8 bits are output as the operation result output, and the upper 1 bit is output as the carry signal.
  • the arithmetic function is fixed at 8 bits, so that the power that cannot handle data in units of 4 bits (1 nib ore) can be handled.
  • a 4-bit double arithmetic was executed. After that, the 5th bit out of the 8 bits of the operation result is referred to by the program, and it must be determined by the program whether the carry has occurred. The handling was troublesome. Disclosure of the invention
  • An object of the present invention to enable calculation of data having a plurality of bit widths.
  • An object of the present invention is to arbitrarily switch an arithmetic result to a hexadecimal or a 10-base.
  • An object of the present invention is to provide a semiconductor device capable of performing the above operation.
  • Another object of the present invention is to provide an electronic device incorporating such a semiconductor device.
  • a semiconductor device includes: an input unit for receiving an input data in an unpacked state; and a flag for performing an arithmetic operation. It is possible to perform arithmetic processing on the data to be set and the data of a plurality of bit widths, and the flag is set in the register and the short bit is set. When data processing of the bit width is commanded, the arithmetic operation is performed on the data of the bit width of 1Z2 of the input data, and the carry signal of the upper bit is calculated. With ALU to set in the carry flag.
  • the ALU has an arithmetic processing function of 16-bit and 8-bit bit widths, an arithmetic processing of data of 8-bit bit width is selected, and When an unchecked flag is set, the following processing is performed to obtain a 4-bit 1Z2 bit. The arithmetic processing of the bit width is performed.
  • the input data is input in an unpacked state. Therefore, only the lower 4 bits are valid and the upper 4 bits are invalid (the upper 4 bits). The bits are set to 0.) In this state, arithmetic processing is performed on the lower 4 bits, and the carry (or borrow) of the 4th bit is keyed. By setting the carry flag, the existence of the upper 4 bits is ignored, and the next 8 bits of data (the valid part is the lower 4 bits) However, it will function as a carry (or borrow) for the.
  • the operation in this case may be any of addition, subtraction, multiplication and division.
  • an arithmetic function in units of 4 bits is added to an arithmetic function previously fixed in units of 8 bits. It is now possible to programmatically select between bit operation and 4-bit operation.
  • 4-bit operation an overflow occurs every digit, and when the present invention is incorporated in a micro computer, multiple overflow occurs.
  • Each digit of the output result of complicated numerical calculation can be easily stored in one address unit. Therefore, the data is stored in one address and one address, and the decimal point position can be easily adjusted.
  • the semiconductor device sets a decimal flag when converting hexadecimal data to decimal data. It has a resistor.
  • the ALU converts the hexadecimal operation result to 10-decimal data and outputs it.
  • the data when storing arithmetic data in a storage device, the data is packed and stored, and the data is read out from the storage device. In this case, the data is automatically read and read.
  • the above-described semiconductor device is applied to various electronic devices.
  • it is applied to arithmetic operators, in which case setting the decimal flag allows the operation result to be displayed in decimal notation.
  • FIG. 1 is a block diagram showing a configuration of a semiconductor device according to one embodiment of the present invention.
  • Fig. 2 is a block diagram showing the details of the ALU in Fig. 1.
  • c Fig. 3 is an external view of the four arithmetic unit to which the semiconductor device in Fig. 1 is applied.
  • FIG. 4 to FIG. 11 are explanatory diagrams of the decimal operation, the anchor operation, and the pack operation.
  • FIGS. 12A and 12B are flow charts showing the processing flow in the case of addition processing in the four arithmetic units of FIG. 3.
  • FIG. 13 is a flowchart of FIG. This is a flow chart showing the flow of the processing of the operation routine of FIG.
  • FIG. 14 is a diagram showing a work area of the RAM.
  • FIG. 15 is a diagram showing an example of input data.
  • FIG. 16A to FIG. 16G are diagrams showing changes in data stored in the work area.
  • Fig. 17 is an evening chart showing the operation of the step of the addition process in Fig. 13.
  • FIG. 18 is a diagram showing data when the ADD instruction is executed.
  • FIG. 19 is a diagram showing data at the time of executing a pack instruction.
  • Figure 20 shows the data at the time of execution of the amp instruction.
  • FIG. 21A, FIG. 21B, FIG. 22A, FIG. 22B, and FIG. 23 to FIG. 29 are diagrams showing specific circuits of the ALU in FIG. BEST MODE FOR CARRYING OUT THE INVENTION
  • the semiconductor device shown in FIG. 1 includes a dress bus 2 and a data bus 4.
  • the input register 6 is used to input the input data from the data bus and to the timing generator. 8 Input the timing signals of these.
  • This instruction is decoded by the instruction decoder 10, and the micro-instruction signal is used. It is sent out via line group 12.
  • Reference numeral 4 is connected to the address bus 2 and the data bus 4 and to the microinstruction signal line group 12.
  • the data register group (A, B) 16 is connected to the data bus 4 and the microinstruction signal line group 12.
  • Temporary registers 18 and 20 are also connected to data bus 4 and microinstruction signal line group 12, and their outputs are Output to ALU22.
  • the temporary carry flag 24 is used to input the condition flag 26, the other flags, and the temporary register 18 And is connected to the microstructural signal line group 12.
  • AL ⁇ 22 receives the signals from the temporary carrier flag 24 and the temporary register 18, 20, as well as Performs prescribed arithmetic processing based on the transaction.
  • Temporary register 28 receives the output of ALU 22 and receives address bus 2 and data bus based on microinstruction. Output data via 4.
  • the input port 30 inputs a key input from the keyboard 32 via the address bus 2 and the data bus 4.
  • the ROM 34 stores, for example, a system program, etc.
  • the RAM 36 stores, for example, a key input from an external keyboard 32. In addition, it functions as a working memory described later.
  • the LCD driver 38 receives the data of the temporary register 28 and drives the LCD panel 40 to display the data.
  • the portion surrounded by a dashed line is composed of a chip microprocessor 42, an input port 3 2 and a keyboard 3 2 is an LCD driver 38 and an LCD panel 40 constituting the input device 44. 6.
  • ALU 2.2 is a 16-bit padder 50, as shown in Figure 2, and a decimator resistor.
  • a logic circuit 52 including clock logic and a right shifter 54 are included.
  • the ALU 22 can perform arithmetic processing of 16-bit and 8-bit bit widths, and each microcontroller corresponds to the bit width.
  • An installation kit is provided. Here, a description will be given of a case where an arithmetic processing function of 8-bit width is selected. In other words, in this embodiment, even when the 8-bit arithmetic processing function is selected, a 4-bit arithmetic processing can be performed. Therefore, the following description focuses on this point.
  • microactions are used.
  • the outline of the microactions is as follows.
  • ⁇ U SUB Inverts the temporary register A18 and "CYIN" during SUB and SBC operations, and generates a complement value of "2". Also, operate the flag on the operation result
  • UAND Selects AND operation as the ALU22 operation mode. Also, the flag is operated on the operation result (N, Z). • UOR: Performs an OR operation. Others are the same as UAND O
  • UCAL16 Selects 16-bit mode as ALU22 status (input signal to flag).
  • UDAPK Decimal area just operation and unpack operation (4 bits) are permitted. It is enabled at 8-bit addition / subtraction (ADD, ADC, SUB, SBC).
  • ⁇ SEP The 8-bit “2” complement value is expanded to 16 bits.
  • SWAP Exchanges the upper 2 and lower 2 bits of 8-bit data.
  • ⁇ UUPCK The data on the 8-bit register is stored in 16 bits. Unpack the data on the register.
  • microinstructions marked with ⁇ in the above are particularly related to the present invention.
  • the semiconductor device described above is applied to various types of electronic equipment.Here, the operation when applied to the four arithmetic units as shown in FIG. 3 will be mainly described. You
  • FIGS. 4 and 5 show. As shown. Whether the result of addition or subtraction of the input terms is output as BCD or HEX is switched according to the decimating flag "DF" described later.
  • FIGS. 6 and 7 show examples in which a 4-bit HEX value “7” and “B” are added and subtracted, respectively.
  • the lower four bits of the carry flag C carry flag C Set to F.
  • the lower four bits of the borrow are set in the carry flag CF.
  • the amp operation 4-bit operation
  • the function expands the data on the 8-bit register into the 16-bit register in the evening as shown in Fig. 10.
  • the processing is “UN” in this embodiment.
  • PACK "instruction.
  • the pack packs (reversely expands) the 16-bit register data on the 8-bit register as shown in Figure 11 on the 8-bit register. This packing process is performed by an "UNP ACK" instruction or the like in the present embodiment.
  • the key input and the like are input to the RAM 36, and the data structure at that time is, as shown in FIG. 15, the address "0000X” is the addition term word as shown in FIG. It is a query, and the address “0 0 IX” is a work area to be added.
  • the point indicated by reference numeral 60 is the boundary of the decimal point
  • 61 is the first decimal place
  • 62 is the second decimal place
  • 63 is the decimal point.
  • the seventh is shown respectively.
  • 64 indicates the “1” digit
  • 65 indicates the 100,000 digit
  • 66 indicates the 1,000,000 digit
  • 67 indicates the key input value. This area is used to store the position of the decimal point at the time of import.
  • the initial value of 1 X is “0000E”, where “0000” D ”and the digit position is one digit lower. Increment the digit counter by one (S29). "1" is set to the significant digit flag (S30).
  • M (0000F) is set to the value of M (0000F) — 1 and M (0000F) was "4", so it is "3" here. You. As described above, the value of M (0000F) is reduced by "1", and the process is repeated until the value of M (0000F) becomes zero (S50). When the value of M (0000F) becomes zero, the state shown in Fig. 16C is reached, and the decimal point alignment is completed.
  • the above 46 and 60 are examples of machine code.
  • the internal bus is a powerful 16-bit configuration, and only the lower 8 bits (I ⁇ 07 to 00) are used in the above instruction. Use and reduce execution cycles
  • the internal structure of CPu is composed of multiple bus lines (internal bus and external bus). The execution of this instruction is processed at the timing shown in the timing chart shown in FIG.
  • each instruction of the micro-instruction group for the data path is as follows.
  • UILVEB Transfer from lower internal bus to external bus
  • UEBIL Transfer from lower external bus to lower internal bus
  • UAVIL Read from A register to lower internal bus
  • UILVA Internal bus lower power, write to A register UWITHC: Carry flag power, write to temporary carrier flag
  • the addition instruction (ADD instruction) is as shown in FIG.
  • the temporary register “A” (TA) stores “19” in the lower eight bits, and the temporary register.
  • Register B (TB) stores "58" in the lower 8 bits. Then, both of them are added to the temporary flag TC, and the 16-bit adder output CAL is output to the decimal output register. Make an input to the knock logic. Decimazorea Just Finale Amp In the clock, BCD correction and unpack correction are performed, the output DAF is as shown in the figure, and the calculation output is “0 ⁇ 0100”. "1" is set in the carry flag CF.
  • each digit of the input data is stored in one-address units in decimal notation.
  • the position of the decimal point between the addition term and the augmented term can be easily adjusted.
  • addition of each digit can be output in one-digit decimal system (BCD, 4 bits), and the addition of the one digit is an overflow. Since it can be reflected in the carry flag CF, carry processing to the upper digit can be easily performed.
  • the program is executed by executing a pack instruction (PACK instruction) to store the data. This can save space.
  • PACK instruction pack instruction
  • Temporary register A stores B, A, and force as 16-bit data. “0000H” is stored in B (TB). Then, when the two are added, a 16-bit adder output CAL is obtained. Entered in 2.
  • the output DAF is as shown in the figure, and the lower 4 bits of data, the 9th power of the output CAL, and the 12th bit of data are output. No ,. And obtained as the output of ALU22. Therefore, the lower 8 bits of the output of ALU 22 are treated as valid data and stored in RAM 36, but the upper 8 bits are treated as invalid data. .
  • an unpacking instruction (UNP ACK instruction) is executed by the program.
  • a numerical value of 65 will be explained as an example.
  • Temporary register A stores the value of ⁇ 0H '' in the upper part and the value of register A in the lower part.
  • "0000H” is stored in the evening B (TB).
  • Addition of the two results in a 16-bit Atsuta output CAL, which is a digital filter, a digital filter, and a logic filter. Input to the circuit.
  • the output DAF is as shown in the figure, and the lower 4 bits of data remain the same as the lower 4 bits of the ALU output, and the next 4 bits are output. "0H” is introduced. In the next 4 bits, the data of the upper 4 bits of the DAF output is output, and in the next 4 most significant bits, “0H” is inserted. . In this way, the unpacked data "0605" is obtained.
  • FIGS. 21A to 29 The specific circuit configuration of ALU22 is as shown in FIGS. 21A to 29.
  • FIG. FIGS. 21A and 21B are ALU wiring diagrams.
  • FIGS. 22A and 22B are 16-bit atlas circuits, and
  • FIG. 23 is a decimal adjuster. Evening ⁇ Anno.
  • FIG. 24 is a circuit diagram showing the configuration of a clock logic circuit
  • FIG. 24 is an ALU shifter
  • FIG. 25 is a circuit diagram showing each configuration of a control flag.
  • FIGS. 26 to 29 are specific circuit diagrams of the latches constituting the control flag shown in FIG.
  • FIG. 25 corresponds to the FLAG block of FIG. 21B
  • FIG. 21B corresponds to the condition flag 26 of FIG.
  • Figure 26 is a circuit diagram of the zero-flag, over-flag, and negative flag grabbers.
  • Figure 27 is a circuit diagram of the 2-bit interrupt flag latch
  • Figure 28 is a circuit diagram of the carry flag latch
  • Figure 29 is a decimal flag. This is the circuit diagram of the amp flag latch section.

Abstract

L'invention concerne un dispositif à semi-conducteur pouvant traiter facilement des données de longueur différente, ainsi qu'un agencement électronique incorporant ce dispositif à semi-conducteur. Le dispositif à semi-conducteur comprend des moyens d'entrée pour extraire des données d'entrée non condensées, un registre ayant un indicateur à établir lors du traitement des données non condensées, et une unité arithmétique et logique (ALU) pouvant traiter des données de longueur différente. Lorsque l'indicateur est réglé sur le registre ci-dessus et que l'instruction en cours indique un traitement de données de courte longueur, l'unité arithmétique et logique traite des données ayant une longueur égale à la moitié de la longueur des données d'entrée et établit un signal de report pour des bits d'ordre supérieur des données sur un indicateur de report. Par exemple, même lorsque l'unité arithmétique et logique possède la fonction de traiter des données de 16 bits et de 8 bits, elle est capable de traiter des données de 4 bits lorsque le traitement de données de 8 bits est sélectionné et un indicateur d'éclatement est établi.
PCT/JP1991/001496 1990-11-02 1991-11-01 Dispositif a semi-conducteur WO1992008188A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP29767790 1990-11-02
JP2/297677 1990-11-02

Publications (1)

Publication Number Publication Date
WO1992008188A1 true WO1992008188A1 (fr) 1992-05-14

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7966482B2 (en) 1994-12-02 2011-06-21 Intel Corporation Interleaving saturated lower half of data elements from two source registers of packed data

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6222144A (ja) * 1985-07-23 1987-01-30 Nec Corp １０進演算回路
JPS63175927A (ja) * 1987-01-12 1988-07-20 アメリカン　テレフオン　アンド　テレグラフ　カムパニ− 二進化十進／パックドデ−タの処理方法および処理装置
JPS6462726A (en) * 1987-09-03 1989-03-09 Fujitsu Ltd Adder-subtracter
JPS6462727A (en) * 1987-09-03 1989-03-09 Fujitsu Ltd Adder-subtracter

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6222144A (ja) * 1985-07-23 1987-01-30 Nec Corp １０進演算回路
JPS63175927A (ja) * 1987-01-12 1988-07-20 アメリカン　テレフオン　アンド　テレグラフ　カムパニ− 二進化十進／パックドデ−タの処理方法および処理装置
JPS6462726A (en) * 1987-09-03 1989-03-09 Fujitsu Ltd Adder-subtracter
JPS6462727A (en) * 1987-09-03 1989-03-09 Fujitsu Ltd Adder-subtracter

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7966482B2 (en) 1994-12-02 2011-06-21 Intel Corporation Interleaving saturated lower half of data elements from two source registers of packed data
US8190867B2 (en) 1994-12-02 2012-05-29 Intel Corporation Packing two packed signed data in registers with saturation
US8495346B2 (en) 1994-12-02 2013-07-23 Intel Corporation Processor executing pack and unpack instructions
US8521994B2 (en) 1994-12-02 2013-08-27 Intel Corporation Interleaving corresponding data elements from part of two source registers to destination register in processor operable to perform saturation
US8601246B2 (en) 1994-12-02 2013-12-03 Intel Corporation Execution of instruction with element size control bit to interleavingly store half packed data elements of source registers in same size destination register
US8639914B2 (en) 1994-12-02 2014-01-28 Intel Corporation Packing signed word elements from two source registers to saturated signed byte elements in destination register
US8793475B2 (en) 1994-12-02 2014-07-29 Intel Corporation Method and apparatus for unpacking and moving packed data
US8838946B2 (en) 1994-12-02 2014-09-16 Intel Corporation Packing lower half bits of signed data elements in two source registers in a destination register with saturation
US9015453B2 (en) 1994-12-02 2015-04-21 Intel Corporation Packing odd bytes from two source registers of packed data
US9116687B2 (en) 1994-12-02 2015-08-25 Intel Corporation Packing in destination register half of each element with saturation from two source packed data registers
US9141387B2 (en) 1994-12-02 2015-09-22 Intel Corporation Processor executing unpack and pack instructions specifying two source packed data operands and saturation
US9182983B2 (en) 1994-12-02 2015-11-10 Intel Corporation Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers
US9223572B2 (en) 1994-12-02 2015-12-29 Intel Corporation Interleaving half of packed data elements of size specified in instruction and stored in two source registers
US9361100B2 (en) 1994-12-02 2016-06-07 Intel Corporation Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements
US9389858B2 (en) 1994-12-02 2016-07-12 Intel Corporation Orderly storing of corresponding packed bytes from first and second source registers in result register

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