Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
  • G06T1/00—General purpose image data processing
  • G06T1/60—Memory management
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
  • G06V30/00—Character recognition; Recognising digital ink; Document-oriented image-based pattern recognition
  • G06V30/10—Character recognition
  • G06V30/18—Extraction of features or characteristics of the image
  • G06V30/18086—Extraction of features or characteristics of the image by performing operations within image blocks or by using histograms
  • G06V30/18095—Summing image-intensity values; Projection and histogram analysis
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
  • G06V30/00—Character recognition; Recognising digital ink; Document-oriented image-based pattern recognition
  • G06V30/10—Character recognition

Definitions

• the invention relates to a circuit arrangement for processing pixel data in automatic character recognition according to the preamble of patent claim 1.
• a document is resolved into biic points by scanning, and the associated pixel cates are stored in a memory.
• the reading out of the stored fixed data from the memory, their processing and a possibly necessary writing back of the data are usually triggered and controlled by a central processing unit.
• the time required by such a system to process the pixel data associated with a document is unpredictable in individual cases due to the greatly differently designed templates and the complex recognition processes, which are not limited to standard fonts, for example, and can vary over large areas. Coupling the system with input units with high throughput, for example high-speed document sorters, can result in bottlenecks in the processing of the incoming documents, which can result in the document being rejected even before the recognition process begins.
• the present invention is therefore based on the object of designing a circuit arrangement of the type mentioned at the outset in such a way that the fastest possible processing of the pixel data associated with a document is ensured.
• a control unit is provided in an address arithmetic unit, with which independent processing of pixel data can be achieved in parallel with the processing unit. It contains a memory device for receiving the commands provided for the execution of a given function.
• the control unit has access to a parameter memory, consisting of memory devices connected in parallel for the separate storage of the horizontal and vertical address parameters, with which the addressing and reading of any data in a limited
• Pixel field of memory is guaranteed.
• the advantage of such an arrangement is that the processing unit is released from an essential part of its tasks.
• the pixel data read out on the basis of the working memory addresses calculated in the address arithmetic unit are entered in a separate register, wherein individual pixel values can be selected and forwarded to an evaluation unit for performing a predetermined function.
• Further developments of the invention relate to the arithmetic units, in which a plurality of registers are arranged, which can be loaded from the respectively associated memory devices of the parameter memory with address parameters corresponding to the function to be carried out or whose entries can be written back to them.
• the evaluation unit has registers in which the end addresses for the horizontal and vertical limits of the pixel to be read out are stored, so that the readout of pixel data for the current function is terminated in accordance with the working memory addresses created by the address processor.
• the sequence of the pixel processing for a function to be carried out independently by the control unit can be determined depending on signals from the evaluation unit or on the individual pixel value selected in each case during an addressing process.
• FIG. 1 shows the block diagram of an n circuit arrangement designed according to the invention.
• a processing unit SPU e.g. In the form of a signal processor, an address arithmetic unit ARW and a working memory ASP form the general structure of a script reading system for reading out and processing data which are obtained by scanning an existing document and stored as information pixels.
• the processing unit SPU has access to all data entered in the main memory ASP, including the pixel data mentioned, via its own address and data paths, which are not specifically drawn in the block diagram.
• a control unit MIC and a parameter memory PSP are coupled to the processing unit SPU in the address computing unit ARW.
• the control unit MIC has memory devices for receiving commands which are transferred by the processing unit SPU to perform a specific function, for example to find related areas on the document.
• the parameters belonging to the commands for example starting addresses for controlling the working memory ASP, step sizes for calculating the sequence addresses, etc., form the entries in the parameter memory PSF, which has a comparatively small storage capacity but a short access time.
• the processing unit SPU initiates an address calculation, the execution of the specified function is handled independently by the control unit MIC as part of the address arithmetic unit ARW.
• the pixel processing begins with the addressing of pixel data ADAT in the working memory ASP.
• the address calculation is carried out in accordance with a pixel field extended in the horizontal and vertical directions, each with an arithmetic unit RWH or RWV, which is connected downstream of the assigned memory devices PSPH or PSPV.
• Each of the two arithmetic units RWH or RWV has an input register DRH or DRV, in which the step size for the exact setting of the next working memory address AD-H or AD-V is stored.
• a device ADD is provided for each arithmetic logic unit RWH or RWV, in which the previously valid working memory address AD-H or AD-V stored in the exit register AKR is summed with the current step size stored in the input register DRH or DRV becomes.
• the parameter memory PSP with its memory devices PSPH and PSPV can not only be loaded with parameter data by the processing unit SPU, but also, if necessary, also receives calculated addresses from the battery registers AKR or data ADAT, which are read out from the working memory ASP. Its individual entries are selected by creating an address PAD generated by the control unit MIC and temporarily stored in an address register ADR.
• control unit MIC accesses the pixel field limited in the horizontal and vertical directions, it is necessary for each reading process that the current working memory addresses AD-H and AD-V are compared with end addresses PAR-H and PAR-V for both directions.
• the memory addresses AD-H and AD-V reach an evaluation unit AWE with comparison devices COMP arranged therein via a line system AEUS.
• the end addresses PAR-H and PAR-V required for the comparison are read out from the parameter memory PSP and, after transmission via the ABUS line system, written into the registers CRH and CRV.
• Individual outputs of the comparison devices COMP are connected to a control unit STC connected upstream of the control unit MIC, which, depending on the incoming evaluation signals CSH and CSV, forms a control signal for determining the further command sequence in the control unit MIC.
• the pixel data ADAT for example consisting of a data word with a defined bit width, are addressed in the working memory ASP and written into a separate register PIXR via a further line system DBUS.
• a single pixel value PIX0 / 1 in the register PIXR can be specified for a subsequent query in the control unit STC by means of a partial address PIXA, which is formed from a part of the working memory address AAD. In this way it can be determined whether it is a white (PIX0) or black pixel (PIX1).
• register PIXR there is also the option of value in register PIXR to black or white, and write the modified data word ADAT back to the same memory location selected by the address AAD.
• Another application of the specification of a single pixel value is that a pixel value located in the middle of a subfield picked out from the entire pixel field can be determined.
• each individual pixel value PIX0 / 1 of the subfield is fed to a counter circuit ZWS in the evaluation unit AWE, which consists, for example, of a counter, an adder and several registers.
• the total value of all black pixels (PIX1) and a threshold value loaded from the parameter memory PSP into the register CRV form the signals to be compared with one another in the comparison device COMP. If the value falls below the comparison value, the
• PIXR a white pixel (PIX0) for the value to be determined, otherwise a black pixel (PIX1) is entered.
• control unit MIC for example the finding of a character on an existing document.
• the output registers AKR of the arithmetic units RWH and RWV are used for the control of the working memory ASP
• the working memory addresses AD-H and AD-V cause the pixel data ADAT to be read out, with a single pixel value PIX0 / 1 being selected by a part PIXA of the address bits AAD at the same time as the readout process, and then in the control device STC for the presence of one
• start addresses are increased by the address increments loaded by the control unit MIC into the input registers DRH and DRV, and the next pixel data including the defined pixel value based on the current working memory addresses AD-H and AD-V. This is followed by the query in the control device STC, which sends a control signal for the further command sequence to the control unit MIC.
• the accumulation process for the addresses is repeated until a single pixel value represents a black pixel (PIX1), unless the limits of the pixel field, recognizable by the evaluation signals CSV or CSH, have been reached, which means that the P-ixel processing is terminated has a negative result for the function to be performed.
• the addresses AD-H and AD-V of the first black pixel (PIX1) found in the output registers AKR are written into the associated parameter memories PSPH and PSPV.
• the surroundings of the black pixel are examined for the presence of further black pixels.
• the control unit MIC in turn loads the address increments into the registers DRH and DRV according to the position of the neighborhood pixels to be examined.
• further data with a selected pixel value PIX0 / 1 can be called up from the working memory ASP.
• the addresses AD-H and AD-V of each black pixel (PIX1) of the environment found lead to further entries in the corresponding parameter memories PSPH and PSPV.
• control addresses AD-H and AD-V are transmitted via a separate data path DAD to the working memory ASP, in which the working memory addresses that only concern black pixels (PIX1) are then finally stored.
• the character to be found can be reconstructed from the addresses finally stored in the working memory ASP for the individual pixel data including the specified pixel values (PIX1).
• the stored parameter values can be entered in the working memory ASP.
• Another example of the processing of read-out pixel data in the context of automatic character preparation is the so-called line-edge smoothing, in which the mean pixel value of a sub-pixel field by counting the surrounding black pixels (PIX1) in the circuit ZWS to black (PIX1) or white ( PIX0) is set.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Computer Vision & Pattern Recognition (AREA)
• Multimedia (AREA)
• Character Input (AREA)

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Citations (2)

• 1991
  • 1991-09-26 WO PCT/EP1991/001835 patent/WO1992006443A1/de unknown

Patent Citations (2)

Non-Patent Citations (1)

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