WO1992004709A1 - Adressage par coordonnees de cellules a cristaux liquides - Google Patents

Adressage par coordonnees de cellules a cristaux liquides Download PDF

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Publication number
WO1992004709A1
WO1992004709A1 PCT/GB1991/001536 GB9101536W WO9204709A1 WO 1992004709 A1 WO1992004709 A1 WO 1992004709A1 GB 9101536 W GB9101536 W GB 9101536W WO 9204709 A1 WO9204709 A1 WO 9204709A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixels
liquid crystal
refreshing
ordinate
states
Prior art date
Application number
PCT/GB1991/001536
Other languages
English (en)
Inventor
William Alden Crossland
Martin John Birch
Original Assignee
Northern Telecom Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Limited filed Critical Northern Telecom Limited
Priority to JP03515534A priority Critical patent/JP3105248B2/ja
Priority to DE69116694T priority patent/DE69116694T2/de
Priority to EP91916345A priority patent/EP0548179B1/fr
Publication of WO1992004709A1 publication Critical patent/WO1992004709A1/fr
Priority to US08/739,811 priority patent/US5774104A/en

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3651—Control of matrices with row and column drivers using an active matrix using multistable liquid crystals, e.g. ferroelectric liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels

Definitions

  • This invention relates to the co-ordinate addressing of liquid crystal cells.
  • Co-ordinate addressing of such cells can be achieved by methods in which each pixel is defined as the area of overlap between one member of a set of row electrodes on one side of the liquid crystal layer and one member of another set of column electrodes on the other side.
  • the liquid crystal is backed by 'an active back-plane' which has a co-ordinate array of electrode pads which are addressed on a co-ordinate basis within the active back-plane, and electrical stimuli are applied to the liquid crystal layer between individual members of this set of electrode pads on one side of the liquid crystal layer and a co-operating front-plane electrode on the other side of the liquid crystal layer.
  • the front-plane electrode is a single electrode, but in some instances it may be subdivided into a number of electrically distinct regions.
  • the active back-plane may be constructed as an integrated single crystal structure, fcr instance cf silicon.
  • This invention relates in particular to the active back-plane addressing of liquid crystal cells whose response to an electrical stimulus is sensitive to the polarity of that stimulus.
  • any particular pixel of a co-ordinate array of pixels is identified by its row and column co-ordinates.
  • rows and columns are respectively identified as horizontally-extending and vertically-extending lines; in this instance these terms are employed in a wider sense that does not imply any particular orientation of the row and column lines with respect to the horizontal, but merely that the sets of row and column lines intersect each other.
  • a method of addressing a liquid crystal cell having a coordinate array of pixels wherein data for refreshing the cell is applied at each refreshing in two sequential stages in one of which the pixels are individually set to their required states and in the other of which they are set to the inverse of their required states, whereby the second stage operates substantially to cancel charge imbalances applied across individual pixels in the first stage.
  • the inventional further provides a method of co-ordinate refreshing a liquid crystal cell that includes a liquid crystal layer which by the application of oppositely directed electric potential differences across the thickness of the layer is enabled to be switched between two states, which cell is switchable between said two states using an active back-plane provided with a co-ordinate array of electrode pads on one side of the liquid crystal layer, which pads co-operate with a front-plane electrode on the other side of the liquid crystal layer to define an associated co-ordinate array of pixels within the liquid crystal layer, wherein each time the pixels of the co-ordinate array are refreshed such refreshing is performed in two sequential stages that co-operate to preserve substantial charge balance across each individual pixel of the array, in one of which stages the pixels are set to their required states, and in the other of which stages the pixels are set into their opposite states.
  • pixels scheduled for refreshing into one state may be set into that state by applying to their electrode pads a potential of +V/2 with respect to the potential of the front-plane electrode.
  • pixels scheduled for refreshing into the other state may be set into that other state by applying to their electrode pads a potential -V/2.
  • the application of these potentials necessarily creates a charge imbalance across individual pixels, and if refreshing were to be carried out as a single operation not involving the setting up of the inverse display in which all pixels are set to the opposite of their scheduled states, it is evident that repetitive refreshing in which any given pixel is consistently set to the same state is necessarily going to give rise to cumulative charge imbalance.
  • Cumulative charge imbalance is also going to similarly arise if the single stage refreshing (that does not involve the setting up of the inverse display) is performed by a refreshing operation that commences with a blanking operation in which the potential of the electrode pads of all pixels are taken to a potential +V with respect to the front-plane electrode prior to taking the potential of the electrode pads of selected pixels to a potential -V with respect to the front-plane electrode.
  • the problem of cumulative charge imbalance is however capable of being overcome by adopting the two stage refreshing process of the present invention in which a stage that involves the setting up of the pixels into their required states is preceded or followed by a stage in which they are set up into states that are the inverse of the required states.
  • a stage that involves the setting up of the pixels into their required states is preceded or followed by a stage in which they are set up into states that are the inverse of the required states.
  • use may be confined to those periods in which the 'required states' display is being displayed, or use may also be made of the periods in which the 'inverse' display is being displayed, taking additional steps to invert the inverse.
  • Figure 1 is a block-diagram of a back-plane co-ordinate addressed liquid crystal device.
  • Figure 2 depicts a schematic cross-section of the liquid crystal cell of the device of Figure 1
  • Figure 3 is a diagram of the pixel pad addressing arrangement.
  • a data processor 10 receives incoming data over an input line 11, and controls the operation of row and column addressing units 12 and 13 which provide inputs on lines 14 and 15 to the electrodes of a back-plane co-ordinate addressed liquid crystal cell 16 with pixels arranged in a co-ordinate array of n rows and m columns.
  • a hermetic enclosure for a liquid crystal layer 20 (Figure 2) is formed by securing a transparent front sheet 21 with a perimeter seal 22 to a back sheet 23. Small transparent spheres (not shown) of uniform diameter may be trapped between the two sheets 21 and 23 to maintain a uniform separation, and hence uniform liquid crystal layer thickness.
  • the front sheet 11 On its inward facing surface, the front sheet 11 earries a transparent electrode layer 24, the front-plane electrode layer, while a co-ordinate array of pixel pad electrodes 25 are similarly carried on the inward facing surface of the back sheet 23. These two inward facing surfaces are treated to promote a particular molecular alignment of the liquid crystal molecules in contact with these surfaces in the same direction.
  • the back sheet 23 constitutes an active back-plane, by means of which the pixel pads 25 may be individually addressed on a row by row basis. Within its active structure, which may for instance be constructed in single crystal silicon, it contains the row and column addressing 12 and 13 units ( Figure 1), and may additionally contain the data processor 10. The area of overlap between the front-plane electrode layer 24 and an individual pixel pad 25 defines a pixel of the cell.
  • the liquid crystal layer 20 is composed of a ferroelectric chiral s ectic C material.
  • the thickness of the layer 20 is equal to an odd number of quarter wavelengths divided by the birefringence of the liquid crystal material, and it is viewed through a polariser (not shown).
  • a single gate 30 is associated with each pixel electrode pad 25. All the m gates of a row of pixel electrode pads are enabled by the application of a suitable potential to a row electrode 31 associated with that row. The gates 30 are enabled in row sequence using a strobing pulse applied in turn to the n row electrodes 31 from the row addressing unit 12. Enablement of each row of gates 30 serves to connect each pixel electrode pad of that row with an associated column electrode 31 connected to the column addressing unit 13.
  • Refresh rows of data are entered in row sequence into a single bit m-stage shift register (not separately illustrated) in the column address unit 13 under the control of the data processor 10.
  • a logic unit (not separately illustrated) which determines whether the associated column electrode 32 shall be connected to a voltage rail (not separately illustrated) held at a potential +V/2 with respect to the potential of the front-plane electrode 24, or to a voltage rail (not separately illustrated) held at a potential -V/2. While the refresh line of data is held in the shift register, the data processor 10 causes the row address unit to supply a strobe pulse to the relevant row electrode 31.
  • each individual pixel is subjected to a potential difference for a certain period of time special to that row, first in one direction, and then later, for an equal period of time, to an equivalent oppositely directed potential difference.
  • the front-plane electrode 24 is at ail times maintained at a constant potential, and that the voltage rails of the column address unit are maintained equally positive and negative with respect to that fixed voltage. If the construction of the back-plane sheet 23 is such that it is able to drive pixel electrode pads 25 within the voltage range from 0 volts to V volts, then, if the front-plane electrode is to be maintained at a fixed potential, the fixed potential is preferably V/2 so as to allow a maximum potential difference of ⁇ V/2 or -V/2 to be developed across any pixel. A larger potential difference can be developed if the potential of the front-plane electrode is allowed to change.
  • the front-plane electrode potential is changed from +V to 0 volts ready for selected pixels to be set to the opposite state row-by-row in the continuation of this stage.
  • the second stage commences with blanking all the pixels by setting them all to the same state as the selected pixels, then, with the front-plane electrode potential once again restored from 0 volts to +V, the second stage continues with the setting row-by-row of the selected pixels back to the other state.
  • a matrix vector multiplier for instance for use as an optical cross-bar switch.
  • a columnar array of n optical sources is optically arranged relative to the pixels of the co-ordinate array of the cell so that the p element of the column of sources is optically coupled with all m pixels of the p row of the co-ordinate array
  • a row array of m optical detectors is optically arranged relative to the pixels so that all n pixels of the r column of the co-ordinate array are optically coupled with the r element of the row of detectors.
  • a polarisation beam splitter is employed in the optical coupling of the sources and detectors with the co-ordinate array in order to provide the dual function of separating the input and output beams and of providing the necessary polariser for operation of the device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

Dans une cellule à cristaux liquides adressée par coordonnées et à plan de fond actif, dont les pixels sont mis dans un état par l'application d'un potentiel unidirectionnel sur l'épaisseur de la couche de cristaux liquides et dans l'état opposé si la direction du potentiel appliqué est inversée, la régénération est effectuée en deux étapes séquentielles afin d'éviter les effets de déséquilibre dus à la charge cumulative. Au cours d'une étape on met les pixels dans leurs états requis, alors qu'au cours de l'autre étape on les met dans les états inverses.
PCT/GB1991/001536 1990-09-11 1991-09-10 Adressage par coordonnees de cellules a cristaux liquides WO1992004709A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP03515534A JP3105248B2 (ja) 1990-09-11 1991-09-10 液晶セルの座標アドレス
DE69116694T DE69116694T2 (de) 1990-09-11 1991-09-10 Adressierung von einer flüssigkristall-anzeigematrix
EP91916345A EP0548179B1 (fr) 1990-09-11 1991-09-10 Adressage par coordonnees de cellules a cristaux liquides
US08/739,811 US5774104A (en) 1990-09-11 1996-10-30 Co-ordinate addressing of liquid crystal cells

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9019883.9 1990-09-11
GB9019883A GB2247974B (en) 1990-09-11 1990-09-11 Co-ordinate addressing of liquid crystal cells

Publications (1)

Publication Number Publication Date
WO1992004709A1 true WO1992004709A1 (fr) 1992-03-19

Family

ID=10682048

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1991/001536 WO1992004709A1 (fr) 1990-09-11 1991-09-10 Adressage par coordonnees de cellules a cristaux liquides

Country Status (5)

Country Link
EP (1) EP0548179B1 (fr)
JP (1) JP3105248B2 (fr)
DE (1) DE69116694T2 (fr)
GB (1) GB2247974B (fr)
WO (1) WO1992004709A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0548180B1 (fr) * 1990-09-11 1996-04-24 Nortel Networks Corporation Adressage par coordonnees de cellules a cristaux liquides
GB2329035A (en) * 1997-09-08 1999-03-10 Central Research Lab Ltd Liquid crystal display with an integrated circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9827945D0 (en) 1998-12-19 1999-02-10 Secr Defence Method of driving a spatial light modulator

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0199361A2 (fr) * 1985-04-26 1986-10-29 Matsushita Electric Industrial Co., Ltd. Circuit de commande pour un dispositif d'affichage à cristaux liquides
EP0371665A1 (fr) * 1988-11-18 1990-06-06 SHARP Corporation Dispositif d'affichage et méthode de contrôle d'un affichage
WO1990007768A1 (fr) * 1988-12-29 1990-07-12 Honeywell Inc. Systeme d'attaque d'affichage a cristaux liquides exempt de scintillement

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2173336B (en) * 1985-04-03 1988-04-27 Stc Plc Addressing liquid crystal cells
GB2173629B (en) * 1986-04-01 1989-11-15 Stc Plc Addressing liquid crystal cells
GB2247972B (en) * 1990-09-11 1994-07-27 Stc Plc Co-ordinate addressing of liquid crystal cells

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0199361A2 (fr) * 1985-04-26 1986-10-29 Matsushita Electric Industrial Co., Ltd. Circuit de commande pour un dispositif d'affichage à cristaux liquides
EP0371665A1 (fr) * 1988-11-18 1990-06-06 SHARP Corporation Dispositif d'affichage et méthode de contrôle d'un affichage
WO1990007768A1 (fr) * 1988-12-29 1990-07-12 Honeywell Inc. Systeme d'attaque d'affichage a cristaux liquides exempt de scintillement

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0548180B1 (fr) * 1990-09-11 1996-04-24 Nortel Networks Corporation Adressage par coordonnees de cellules a cristaux liquides
GB2329035A (en) * 1997-09-08 1999-03-10 Central Research Lab Ltd Liquid crystal display with an integrated circuit
GB2329035B (en) * 1997-09-08 2000-03-08 Central Research Lab Ltd An opitical modulator and integrated circuit therfor
US6630919B1 (en) 1997-09-08 2003-10-07 Central Research Laboratories Limited Optical modulator and integrated circuit therefor

Also Published As

Publication number Publication date
EP0548179A1 (fr) 1993-06-30
JP3105248B2 (ja) 2000-10-30
JPH06501568A (ja) 1994-02-17
EP0548179B1 (fr) 1996-01-24
DE69116694T2 (de) 1996-05-30
GB9019883D0 (en) 1990-10-24
GB2247974A (en) 1992-03-18
GB2247974B (en) 1994-07-27
DE69116694D1 (de) 1996-03-07

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