WO1992003843A1 - Procede de fabrication de condensateurs et de resistances polycristallins pour circuits integres et circuit integre obtenu au moyen dudit procede - Google Patents

Procede de fabrication de condensateurs et de resistances polycristallins pour circuits integres et circuit integre obtenu au moyen dudit procede Download PDF

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Publication number
WO1992003843A1
WO1992003843A1 PCT/CA1991/000277 CA9100277W WO9203843A1 WO 1992003843 A1 WO1992003843 A1 WO 1992003843A1 CA 9100277 W CA9100277 W CA 9100277W WO 9203843 A1 WO9203843 A1 WO 9203843A1
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WO
WIPO (PCT)
Prior art keywords
poly layer
layer
regions
poly
capacitor
Prior art date
Application number
PCT/CA1991/000277
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English (en)
Inventor
François CORDEAU
Gord Harling
Original Assignee
Mitel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitel Corporation filed Critical Mitel Corporation
Publication of WO1992003843A1 publication Critical patent/WO1992003843A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

Definitions

  • This invention relates to a method of manufacturing double poly capacitors in integrated circuits, and integrated circuits manufactured thereby.
  • Double poly capacitors i.e. capacitors consisting a pair of opposed electrodes made of polycrystalline silicon, are widely used in integrated circuit manufacturing, especially in analog applications and for switched capacitor circuits.
  • the use of two poly layers to fabricate capacitors is well known and has been used since the first 5 micron process became known about ten years ago.
  • the first poly layer is heavily doped, either with P0C1 3 , ion implantation, or during deposition (In-Situ Doped) .
  • An oxide is then thermally grown on top of the first poly layer (Poly I) to form the capacitor dielectric.
  • a second poly layer is deposited to form the top electrode of the capacitor. If a resistive film is required to fabricate small resistors, this second layer is lightly doped .
  • lightly doped poly II is advantageous in providing very linear resistors that are small, compared to other materials.
  • the voltage coefficient of the double-poly capacitor produced by this method is large because of the difference in doping levels between the two poly layers.
  • An object of the invention is to alleviate the aforementioned problem.
  • the present invention provides a method of manufacturing integrated circuits including transistors, capacitors, and resistors, comprising the steps of forming a first poly layer, which is heavily doped; forming a dielectric layer over said first poly layer; forming a second poly layer over said dielectric layer, said second poly layer being lightly doped; and subsequently further doping said second poly layer at least in capacitor regions while masking said second poly layer in resistor regions so as to heavily dope said second poly layer in said capacitor regions and thereby improve capacitor linearity while substantially maintaining the resistivity of said lightly doped second poly layer in said resistor regions.
  • the heavily doped Poly I layer has a sheet resistance R s between 15 and 30 ohms/square for a thickness of 330 nm.
  • the lightly doped Poly II layer has a sheet resistance R s at least 50 and up to 500 or more ohms/square for a thickness of 250 nm.
  • a layer of refractory metal silicide can be formed on top of the first poly layer.
  • the dielectric is then grown and/or deposited on the refractory layer depending on the type of material used on top of the first poly layer.
  • the subsequent doping takes place through a mask with windows opened in the capacitor regions, the mask being the same mask that is used to fabricate the source and drain regions of the integrated circuit.
  • the contact regions for the small area resistors can also be heavily doped in the same step to improve contact resistance.
  • the invention allows the use of a second lightly doped poly layer, which gives a much improved voltage coefficient of the double poly capacitor and a much lower contact resistance for the resistors.
  • the invention provides an integrated circuit including transistors, capacitors, and resistors, comprising a first poly layer, which is heavily doped; a dielectric layer on said first poly layer; a second poly layer on said dielectric layer, said second poly layer being lightly doped in resistor regions and heavily doped in capacitor regions; whereby capacitor linearity is improved while the resistivity of said lightly doped second poly layer in said resistor regions is substantially maintained.
  • Figure 2 shows a portion of an integrated circuit forming a double poly capacitor
  • Figure 3 shows a portion of an integrated circuit forming a poly resistor.
  • a first poly layer 1 is deposited on an insulator (thick field oxide) 5 which has been previously grown or deposited on a silicon substrate (Filed oxide 5 is omitted in Figures lb to le) .
  • the layer 1 is normally heavily doped during deposition, or can be doped subsequentl .
  • an oxide layer 2 is thermally grown on the first poly layer 1, as shown in Figure lb.
  • the oxide layer serves a dielectric in the finished double poly capacitor.
  • a second poly layer 3 is then deposited undoped on the oxide layer 2.
  • the second poly layer is lightly doped by diffusion, ion implantation, or during deposition (in-situ doped) to yield a high final sheet resistance of about 100 ohms per square, or even greater.
  • the second poly layer 3 is then patterned, as shown in Figure Id, and resist 4 spun onto the wafer in preparation for N + active area implantation to heavily dope the second poly layer 3.
  • the heavily doped N + implantation is normally carried out to form the source and drain regions of the transistors.
  • windows are opened up on top of the second poly layer 3 at locations where it is desired to increase locally the doping level, that is over capacitor areas and where resistor contacts to the second poly layer 3 are to be made ( Figure le) .
  • the resist is retained over the small area resistors in order to mask them during the implantation process.
  • the N + implantation can then be performed selectively to dope simultaneously the N + active area and the upper plate of the double poly capacitors and the regions where metal contacts to the poly II layer are to be made.
  • Figure 2 shows a poly-poly capacitor fabricated in accordance with the method of the present invention.
  • the second poly layer 3 forming one plate of the capacitor, lies above the first poly layer 1 and is separated therefrom by the dielectric (not shown in Fig. 2) .
  • the second poly layer 3 is surrounded by window 3a in the source/drain mask (not shown) through which N + ion implantation is carried out during formation of the source/drain of the integrated circuit. " 'e doping of the second poly layer is enhanced, resulting in increased conductivity and therefore linearity.
  • the second poly layer 3 forms serpentine resistor 3b.
  • a window 3a 1 is formed in the source/drain mask (not shown) through which N + ion implantation is carried out during formation of the source/drain of the integrated circuit to increase the doping of end regions 3b', where metal contacts are to be made.
  • the invention allows double poly capacitors to be fabricated with good linearity without the need to employ an extra mask.
  • the additional benefits in terms of contact resistance can also be obtained without added cost.
  • the second poly layer 3 can be doped with, for example, phosphorous and/or arsenic to provide the light level of doping, and then an N + diffusion implant, using phosphorus and/or arsenic, employed to locally increase the doping level.
  • the second poly layer 3 can be doped with boron, and P + diffusion implant, using boron, BF or BF2-
  • the dielectric layer can be a deposited layer (oxide, or nitrite) , or a combination of thermally grown and deposited layers (thermal oxide/nitrite/oxide) .
  • Rapid thermal processing treatment can be carried out on the thus fabricated wafer to further activate the implanted heavily doped regions in the second poly layer 3.
  • the invention has general application in the doping of poly films and integrated circuits, including MOS and bipolar transistors. It allows a lightly doped second poly layer with high sheet resistance per square to be employed, while giving a low voltage coefficient of the double poly capacitor, a low metal to poly 2 contact resistance without the need for additional processing.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Procédé de fabrication de circuits intégrés comprenant des transistors, des condensateurs et des résistances, qui comporte les étapes suivantes: formation d'une première couche polycristalline (1) à dopage élevé; formation d'une couche diélectrique (2) au-dessus de la première couche polycristalline; formation d'une deuxième couche polycristalline (3) au-dessus de la couche diélectrique, la deuxième couche polycristalline étant légèrement dopée; dopage consécutif et supplémentaire de la deuxième couche polycristalline, au moins dans les régions des condensateurs, tout en masquant la deuxième couche polycristalline dans les régions des résistances afin de doper fortement la deuxième couche polycristalline dans les régions des condensateurs et, de ce fait, augmenter la linéarité desdits condensateurs tout en maintenant ensuite la résistivité de la deuxième couche polycristalline à dopage faible dans les régions des résistances. De cette façon, on peut fabriquer des condensateurs possédant une bonne linéarité en même temps que de petites résistances localisées possédant une bonne résistance de contact.
PCT/CA1991/000277 1990-08-13 1991-08-12 Procede de fabrication de condensateurs et de resistances polycristallins pour circuits integres et circuit integre obtenu au moyen dudit procede WO1992003843A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA 2023172 CA2023172A1 (fr) 1990-08-13 1990-08-13 Methode de fabrication de condensateurs a deux polymeres
CA2,023,172 1990-08-13

Publications (1)

Publication Number Publication Date
WO1992003843A1 true WO1992003843A1 (fr) 1992-03-05

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PCT/CA1991/000277 WO1992003843A1 (fr) 1990-08-13 1991-08-12 Procede de fabrication de condensateurs et de resistances polycristallins pour circuits integres et circuit integre obtenu au moyen dudit procede

Country Status (2)

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CA (1) CA2023172A1 (fr)
WO (1) WO1992003843A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0698923A1 (fr) * 1994-08-19 1996-02-28 Seiko Instruments Inc. Circuit intégré semi-conducteur
EP0700091A3 (fr) * 1994-08-31 1997-05-21 Ibm Configuration compacte d'un condensateur résistance/inducteur intégré

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4209716A (en) * 1977-05-31 1980-06-24 Texas Instruments Incorporated Semiconductor integrated circuit with implanted resistor element in second-level polycrystalline silicon layer
US4455568A (en) * 1981-08-27 1984-06-19 American Microsystems, Inc. Insulation process for integrated circuits
US4577390A (en) * 1983-02-23 1986-03-25 Texas Instruments Incorporated Fabrication of polysilicon to polysilicon capacitors with a composite dielectric layer
EP0183623A2 (fr) * 1984-11-28 1986-06-04 Fairchild Semiconductor Corporation Condensateur de précision du type MOS à forte valeur
US4682402A (en) * 1983-05-16 1987-07-28 Nec Corporation Semiconductor device comprising polycrystalline silicon resistor element

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4209716A (en) * 1977-05-31 1980-06-24 Texas Instruments Incorporated Semiconductor integrated circuit with implanted resistor element in second-level polycrystalline silicon layer
US4455568A (en) * 1981-08-27 1984-06-19 American Microsystems, Inc. Insulation process for integrated circuits
US4577390A (en) * 1983-02-23 1986-03-25 Texas Instruments Incorporated Fabrication of polysilicon to polysilicon capacitors with a composite dielectric layer
US4682402A (en) * 1983-05-16 1987-07-28 Nec Corporation Semiconductor device comprising polycrystalline silicon resistor element
EP0183623A2 (fr) * 1984-11-28 1986-06-04 Fairchild Semiconductor Corporation Condensateur de précision du type MOS à forte valeur

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Extended Abstracts, volume 80-1, May 1980, Princeton (US), C. Simson: "Properties of polycristalline silicon IC resistors", pages 491-493, see the whole article *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0698923A1 (fr) * 1994-08-19 1996-02-28 Seiko Instruments Inc. Circuit intégré semi-conducteur
EP0700091A3 (fr) * 1994-08-31 1997-05-21 Ibm Configuration compacte d'un condensateur résistance/inducteur intégré

Also Published As

Publication number Publication date
CA2023172A1 (fr) 1992-02-14

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