WO1992001287A1 - Device with self-amplifying dynamic mos transistor storage cells - Google Patents

Device with self-amplifying dynamic mos transistor storage cells Download PDF

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Publication number
WO1992001287A1
WO1992001287A1 PCT/DE1991/000502 DE9100502W WO9201287A1 WO 1992001287 A1 WO1992001287 A1 WO 1992001287A1 DE 9100502 W DE9100502 W DE 9100502W WO 9201287 A1 WO9201287 A1 WO 9201287A1
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WO
WIPO (PCT)
Prior art keywords
transistor
memory
gate
self
gst
Prior art date
Application number
PCT/DE1991/000502
Other languages
German (de)
French (fr)
Inventor
Wolfgang Krautschneider
Lothar Risch
Klaus Lau
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to DE59102966T priority Critical patent/DE59102966D1/en
Priority to JP3510021A priority patent/JP3061857B2/en
Priority to EP91911441A priority patent/EP0537203B1/en
Priority to KR1019920703410A priority patent/KR0156233B1/en
Priority to US07/956,896 priority patent/US5327374A/en
Publication of WO1992001287A1 publication Critical patent/WO1992001287A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the invention relates to an arrangement with self-reinforcing dynamic MOS transistor memory cells according to the preamble of claim 1.
  • the invention has for its object to provide an arrangement with self-reinforcing dynamic MOS transistor memory cells of the type mentioned, which is simple in construction, allows short access times, has a low sensitivity to hits by alpha particles and, above all, their cell geometry is scalable without the amount of charge readable on the bit line is significantly reduced.
  • the object is achieved according to the invention by the features specified in the characterizing part of patent claim 1.
  • the advantage that can be achieved with the invention is, in particular, that in the arrangement designed according to the invention with self-amplifying dynamic MOS transistor memory cells, owing to higher capacitance values with the same area requirement and lower leakage current losses, better charge storage behavior is possible than in the beginning cited memory cell. Further advantages are the simple manufacture of the MOS transistor compared to the junction FET and a lower soft error rate due to the lower sensitivity to alpha rays due to a smaller sensitive area compared to the cell area.
  • Claims 2 to 8 are directed to preferred embodiments of the arrangement according to the invention with self-amplifying dynamic MOS transistor memory cells.
  • Figure 1 is a sectional view of two adjacent MOS transistor memory cells of a memory cell arrangement according to the invention with planar transistors and each having an n + n junction as a voltage-dependent
  • FIG. 2 shows a sectional view of a MOS transistor memory cell of a memory cell arrangement according to the invention with planar transistors and a Schottky junction as a voltage-dependent resistor,
  • FIG. 3 shows a sectional illustration of a MOS transistor memory cell of a memory cell arrangement according to the invention with planar transistors and an n + p + -
  • FIG. 4 shows a sectional illustration of a MOS transistor memory cell of a memory cell arrangement according to the invention with a planar selection transistor and a memory transistor in a trench design
  • FIG. 5 shows a sectional illustration of a MOS transistor memory cell of a memory cell arrangement according to the invention with a selection transistor and a memory transistor in a trench design
  • FIG. 6 shows an equivalent circuit diagram of a MOS transistor memory cell of a memory cell arrangement according to the invention
  • FIG. 7 shows a diagram to illustrate the temporal voltage curves when writing information into a memory cell arrangement according to the invention
  • FIG. 8 shows a diagram to illustrate the temporal current and voltage profiles for reading out information from a MOS transistor memory cell of a memory cell arrangement according to the invention.
  • FIG. 1 shows a preferred embodiment of two adjacent MOS transistor memory cells Z and Z 1 according to the invention.
  • the cells Z and Z ' have a p-doped substrate PSUB, which consists, for example, of silicon and is at reference potential.
  • this substrate PSUB there are n + -doped drain regions D and D 1 , n-doped drain-source regions DS and DS 1 and an n + -doped and both storage cells Z and Z 1 common source region S from one surface 0 of the substrate PSUB brought here.
  • the common source region S is connected to one of the two memory cells Z and Z ', a single bit line BL.
  • the two storage cells Z and Z 1 common source region S, the drain-source region DS and the substrate PSUB lying between the two regions S and DS form together with a n + separated by a thin gate oxide GOX from the substrate PSUB -doped gate electrode GAT a selection transistor AT.
  • the drain-source region DS represents the drain region of the selection transistor AT and at the same time forms the source region of the memory transistor ST.
  • the memory transistor ST is formed from the drain-source region DS, a drain region D and an intermediate substrate PSUB together with a n + -doped gate electrode GST of the control transistor ST which is separated from the substrate PSUB by the thin gate oxide GOX .
  • the drain region D is connected to a supply voltage line V and the gate electrode GAT of the selection transistor AT is electrically connected to a word line WL.
  • the gate electrodes de GST of the control transistor ST and the drain-source region DS touch and form an n + n junction 1.
  • FIG. 2 shows a preferred embodiment of a memory cell Z of an arrangement of memory cells with planar transistors in accordance with the invention, the memory cell differing from the memory cell shown in FIG.
  • the Schottky junction 2 is formed here by the n + -doped gate electrode GST and a metal film M.
  • FIG. 3 shows, as in FIGS. 1 and 2, a preferred embodiment of a MOS transistor memory cell in an arrangement of memory cells according to the invention with planar transistors, but in which a polycrystalline or polycrystalline silicided n + gate electrode GST meets a p + region G in order to form a voltage-dependent resistance through an n + p + junction 3.
  • a sufficiently highly doped p + n + junction makes ohmic contact with the source-drain region DS.
  • FIG. 4 Another preferred embodiment of the MOS memory cell of an arrangement according to the invention with memory cells, as shown in FIG. 4, has a planar selection transistor AT and a memory transistor ST in the form of a trench.
  • an n-doped substrate NSUB contains a p-doped region PG lying at reference potential, into which an n-doped drain-source region DS and an n + -doped source region S from the surface 0 are introduced.
  • a planer selection transistor AT is replaced by an n-doped drain-source region DS, a common n + -doped source region S and the p-doped region PG in between, together with one by Thin gate oxide GOX formed from the substrate NSUB and n + -doped gate electrode GAT of the selection transistor AT is formed.
  • the source region S is connected to a bit line BL and the gate electrode GAT of the selection transistor AT is connected to a word line WL.
  • a trench T (trench) is etched into the substrate NSUB, which is slightly deeper than the p-doped region PG.
  • the n-doped substrate NSUB is included connected to the supply voltage line V, so that only the bit and word lines BL and WL arranged in matrix form are required on the chip surface for contacting the cells.
  • An n + -doped gate electrode GST of the control transistor ST is largely laid in the trench T (trench), the gate region GST being separated from the substrate NSUB by a thin gate oxide GOX and lining the trench T. .
  • an electrically conductive region P1 for example made of polycrystalline silicon, which is insulated from the gate region GST by an intermediate oxide ZOX for example at a potential of V DD 2.
  • the gate electrode GST of the control transistor ST and the drain-source region DS touch and thus form an n + n junction 1 a.
  • both a selection transistor AT and a control transistor ST in trench design are implemented.
  • an n + -doped common source region S and an n + -doped drain region D are introduced into a p-doped substrate PSUB from the surface 0 and each extend to the edge of a trench T (trench) .
  • An n-doped drain-source region DS is located directly underneath the trench T, which through a thin gate oxide GOX except for an n + n junction 1b between the gate electrode GST of the memory transistor ST and the drain-source Area DS is lined.
  • the gate electrode GAT of the selection transistor AT In the trench T lined by the thin gate oxide there is also the gate electrode GAT of the selection transistor AT, insulated from the gate electrode GST.
  • the gate electrode GAT of the selection transistor AT is connected to a word line WL and, like the gate electrode GST of the memory transistor ST, is insulated from a trench filling PF made of polycrystalline silicon by an intermediate oxide ZOX on the inside of the trench.
  • the n + -doped drain region D is connected to the supply voltage line V and the n + -doped common source region S is connected to a bit line BL. All combinations between the transitions 1 to 3 and the transistor embodiments planar / planar, planar / trench, trench / planar and trench / trench can be produced.
  • transitions 1 to 3 are shown in FIGS. 1 to 3 only together with a planar / planar transistor design, and in FIGS. 4 and 5 only the transition 1 (la, lb) is shown together with a planar / Trench transistor version and a trench / trench transistor version shown.
  • FIG. 6 The equivalent circuit diagram of a MOS transistor memory cell of an arrangement according to the invention with memory cells is shown in FIG. 6, the components having only secondary or parasitic effects being identified by dashed lines.
  • a bit line voltage U g lies between the reference potential and the bit line BL and the source terminal of the selection transistor AT is connected to a bit line BL, so that a bit line current i ⁇ can flow onto the bit line BL.
  • a word line voltage u w lies between the reference potential and word line WL and the gate connection of the selection transistor AT is electrically conductively connected to a word line WL.
  • the drain terminal of the selection transistor AT has with the source terminal of the memory transistor ST a common drain-source node DSK, which has a voltage-dependent resistor VR, which in turn consists of a resistor R and a diode Di parallel thereto, with the gate of the Memory transistor is connected.
  • the gate of the memory transistor ST has a gate capacitance C ⁇ compared to the reference potential and there is a voltage + Vp D between the supply voltage line V and the reference potential.
  • an additional capacitance C z connected in parallel to the gate capacitance C G can be generated by the plate P1 shown in FIG. Since the substrate NSUB is connected to the supply voltage V DD in FIG. 4, a further additional capacitance C Z2 between the supply voltage line V and the gate of the memory transistor ST must be taken into account here in particular.
  • the transition between the n-doped drain-source region DS and the adjacent p-doped region PSUB or PG represents a polar parasitic diode Di through which a leakage current i L2 flows. In the case of a stored "logic 1" it can be achieved that one flowing to the selection transistor AT
  • Leakage current i. together with the leakage current i. 2 , which flows through the diode Dipn 'corresponds to the amount after a subthreshold current i ⁇ T of the memory transistor ST. If this is the case, the capacitance C effective at the gate of the memory transistor ST cannot discharge to the drain-source node DSK via the voltage-dependent resistor VR and the information of the "logical 1" is retained for a longer time. In the case of a stored "logic 0", the operating point of the memory transistor ST is in the subthreshold range.
  • the subthres ⁇ hold current i ⁇ shifts the potential of the common drain-source node DSK somewhat upwards, until an equilibrium is created by higher leakage currents i and i L2 .
  • a bit line voltage u B and a word line voltage u w which within a time interval t 2 to t 2 are the values u BH , u WH (high) and otherwise assume the values u BL , u WL (low).
  • the applied bit line voltage u ßH (high) but also the bit line voltage Um (low) is read into the MOS transistor memory cell.
  • the voltage-dependent resistor VR has a low resistance value on the order of a few 10 kOh.
  • the selection transistor AT which is driven by u w, is switched through and the bit line BL is thereby connected to the drain-source node DSK t, to t
  • the time integral of ig represents the amount of charge Q available when reading out a “logical 1” (high).
  • a transient current flow through the memory transistor ST and thus also a transient bit line current ig is generated by the fact that the gate potential is temporal delayed follows the source potential of the memory transistor and thereby a gate-source voltage arises which is greater than the threshold voltage of the memory transistor ST.
  • the charge Q consists of the charge of the capacitance C effective at the gate of the memory transistor ST and of the charge which is many times greater, resulting from the drain current of the memory transistor ST.
  • the amount of charge Q is large enough, a voltage pulse on the bit line BL can be detected as "logical 1" for a given bit line capacitance.
  • the channel width and the channel length decrease approximately to the same extent, which results in a largely unchanged drain current through the memory transistor.
  • the time constant T R * C also remains largely unchanged, since the resistance R increases approximately to the same extent as the capacitance C decreases. Due to the largely constant drain current and the time constant T, the available amount of charge Q is largely independent of scaling.
  • the arrangement according to the invention can be constructed not only in n-channel technology, as shown, but also in p-channel technology.
  • the line types have to be exchanged from p to n and vice versa for all doping areas and the signs of the voltages have to be changed.

Abstract

The invention concerns a device with self-amplifying dynamic MOS transistor cells each with an MOS selector transistor (AT), the gate of which is connected to a word line (WL), and an MOS storage transistor (ST) at the gate of which is applied a capacitor (C) for charge storage. This self-amplifying storage cell can be described into and read out with only one bit line (BL) and one word line (WL). The two transistors (AT and ST) are connected in series and a shared drain source region (DS) is connected to the gate electrode (GST) of the control transistor via a voltage-dependent resistor (VR). The main advantages of the invention are that the line geometry can be scaled without reducing the charge quantity (Q) which can be read out from the bit line (BL), that the charge quantity (Q) which can be read out is greater than the charge stored in the capacitor (C) operative at the gate of the storage transistor and that the two MOS transistors (AT and ST) are fairly easy to make.

Description

Anordnung mit selbstverstärkenden dynamischen MOS-Transistor- speicherzellen. Arrangement with self-amplifying dynamic MOS transistor memory cells.
Die Erfindung betrifft eine Anordnung mit selbstverstärkenden dynamischen MOS-Transistorspeicherzellen nach dem Oberbegriff des Patentanspruchs 1.The invention relates to an arrangement with self-reinforcing dynamic MOS transistor memory cells according to the preamble of claim 1.
Eine Anordnung selbstverstärkender dynamischer MOS-Transistor¬ speicherzellen dieser Art ist aus der Veröffentlichung mit dem Titel "New Dynamic RAM Cell for VLSI Memories" von T. Tsuchiya und M. Itsumi aus IEEE Electron. Device Letters, Vol. EDL-3, No. 1, January 1982 (Seite 7 bis 10) bekannt. Dabei handelt es sich um eine Speicherzelle mit zwei Schreibleitungen und einer Leseleitung die aus einem MOS-FET, einem MOS-Kondensator und einem Junction-FET aufgebaut ist.An arrangement of self-amplifying dynamic MOS transistor memory cells of this type is from the publication entitled "New Dynamic RAM Cell for VLSI Memories" by T. Tsuchiya and M. Itsumi from IEEE Electron. Device Letters, Vol. EDL-3, No. 1, January 1982 (pages 7 to 10). It is a memory cell with two write lines and a read line which is made up of a MOS-FET, a MOS capacitor and a junction FET.
Der Erfindung liegt die Aufgabe zugrunde, eine Anordnung mit selbstverstärkenden dynamischen MOS-Transistorspeicherzellen der eingangs genannten Art anzugeben, die einfach aufgebaut ist, kurze Zugriffszeiten ermöglicht, eine geringe Empfindlich¬ keit gegen Treffer von Alphateilchen besitzt und vor allem deren Zellgeometrie skalierbar ist, ohne daß dabei die auf die Bitleitung auslesbare Ladungsmenge wesentlich verkleinert wird. Die Aufgabe wird erfinduπgsgemäß durch die im kennzeichnenden Teil des Patentanspruchs 1 angegebenen Merkmale gelöst.The invention has for its object to provide an arrangement with self-reinforcing dynamic MOS transistor memory cells of the type mentioned, which is simple in construction, allows short access times, has a low sensitivity to hits by alpha particles and, above all, their cell geometry is scalable without the amount of charge readable on the bit line is significantly reduced. The object is achieved according to the invention by the features specified in the characterizing part of patent claim 1.
Der mit der Erfindung erzielbare Vorteil liegt insbesondere darin, daß bei der nach der Erfindung ausgebildeten Anordnung mit selbstverstärkenden dynamischen MOS-Transistorspeicherzel¬ len, aufgrund höherer Kapazitätswerte bei gleichem Flächenbe¬ darf und geringerer Leckstromverluste, ein besseres Ladungs- Speicherungsverhalten möglich ist als bei der eingangs zitier¬ ten Speicherzelle. Weitere Vorteile sind die einfacher Her¬ stellbarkeit des MOS-Transistors im Vergleich zum Junction-FET und eine geringere Soft-Error-Rate durch die geringere Empfind lichkeit gegenüber Alpha-Strahlen aufgrund einer im Vergleich zur Zellfläche kleineren empfindlichen Fläche.The advantage that can be achieved with the invention is, in particular, that in the arrangement designed according to the invention with self-amplifying dynamic MOS transistor memory cells, owing to higher capacitance values with the same area requirement and lower leakage current losses, better charge storage behavior is possible than in the beginning cited memory cell. Further advantages are the simple manufacture of the MOS transistor compared to the junction FET and a lower soft error rate due to the lower sensitivity to alpha rays due to a smaller sensitive area compared to the cell area.
Die Patentansprüche 2 bis 8 sind auf bevorzugte Ausbildungen der erfindungsgemäßen Anordnung mit selbstverstärkenden dyna¬ mischen MOS-Transistorspeicherzellen gerichtet.Claims 2 to 8 are directed to preferred embodiments of the arrangement according to the invention with self-amplifying dynamic MOS transistor memory cells.
Die Erfindung wird nachfolgend anhand der Zeichnung näher er- läutert. Dabei zeigt:The invention is explained in more detail below with reference to the drawing. It shows:
Figur 1 eine Schnittdarstellung zweier benachbarter MOS-Tran¬ sistorspeicherzellen einer erfindungsgemäßen Speicher¬ zellenanordnung mit planar aufgebauten Transistoren und jeweils einem n+n-Übergang als spannungsabhängigerFigure 1 is a sectional view of two adjacent MOS transistor memory cells of a memory cell arrangement according to the invention with planar transistors and each having an n + n junction as a voltage-dependent
Widerstand,Resistance,
Figur 2 eine Schnittdarstellung einer MOS-Transistorspeicher¬ zelle einer erfindungsgemäßen Speicherzellenanordnung mit planar ausgeführten Transistoren und einem Schott- ky-Übergang als spannungsabhängiger Widerstand,FIG. 2 shows a sectional view of a MOS transistor memory cell of a memory cell arrangement according to the invention with planar transistors and a Schottky junction as a voltage-dependent resistor,
Figur 3 eine Schnittdarstellung einer MOS-Transistorspeicher¬ zelle einer erfindungsgemäßen Speicherzellenanordnung mit planar ausgeführten Transistoren und einem n+p+-FIG. 3 shows a sectional illustration of a MOS transistor memory cell of a memory cell arrangement according to the invention with planar transistors and an n + p + -
Übergang als spannungsabhängiger Widerstand,Transition as a voltage-dependent resistor,
Figur 4 eine Schnittdarstellung einer MOS-Transistorspeicher¬ zelle einer erfindungsgemäßen Speicherzellenanordnung mit planare Auswahltransistor und einem Speichertran¬ sistor in Trenchausführung,FIG. 4 shows a sectional illustration of a MOS transistor memory cell of a memory cell arrangement according to the invention with a planar selection transistor and a memory transistor in a trench design,
Figur 5 eine Schnittdarstellung einer MOS-Transistorspeicher¬ zelle einer erfindungsgemäßen Speicherzellenanordnung mit einem Auswahltransistor und einem Speichertransi¬ stor in Trenchausführung,FIG. 5 shows a sectional illustration of a MOS transistor memory cell of a memory cell arrangement according to the invention with a selection transistor and a memory transistor in a trench design,
Figur 6 ein Ersatzschaltbild einer MOS-Transistorspeicherzelle einer erfindungsgemäßen Speicherzellenanordnung, Figur 7 ein Diagramm zur Verdeutlichung der zeitlichen Span¬ nungsverläufe beim Einschreiben von Informationen in eine erfindungsgemäße Speicherzellenanordnung,FIG. 6 shows an equivalent circuit diagram of a MOS transistor memory cell of a memory cell arrangement according to the invention, FIG. 7 shows a diagram to illustrate the temporal voltage curves when writing information into a memory cell arrangement according to the invention,
Figur 8 ein Diagramm zur Verdeutlichung der zeitlichen Stro - und Spannungsverläufe zum Auslesen von Informationen aus einer MOS-Transistorspeicherzelle einer erfindungs¬ gemäßen Speicherzellenanordnung.FIG. 8 shows a diagram to illustrate the temporal current and voltage profiles for reading out information from a MOS transistor memory cell of a memory cell arrangement according to the invention.
Die Schnittdarstellung von Figur 1 zeigt eine bevorzugte Aus¬ bildung zweier benachbarter erfindungsgemäßer MOS-Transistor¬ speicherzellen Z und Z1. Die Zellen Z und Z' besitzen ein p-do- tiertes Substrat PSUB, das beispielsweise aus Silizium besteht und sich auf Bezugspotential befindet. In dieses Substrat PSUB sind n+-dotierte Draingebiete D und D1, n-dotierte Drain-Source- Gebiete DS und DS1 und ein n+-dotiertes und beiden Speicherzel¬ len Z und Z1 gemeinsames Source-Gebiet S von einer Oberfläche 0 des Substrats PSUB her eingebracht. Das gemeinsame Source-Ge¬ biet S ist mit einer beiden Speicherzellen Z und Z' ge einsa- men Bitleitung BL verbunden. Da die Speicherzellen Z und Z' völlig symmetrisch sind, gelten die im folgenden für Z gemach¬ ten Aussagen entsprechender Weise auch für Z'. Das beiden Spei¬ cherzellen Z und Z1 gemeinsame Source-Gebiet S, das Drain- Source-Gebiet DS und das zwischen den beiden Gebieten S und DS liegende Substrat PSUB bilden zusammen mit einer durch ein dünnes Gateoxid GOX vom Substrat PSUB getrennten und n+-dotier- ten Gate-Elektrode GAT einen Auswahltransistor AT. Das Drain- Source-Gebiet DS stellt das Drain-Gebiet des Auswahltransi¬ stors AT dar und bildet gleichzeitig das Source-Gebiet des Speichertransistors ST. Der Speichertransistor ST wird aus dem Drain-Source-Gebiet DS, einem Drain-Gebiet D und einem dazwi¬ schenliegenden Substrat PSUB zusammen mit einer durch das dünne Gateoxid GOX vom Substrat PSUB getrennten und n+-dotierten Gate-Elektrode GST des Steuertransistors ST gebildet. Das Drain-Gebiet D ist mit einer Versorgungsspannungsleitung V und die Gate-Elektrode GAT des Auswahltransistors AT ist mit einer Wortleitung WL elektrisch leitend verbunden. Die Gate-Elektro¬ de GST des Steuertransistors ST und das Drain-Source-Gebiet DS berühren sich und bilden einen n+n-Übergang 1. Figur 2 zeigt eine bevorzugte Ausbildung einer Speicherzelle Z einer erfindungsgemäßen Anordnung von Speicherzellen mit planar ausgeführten Transistoren, wobei sich hierbei die Speicherzel¬ le gegenüber der in Figur 1 gezeigten Speicherzelle darin un¬ terscheidet, daß die Gate-Elektrode GST des Speichertransistors ST mit Hilfe eines Schottky-Übergangs 2 an das Drain-Source-Ge¬ biet DS angeschlossen ist. Der Schottky-Übergang 2 wird hier¬ bei durch die n+-dotierte Gate-Elektrode GST und einen Metall¬ film M gebildet.The sectional view of FIG. 1 shows a preferred embodiment of two adjacent MOS transistor memory cells Z and Z 1 according to the invention. The cells Z and Z 'have a p-doped substrate PSUB, which consists, for example, of silicon and is at reference potential. In this substrate PSUB there are n + -doped drain regions D and D 1 , n-doped drain-source regions DS and DS 1 and an n + -doped and both storage cells Z and Z 1 common source region S from one surface 0 of the substrate PSUB brought here. The common source region S is connected to one of the two memory cells Z and Z ', a single bit line BL. Since the memory cells Z and Z 'are completely symmetrical, the statements made below for Z also apply correspondingly to Z'. The two storage cells Z and Z 1 common source region S, the drain-source region DS and the substrate PSUB lying between the two regions S and DS form together with a n + separated by a thin gate oxide GOX from the substrate PSUB -doped gate electrode GAT a selection transistor AT. The drain-source region DS represents the drain region of the selection transistor AT and at the same time forms the source region of the memory transistor ST. The memory transistor ST is formed from the drain-source region DS, a drain region D and an intermediate substrate PSUB together with a n + -doped gate electrode GST of the control transistor ST which is separated from the substrate PSUB by the thin gate oxide GOX . The drain region D is connected to a supply voltage line V and the gate electrode GAT of the selection transistor AT is electrically connected to a word line WL. The gate electrodes de GST of the control transistor ST and the drain-source region DS touch and form an n + n junction 1. FIG. 2 shows a preferred embodiment of a memory cell Z of an arrangement of memory cells with planar transistors in accordance with the invention, the memory cell differing from the memory cell shown in FIG. 1 in that the gate electrode GST of the memory transistor ST with the aid of a Schottky junction 2 is connected to the drain-source area DS. The Schottky junction 2 is formed here by the n + -doped gate electrode GST and a metal film M.
In Figur 3 ist, wie bei Figur 1 und 2, eine bevorzugte Ausbil¬ dung einer MOS-Transistorspeicherzelle einer erfindungsgemäßen Anordnung von Speicherzellen mit planar ausgeführten Transi¬ storen dargestellt, bei der jedoch eine polykristalline oder polykristallin-silizidierte n+-Gate-Elektrode GST auf ein p+-Gebiet G trifft um einen spannungsabhäπgigen Widerstand durch einen n+p+-Übergang 3 zu bilden. Ein ausreichend hoch¬ dotierter p+n+-Übergang stellt dabei einen ohmschen Kontakt zum Source-Drain-Gebiet DS her.FIG. 3 shows, as in FIGS. 1 and 2, a preferred embodiment of a MOS transistor memory cell in an arrangement of memory cells according to the invention with planar transistors, but in which a polycrystalline or polycrystalline silicided n + gate electrode GST meets a p + region G in order to form a voltage-dependent resistance through an n + p + junction 3. A sufficiently highly doped p + n + junction makes ohmic contact with the source-drain region DS.
Eine andere bevorzugte Ausbildung der MOS-Speicherzelle einer erfindungsgemäßen Anordnung mit Speicherzellen weist, wie in Figur 4 gezeigt, einen planar ausgebildeten Auswahltransistor AT und einen Speichertransistor ST in Trench-Ausführung auf. in einem n-dotierten Substrat NSUB befindet sich hierbei ein p-dotiertes und auf Bezugspotential liegendes Gebiet PG, in das ein n-dotiertes Drain-Source-Gebiet DS und ein n+-dotier- tes Source-Gebiet S von der Oberfläche 0 her eingebracht sind. Wie beispielsweise in Figur 1, wird ein planerer Auswahltran- sistor AT durch ein n-dotiertes Drain-Source-Gebiet DS, ein gemeinsames n+-dotiertes Source-Gebiet S und dem dazwischen¬ liegenden p-dotierten Gebiet PG zusammen mit einer durch ein dünnes Gateoxid GOX vom Substrat NSUB getrennten und n+-do- tierten Gate-Elektrode GAT des Auswahltransistors AT gebildet. Das Source-Gebiet S ist mit einer Bitleitung BL und die Gate- Elektrode GAT des Auswahltransistors AT ist mit einer Wortlei¬ tung WL verbunden. In das Substrat NSUB ist ein Graben T (Trench) eingeätzt, der etwas tiefer ist als das p-dotierte Gebiet PG. Das n-dotierte Substrat NSUB ist in diesem Fall mit der Versorgungsspannungsleitung V verbunden, so daß auf der Chipoberfläche, zur Kontaktierung der Zellen, nur die matrix- för ig angeordneten Bit- und Wortleitungen BL und WL erforder¬ lich sind. Ein n+-dotiertes Gate-Elektrode GST des Steuertran- sistors ST ist zum größten Teil in den Graben T (Trench) ver¬ legt, wobei das Gate-Gebiet GST durch ein dünnes Gateoxid GOX vom Substrat NSUB getrennt ist und den Graben T auskleidet. Im Innern des ausgekleideten Grabens befindet sich, zur Ver¬ größerung einer am Gate des Speichertransistors ST wirksamen Kapazität C, ein elektrisch leitender Bereich Pl (Platte), beispielsweise aus polykristallinem Silizium, der durch ein Zwischenoxid ZOX vom Gate-Gebiet GST isoliert ist und sich zum Beispiel auf einem Potential von VDD 2 befindet. Die Gate-Elek¬ trode GST des Steuertransistors ST und das Drain-Source-Gebiet DS berühren sich und bilden so einen n+n-Übergang la.Another preferred embodiment of the MOS memory cell of an arrangement according to the invention with memory cells, as shown in FIG. 4, has a planar selection transistor AT and a memory transistor ST in the form of a trench. In this case, an n-doped substrate NSUB contains a p-doped region PG lying at reference potential, into which an n-doped drain-source region DS and an n + -doped source region S from the surface 0 are introduced. As for example in FIG. 1, a planer selection transistor AT is replaced by an n-doped drain-source region DS, a common n + -doped source region S and the p-doped region PG in between, together with one by Thin gate oxide GOX formed from the substrate NSUB and n + -doped gate electrode GAT of the selection transistor AT is formed. The source region S is connected to a bit line BL and the gate electrode GAT of the selection transistor AT is connected to a word line WL. A trench T (trench) is etched into the substrate NSUB, which is slightly deeper than the p-doped region PG. In this case, the n-doped substrate NSUB is included connected to the supply voltage line V, so that only the bit and word lines BL and WL arranged in matrix form are required on the chip surface for contacting the cells. An n + -doped gate electrode GST of the control transistor ST is largely laid in the trench T (trench), the gate region GST being separated from the substrate NSUB by a thin gate oxide GOX and lining the trench T. . In the interior of the lined trench, in order to enlarge a capacitance C effective at the gate of the memory transistor ST, there is an electrically conductive region P1 (plate), for example made of polycrystalline silicon, which is insulated from the gate region GST by an intermediate oxide ZOX for example at a potential of V DD 2. The gate electrode GST of the control transistor ST and the drain-source region DS touch and thus form an n + n junction 1 a.
Bei der in Figur 5 gezeigten bevorzugten Ausbildung einer MOS- Transistorspeicherzelle einer erfindungsgemäßen Anordnung von Speicherzellen sind sowohl ein Auswahltransistor AT als auch ein Steuertransistor ST in Trenchausführung realisiert. Hier¬ zu sind ein n+-dotiertes gemeinsames Source-Gebiet S und ein n+-dotiertes Drain-Gebiet D von der Oberfläche 0 her in ein p-dotiertes Substrat PSUB eingebracht und reichen jeweils bis an den Rand eines Grabens T (Trench). Ein n-dotiertes Drain- Source-Gebiet DS befindet sich direkt unterhalb des Grabens T, welcher durch ein dünnes Gateoxid GOX bis auf einen n+n-Über- gang lb zwischen der Gate-Elektrode GST des Speichertransistors ST und dem Drain-Source-Gebiet DS ausgekleidet ist. Im durch das dünne Gateoxid ausgekleideten Graben T befindet sich, von der Gate-Elektrode GST isoliert, ebenfalls die Gate-Elektrode GAT des Auswahltransistors AT. Die Gate-Elektrode GAT des Aus¬ wahltransistors AT ist mit einer Wortleitung WL verbunden und, wie die Gate-Elektrode GST des Speichertransistors ST, durch ein Zwischenoxid ZOX an der Innenseite des Grabens von einer Grabenfüllung PF aus polykristallinem Silizium isoliert. Das n+-dotierte Drain-Gebiet D ist mit der Versorgungsspannungs¬ leitung V und das n+-dotierte gemeinsame Source-Gebiet S mit einer Bitleitung BL verbunden. Alle Kombinationen zwischen den Übergängen 1 bis 3 und den Transistorausführungsformen Planar/Planar, Planar/Trench, Trench/Planar und Trench/Trench sind herstellbar. Stellver¬ tretend hierfür sind in den Figuren 1 bis 3 die Übergänge 1 bis 3 nur zusammen mit einer Planar/Planar-Transistorausfüh- rung gezeigt und in den Figuren 4 und 5 wird nur der Übergang 1 (la, lb) zusammen mit einer Planar/Trench-Transistorausfüh- rung sowie einer Trench/Trench-Transistorausführung gezeigt.In the preferred embodiment of a MOS transistor memory cell of an arrangement of memory cells according to the invention shown in FIG. 5, both a selection transistor AT and a control transistor ST in trench design are implemented. For this purpose, an n + -doped common source region S and an n + -doped drain region D are introduced into a p-doped substrate PSUB from the surface 0 and each extend to the edge of a trench T (trench) . An n-doped drain-source region DS is located directly underneath the trench T, which through a thin gate oxide GOX except for an n + n junction 1b between the gate electrode GST of the memory transistor ST and the drain-source Area DS is lined. In the trench T lined by the thin gate oxide there is also the gate electrode GAT of the selection transistor AT, insulated from the gate electrode GST. The gate electrode GAT of the selection transistor AT is connected to a word line WL and, like the gate electrode GST of the memory transistor ST, is insulated from a trench filling PF made of polycrystalline silicon by an intermediate oxide ZOX on the inside of the trench. The n + -doped drain region D is connected to the supply voltage line V and the n + -doped common source region S is connected to a bit line BL. All combinations between the transitions 1 to 3 and the transistor embodiments planar / planar, planar / trench, trench / planar and trench / trench can be produced. Representative of this, the transitions 1 to 3 are shown in FIGS. 1 to 3 only together with a planar / planar transistor design, and in FIGS. 4 and 5 only the transition 1 (la, lb) is shown together with a planar / Trench transistor version and a trench / trench transistor version shown.
Das Ersatzschaltbild einer MOS-Transistorspeicherzelle einer erfindungsgemäßen Anordnung mit Speicherzellen ist in Figur 6 dargestellt, wobei die nur zweitrangig oder parasitär wirksa¬ men Komponenten durch eine gestrichelte Linienführung gekenn-, zeichnet sind. Zwischen Bezugspotential und Bitleitung BL liegt eine Bitleitungsspannung Ug und der Sourceanschluß des Auswahltransistors AT ist mit einer Bitleitung BL verbunden, so daß ein Bitleitungsstrom iß auf die Bitleitung BL fließen kann. Zwischen Bezugspotential und Wortleitung WL liegt eine Wortleitungsspannung uw und der Gateanschluß des Auswahltran- sistors AT ist mit einer Wortleitung WL elektrisch leitend verbunden. Der Drainanschluß des Auswahltransistors AT besitzt mit dem Sourceanschluß des Speichertransistors ST einen ge¬ meinsamen Drain-Source-Knoten DSK, der über einen spannungs¬ abhängigen Widerstand VR, der seinerseits aus einem Widerstand R und einer dazu parallelen Diode Di besteht, mit dem Gate des Speichertransistors verbunden ist. Das Gate des Speichertran¬ sistors ST weist eine Gatekapazität C~ gegenüber dem Bezugs¬ potential auf und zwischen der Versorgungsspannungsleitung V und dem Bezugspotential liegt eine Spannung + VpD.The equivalent circuit diagram of a MOS transistor memory cell of an arrangement according to the invention with memory cells is shown in FIG. 6, the components having only secondary or parasitic effects being identified by dashed lines. A bit line voltage U g lies between the reference potential and the bit line BL and the source terminal of the selection transistor AT is connected to a bit line BL, so that a bit line current i β can flow onto the bit line BL. A word line voltage u w lies between the reference potential and word line WL and the gate connection of the selection transistor AT is electrically conductively connected to a word line WL. The drain terminal of the selection transistor AT has with the source terminal of the memory transistor ST a common drain-source node DSK, which has a voltage-dependent resistor VR, which in turn consists of a resistor R and a diode Di parallel thereto, with the gate of the Memory transistor is connected. The gate of the memory transistor ST has a gate capacitance C ~ compared to the reference potential and there is a voltage + Vp D between the supply voltage line V and the reference potential.
Zusätzlich zur Gatekapazität Cß kann durch die in Figur 4 ge¬ zeigte Platte Pl eine zur Gatekapazität CG parallelgeschalte¬ te Zusatzkapazität Cz, erzeugt werden. Da in Figur 4 das Sub¬ strat NSUB mit der Versorgungsspannung VDD verbunden ist, ist besonders hier noch eine weitere Zusatzkapazität CZ2 zwischen der Versorgungsspannungsleitung V und dem Gate des Speicher¬ transistors ST zu berücksichtigen. Der Übergang zwischen dem n-dotierten Drain-Source-Gebiet DS und dem angrenzenden p-do- tierten Gebiet PSUB oder PG stellt eine in Sperrichtung ge- polte parasitäre Diode Di dar, durch die ein Leckstrom iL2 fließt. Für den Fall einer gespeicherten "logischen 1" kann erreicht werden, daß ein zum Auswahltransistor AT fließenderIn addition to the gate capacitance C β , an additional capacitance C z connected in parallel to the gate capacitance C G can be generated by the plate P1 shown in FIG. Since the substrate NSUB is connected to the supply voltage V DD in FIG. 4, a further additional capacitance C Z2 between the supply voltage line V and the gate of the memory transistor ST must be taken into account here in particular. The transition between the n-doped drain-source region DS and the adjacent p-doped region PSUB or PG represents a polar parasitic diode Di through which a leakage current i L2 flows. In the case of a stored "logic 1" it can be achieved that one flowing to the selection transistor AT
Leckstrom i. , zusammen mit dem Leckstrom i.2, der durch die Diode Dipn fließt,' dem Betrag nach einem Subthresholdstrom iτT des Speichertransistors ST entspricht. Ist dies der Fall, so kann sich die am Gate des Speichertransistors ST wirksame Kapazität C nicht über den spannungsabhängigen Widerstand VR zum Drain-Source-Knoten DSK hin entladen und die Information der "logischen 1" bleibt länger erhalten. Im Falle einer ein¬ gespeicherten "logischen 0" befindet sich der Arbeitspunkt des Speichertransistors ST im Subthresholdbereich. Der Subthres¬ holdstrom iτ verschiebt das Potential des gemeinsamen Drain- Source-Knotens DSK etwas nach oben, bis durch höhere Leckströ- e i- , und iL2 ein Gleichgewicht entsteht.Leakage current i. , together with the leakage current i. 2 , which flows through the diode Dipn 'corresponds to the amount after a subthreshold current i τ T of the memory transistor ST. If this is the case, the capacitance C effective at the gate of the memory transistor ST cannot discharge to the drain-source node DSK via the voltage-dependent resistor VR and the information of the "logical 1" is retained for a longer time. In the case of a stored "logic 0", the operating point of the memory transistor ST is in the subthreshold range. The subthres¬ hold current i τ shifts the potential of the common drain-source node DSK somewhat upwards, until an equilibrium is created by higher leakage currents i and i L2 .
Zum Einlesen einer "logischen 1" (high) werden, wie in Figur 7 gezeigt, eine Bitleitungsspannung uB und eine Wortleitungsspan¬ nung uw die innerhalb eines Zeitintervalls t-, bis t2 die Werte uBH, uWH (high) und sonst die Werte uBL, uWL (low) annehmen. Solange der Auswahltransistor AT durch eine Wortleitungsspan¬ nung uw = uWH (high) eingeschaltet ist, wird die anliegende Bitleitungsspannung ußH (high) aber auch die Bitleitungsspan¬ nung Um (low) in die MOS-Transistorspeicherzelle eingelesen. Um eine, mit einer "logischen 1" (high) beschriebene, MOS-Tran¬ sistorspeicherzelle durch eine Bitleitungsspannung uß = u*,, (low) nach dem Zeitpunkt t2 nicht wieder teilweise zu entla¬ den, sollte der Auswahltransistor vor dem Zeitpunkt t2 auf¬ grund einer Wortleitungsspannung Uw = UWL(low) bereits sper- ren. Beim Einlesen einer "logischen 1" (high) liegt nach dem Durchschalten des Auswahltransistors AT die Bitleitungsspan¬ nung uß = ußH (high) am Drain-Source-Knoten DSK und lädt die am Gate des Speichertransistors ST wirksame Kapazität C über den in Flußrichtung gepolten, spannungsabhängigen Widerstand VR auf die Bitleitungsspannung uß = ußH (high) auf. Der span¬ nungsabhängige Widerstand VR weist dabei einen niedrigen Wi¬ derstandswert in der Größenordnung von einigen 10 kOh auf.To read in a "logic 1" (high), as shown in FIG. 7, a bit line voltage u B and a word line voltage u w which within a time interval t 2 to t 2 are the values u BH , u WH (high) and otherwise assume the values u BL , u WL (low). As long as the selection transistor AT is switched on by a word line voltage u w = u WH (high), the applied bit line voltage u ßH (high) but also the bit line voltage Um (low) is read into the MOS transistor memory cell. In order not to partially discharge a MOS transistor memory cell described with a "logical 1" (high) by a bit line voltage u β = u * ,, (low) after the time t2, the selection transistor should be before the time Block t2 due to a word line voltage U w = U WL (low). When a "logic 1" (high) is read in, after switching through the selection transistor AT, the bit line voltage u ß = u ßH (high) is at the drain Source node DSK and charges the capacitance C effective at the gate of the memory transistor ST via the voltage-dependent resistor VR which is polarized in the flow direction to the bit line voltage u ß = u ßH (high). The voltage-dependent resistor VR has a low resistance value on the order of a few 10 kOh.
Beim Einlesen einer "logischen 0" (low) liegt nach dem Durch- schalten des Auswahltransistors AT die Bitleitungsspannung uB = uBL (low) auch am Drain-Source-Knoten DSK, was zur Folge hat, daß eine auf die Spannung ußH aufgeladene, am Gate des Speichertransistors ST wirksame Kapazität C über den in Sperr- richtung gepolten, spannungsabhängigen Widerstand VR auf ußL mit der Zeitkonstante T = R*C entladen wird. Der in Sperrich- tung gepolte, spannungsabhängige Widerstand VR weist dabei den hohen Widerstandswert R auf, der im Mega-Ohm-Bereich liegt. Die Kapazität C liegt hierbei im Bereich von einigen fF. Für ein vollständiges Entladen der am Gate des Speichertransistors wirksamen Kapazität C muß für eine Zeitdauer von mehreren Zeitkonstanten T der Auswahltransistor AT eingeschaltet sein.When reading in a "logical 0" (low) after the Switch the selection transistor AT to the bit line voltage u B = u BL (low) also at the drain-source node DSK, which has the consequence that a capacitance C which is charged to the voltage u . direction polarized, voltage-dependent resistor VR to u ßL with the time constant T = R * C is discharged. The voltage-dependent resistor VR, which is polarized in the blocking direction, has the high resistance value R, which is in the mega-ohm range. The capacitance C is in the range of a few fF. For a complete discharge of the capacitance C effective at the gate of the memory transistor, the selection transistor AT must be switched on for a period of several time constants T.
Zum Auslesen wird die in Figur 8 gezeigte Wortleitungsspannung uw angelegt, die in einem Zeitintervall t^ bis t, den Wert uw = uWH (high) und sonst den Wert uw = uw(_ (low) annimmt. Im Zeitintervall t, bis t ist der durch uw angesteuerte Auswahl¬ transistor AT durchgeschaltet und die Bitleitung BL dadurch mit dem Drain-Source-Knoten DSK verbunden. Ist die am Gate des Speichertransistors ST wirksame Kapazität C auf ußH (high) auf¬ geladen und die Bitleitungsspannung uß = ußL (low), so fließt ein ebenfalls in Figur 8 dargestellter Bitleitungsstrom iß auf die Bitleitung BL. Die abfallende Flanke des transienten Bit¬ leitungsstroms ig ist im wesentlichen durch die Zeitkonstante T = R*C bestimmt und .das Zeitintegral von ig stellt die beim Auslesen einer "logischen 1" (high) verfügbare Ladungsmenge Q dar. Ein transienter Stromfluß durch den Speichertransistor ST und damit auch ein transienter Bitleitungsstrom ig wird da¬ durch erzeugt, daß das Gatepotential zeitlich verzögert dem Sourcepotential des Speichertransistors folgt und dadurch eine Gate-Source-Spannung entsteht die großer als die Schwellenspan¬ nung des Speichertransistors ST ist. Die Ladung Q besteht aus der Ladung der am Gate des Speichertransistors ST wirksamen Kapazität C und aus der um ein Vielfaches größeren, aus dem Drainstrom des Speichertransistors ST resultierenden Ladung. Ist die Ladungsmenge Q groß genug, so kann bei vorgegebener Bitleitungskapazität ein Spannungsimpuls auf der Bitleituπg BL als "logische 1" detektiert werden. Bei einer Skalierung der erfindungsgemäßen Anordnung mit MOS- Transistorspeicherzellen zu kleineren Zellgeometrien hin nehmen die Kanalweite und die Kanallänge ungefähr im selben Maß ab, dies bewirkt einen weitgehend unveränderten Drainstrom durch den Speichertransistor. Die Zeitkonstante T = R*C bleibt ebenfalls weitgehend unverändert, da der Widerstand R ungefähr im selben Maß zunimmt wie die Kapazität C abnimmt. Durch die weitgehende Konstanz des Drainstroms und der Zeitkonstante T ist auch die verfügbare Ladungsmenge Q weitgehend skalierungs- unabhängig.For reading out, the word line voltage u w shown in FIG. 8 is applied, which assumes the value u w = u WH (high) and the value u w = u w ( _ (low) in a time interval t ^ to t. In the time interval The selection transistor AT, which is driven by u w, is switched through and the bit line BL is thereby connected to the drain-source node DSK t, to t The capacitance C effective at the gate of the memory transistor ST is charged to u βH (high) and the bit line voltage flows u ß = u SSL (low), a determined also in Figure 8 illustrated bit line current I SS to the bit line BL. the falling edge of the transient Bit¬ is line current IG substantially by the time constant T = R * C. the time integral of ig represents the amount of charge Q available when reading out a “logical 1” (high). A transient current flow through the memory transistor ST and thus also a transient bit line current ig is generated by the fact that the gate potential is temporal delayed follows the source potential of the memory transistor and thereby a gate-source voltage arises which is greater than the threshold voltage of the memory transistor ST. The charge Q consists of the charge of the capacitance C effective at the gate of the memory transistor ST and of the charge which is many times greater, resulting from the drain current of the memory transistor ST. If the amount of charge Q is large enough, a voltage pulse on the bit line BL can be detected as "logical 1" for a given bit line capacitance. When the arrangement according to the invention with MOS transistor memory cells is scaled down to smaller cell geometries, the channel width and the channel length decrease approximately to the same extent, which results in a largely unchanged drain current through the memory transistor. The time constant T = R * C also remains largely unchanged, since the resistance R increases approximately to the same extent as the capacitance C decreases. Due to the largely constant drain current and the time constant T, the available amount of charge Q is largely independent of scaling.
In den obigen Ausführungen entspricht die Bitleitungsspannung UB = UBH (niSn) einer "logischen 1", in entsprechender Weise könnte auch die Bitleitungsspannung uß = Ug, (low) einer "lo- gischen 1" zugeordnet werden.In the above explanations, the bit line voltage U B = U BH ( ni S n ) corresponds to a "logic 1", in a corresponding manner the bit line voltage u β = Ug, (low) could also be assigned to a "logic 1".
Die erfindungsgemäße Anordnung kann nicht nur, wie gezeigt, in n-Kanal-Technologie aufgebaut werden, sondern auch in p-Kanal- Technologie. Hierzu sind bei allen Dotierungsgebieten die Lei- tungstypen von p nach n und umgekehrt zu vertauschen und die Vorzeichen der Spannungen zu ändern. The arrangement according to the invention can be constructed not only in n-channel technology, as shown, but also in p-channel technology. For this purpose, the line types have to be exchanged from p to n and vice versa for all doping areas and the signs of the voltages have to be changed.

Claims

Patentansprüche Claims
1. Eine Anordnung mit selbstverstärkenden dynamischen MOS-Tran sistorspeicherzellen, mit einer Vielzahl von MOS-Transistor- Speicherzellen, die nur mit jeweils einer Bitleitung elektrisc leitend verbunden sind, die jeweils einen Auswahltransistor besitzen, dessen Gate mit einer Wortleitung elektrisch leitend verbunden ist, und die jeweils einen Speichertransistor aufweisen, an dessen Gate eine Kapazität wirksam ist um Informationen in Form von elektrischer Ladung zu speichern, d a d u r c h g e k e n n z e i c h n e t , daß jeweils eine MOS-Transistorspeicherzelle mit lediglich einer Bitleitung (BL) und nur einer Wortleitung (WL) elektrisc leitend verbunden ist, und daß sowohl der Auswahltransistor (AT) als auch der Speichertra sistor (ST) jeweils aus einem MOS-Transistor bestehen.1. An arrangement with self-amplifying dynamic MOS transistor transistor memory cells, with a plurality of MOS transistor memory cells which are electrically connected to only one bit line, each having a selection transistor, the gate of which is electrically connected to a word line, and each having a memory transistor, at the gate of which a capacitance is effective to store information in the form of electrical charge, characterized in that in each case one MOS transistor memory cell is electrically conductively connected to only one bit line (BL) and only one word line (WL), and that both the selection transistor (AT) and the Speichertra sistor (ST) each consist of a MOS transistor.
2. Anordnung mit selbstverstärkenden dynamischen MOS-Transi- storspeicherzellen nach Anspruch 1, d a d u r c h g e ¬ k e n n z e i c h n e t , daß die Wortleitung (WL) jeweils mit einem ersten Anschluß des Auswahltransistors (AT) elektrisch leitend verbunden ist und dieser erste Anschluß der Gatean¬ schluß des Auswahltransistors (AT) ist, daß ein zweiter Anschluß des Auswahltransistors (AT) jeweils mit der Bitleitung (BL) elektrisch leitend verbunden ist, daß jeweils der dritte Anschluß des Auswahltransistors (AT) und ein erster Anschluß des Speichertransistors (ST) einen ge¬ meinsamen Drain-Source-Knoten (DSK) bilden, daß jeweils ein zweiter Anschluß des Speichertransistors (ST) mit einer Versorgungsspannung VDD) elektrisch leitend verbun¬ den ist und der dritte Anschluß den Gateanschluß des Speicher¬ transistors (ST) darstellt, und daß jeweils ein spannungsabhängiger Widerstand (VR) den gemein- samen Drain-Source-Knoten (DSK) so mit dem Gate des Speicher¬ transistors (ST) und einer an ihm wirksamen Kapazität (C) ver¬ bindet, daß ein niedriger Widerstandswert beim Aufladen und ein hoher Widerstandswert (R) beim Entladen der Kapazität (C) auftritt. 2. Arrangement with self-amplifying dynamic MOS transistor memory cells according to claim 1, dadurchge ¬ indicates that the word line (WL) is electrically connected to a first connection of the selection transistor (AT) and this first connection of the gate connection of the selection transistor ( AT) is that a second connection of the selection transistor (AT) is in each case electrically conductively connected to the bit line (BL), that the third connection of the selection transistor (AT) and a first connection of the memory transistor (ST) each have a common drain. Source nodes (DSK) form that in each case a second connection of the memory transistor (ST) is electrically conductively connected to a supply voltage V DD ) and the third connection represents the gate connection of the memory transistor (ST), and that in each case a voltage-dependent one Resistor (VR) the common drain-source node (DSK) with the gate of the memory transistor (ST) and ei connected to him effective capacitance (C) that a low resistance value occurs when charging and a high resistance value (R) when discharging the capacitance (C).
3. Anordnung mit selbstverstärkenden dynamischen MOS-Transi¬ storspeicherzellen nach Anspruch 2, d a d u r c h g e ¬ k e n n z e i c h n e t , daß jeweils der spannungsabhängige Widerstand (VR) dadurch gebildet wird, daß die Gate-Elektrode (GST) des Speichertransistors (ST) und das gemeinsame Drain- Source-Gebiet (DS) der beiden Transistoren (AT, ST) aus Halb¬ leitermaterialien gleichen Leitungstyps bestehen, wobei die Gate-Elektrode (GST) des Speichertransistors (ST) jedoch eine höhere Dotierungskonzentration als das Drain-Source-Gebiet (DS) aufweist.3. Arrangement with self-amplifying dynamic MOS transistor storage cells according to claim 2, dadurchge ¬ indicates that in each case the voltage-dependent resistor (VR) is formed in that the gate electrode (GST) of the memory transistor (ST) and the common drain source Region (DS) of the two transistors (AT, ST) consist of semiconductor materials of the same conductivity type, but the gate electrode (GST) of the memory transistor (ST) has a higher doping concentration than the drain-source region (DS).
4. Anordnung mit selbstverstärkenden dynamischen MOS-Transi¬ storspeicherzellen nach Anspruch 2, d a d u r c h g e ¬ k e n n z e i c h n e t , daß jeweils die Gate-Elektrode (GST) des Speichertransistors (ST) und das gemeinsame Drain- Source-Gebiet (DS) der beiden Transistoren (AT, ST) aus Halb¬ leitermaterialien gleichen Leitungstyps bestehen, wobei die Gate-Elektrode (GST) des Speichertransistors (ST) jedoch eine höhere Dotierungskonzentration als das gemeinsame Drain-Source- Gebiet (DS) aufweist und daß eine Metallschicht (M) zusammen mit der Gate-Elektrode (GST) des Speichertransistors (ST) eine Schottky-Diode bildet, die beim Aufladen der am Gate des Spei¬ chertransistors (ST) wirksamen Kapazität (C) einen niedrigeren Widerstand als beim Entladen dieser Kapazität (C) aufweist.4. Arrangement with self-amplifying dynamic MOS transistor storage cells according to claim 2, dadurchge ¬ indicates that in each case the gate electrode (GST) of the memory transistor (ST) and the common drain-source region (DS) of the two transistors (AT, ST) consist of semiconductor materials of the same conductivity type, the gate electrode (GST) of the memory transistor (ST), however, having a higher doping concentration than the common drain-source region (DS) and that a metal layer (M) together with the gate -Electrode (GST) of the memory transistor (ST) forms a Schottky diode which, when charging the capacitance (C) active at the gate of the memory transistor (ST), has a lower resistance than when this capacitor (C) is discharged.
5. Anordnung mit selbstverstärkenden dynamischen MOS-Transi¬ storspeicherzellen nach Anspruch 2, d a d u r c h g e ¬ k e n n z e i c h n e t , daß jeweils die Gate-Elektrode (GST) des Speichertransistors (ST) und das gemeinsame Drain- Source-Gebiet (DS) der beiden Transistoren (AT, ST) aus hoch¬ dotierten Halbleitermaterialien gleichen Leitungstyps beste¬ hen, zusätzlich aber ein hochdotiertes Gebiet (G) eines zur Gate-Elektrode (GST' und Drain-Source-Geb: t (DS) unterschied¬ lichen Leitungstyps zwischen die Gate-Ele trode (GST) und das Drain-Source-Gebiet (DS) eingefügt ist, um einen spannungsab¬ hängigen Widerstand (VR) zu bewirken, der beim Aufladen der am Gate des Speichertransistors (ST) wirksamen Kapazität (C) einen niedrigeren Widerstand als beim Entladen dieser Kapazi¬ tät (C) aufweist. 5. Arrangement with self-amplifying dynamic MOS transistor storage cells according to claim 2, dadurchge ¬ indicates that in each case the gate electrode (GST) of the memory transistor (ST) and the common drain-source region (DS) of the two transistors (AT, ST) consist of highly doped semiconductor materials of the same conductivity type, but additionally a highly doped region (G) of a conductivity type different from the gate electrode (GST 'and drain-source device (DS)) between the gate electrode (GST) and the drain-source region (DS) is inserted in order to bring about a voltage-dependent resistor (VR) which has a lower resistance when charging the capacitor (C) effective at the gate of the memory transistor (ST) than when discharging this has capacity (C).
6. Anordnung mit selbstverstärkenden dynamischen MOS-Transi¬ storspeicherzellen nach Anspruch 2, d a d u r c h g e ¬ k e n n z e i c h n e t , daß jeweils sowohl der Auswahl¬ transistor (AT) als auch der Speichertransistor (ST) planar aufgebaut sind.6. Arrangement with self-amplifying dynamic MOS transistor memory cells according to claim 2, d a d u r c h g e ¬ k e n n z e i c h n e t that both the selection transistor (AT) and the memory transistor (ST) are constructed planar.
7. Anordnung mit selbstverstärkenden dynamischen MOS-Transi¬ storspeicherzellen nach Anspruch 2, d a d u r c h g e ¬ k e n n z e i c h n e t , daß jeweils der Auswahltransistor (AT) planar aufgebaut ist und der Speichertransistor (ST) sich in einem Graben (T) befindet, wobei die Versorgungsspannung (VDD) direkt über ein Substrat (NSUB) zuführbar ist.7. Arrangement with self-amplifying dynamic MOS transistor storage cells according to claim 2, dadurchge ¬ indicates that each of the selection transistor (AT) is planar and the memory transistor (ST) is in a trench (T), the supply voltage (V DD ) can be fed directly via a substrate (NSUB).
8. Anordnung mit selbstverstärkenden dynamischen MOS-Transi- storspeicherzellen nach Anspruch 2, d a d u r c h g e ¬ k e n n z e i c h n e t , daß jeweils sowohl der Auswahltran¬ sistor (AT) als auch der Speichertransistor (ST) sich im sel¬ ben Graben (T) befinden, wobei die Gate-Elektrode (GST) des Speichertransistors (ST) durch ein Zwischenoxid (ZOX) von einer Gate-Elektrode (GAT) des Auswahltransistors (AT) iso¬ liert ist. 8. An arrangement with self-amplifying dynamic MOS transistor memory cells according to claim 2, dadurchge ¬ indicates that both the selection transistor (AT) and the memory transistor (ST) are in the same trench (T), the gate -Electrode (GST) of the memory transistor (ST) is insulated by an intermediate oxide (ZOX) from a gate electrode (GAT) of the selection transistor (AT).
PCT/DE1991/000502 1990-07-03 1991-06-18 Device with self-amplifying dynamic mos transistor storage cells WO1992001287A1 (en)

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DE59102966T DE59102966D1 (en) 1990-07-03 1991-06-18 ARRANGEMENT WITH SELF-REINFORCING DYNAMIC MOS TRANSISTOR CELLS.
JP3510021A JP3061857B2 (en) 1990-07-03 1991-06-18 Device with self-amplifying dynamic MOS transistor memory cell
EP91911441A EP0537203B1 (en) 1990-07-03 1991-06-18 Device with self-amplifying dynamic mos transistor storage cells
KR1019920703410A KR0156233B1 (en) 1990-07-03 1991-06-18 Arrangement with self-amplifying dynamic mos transistor storage cells
US07/956,896 US5327374A (en) 1990-07-03 1991-07-18 Arrangement with self-amplifying dynamic MOS transistor storage cells

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4417150A1 (en) * 1994-05-17 1995-11-23 Siemens Ag Method for producing an arrangement with self-reinforcing dynamic MOS transistor memory cells
EP0766312A1 (en) * 1995-09-26 1997-04-02 Siemens Aktiengesellschaft Gain cell DRAM storage device
US5710448A (en) * 1995-10-27 1998-01-20 Siemens Aktiengesellschaft Integrated polysilicon diode contact for gain memory cells
DE19727436C1 (en) * 1997-06-27 1998-10-01 Siemens Ag DRAM-cell arrangement with dynamic self-amplifying storage cells
WO1999035693A1 (en) * 1998-01-07 1999-07-15 Siemens Aktiengesellschaft Semiconductor memory system and method for producing same
US6576948B2 (en) 1998-12-03 2003-06-10 Infineon Technologies Ag Integrated circuit configuration and method for manufacturing it

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5684313A (en) * 1996-02-20 1997-11-04 Kenney; Donald M. Vertical precharge structure for DRAM
US5721448A (en) * 1996-07-30 1998-02-24 International Business Machines Corporation Integrated circuit chip having isolation trenches composed of a dielectric layer with oxidation catalyst material
US5757059A (en) * 1996-07-30 1998-05-26 International Business Machines Corporation Insulated gate field effect transistor
DE19720193C2 (en) * 1997-05-14 2002-10-17 Infineon Technologies Ag Integrated circuit arrangement with at least two vertical MOS transistors and method for their production
DE19723936A1 (en) * 1997-06-06 1998-12-10 Siemens Ag DRAM cell arrangement and method for its production
US5886382A (en) * 1997-07-18 1999-03-23 Motorola, Inc. Trench transistor structure comprising at least two vertical transistors
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DE19961779A1 (en) * 1999-12-21 2001-07-05 Infineon Technologies Ag Integrated dynamic memory cell with small spreading area and process for its production
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US8097915B2 (en) * 2005-05-31 2012-01-17 Qimonda Ag Semiconductor memory device
US7859026B2 (en) * 2006-03-16 2010-12-28 Spansion Llc Vertical semiconductor device
US7582922B2 (en) * 2007-11-26 2009-09-01 Infineon Technologies Austria Ag Semiconductor device
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US8796751B2 (en) * 2012-11-20 2014-08-05 Micron Technology, Inc. Transistors, memory cells and semiconductor constructions
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4805148A (en) * 1985-11-22 1989-02-14 Diehl Nagle Sherra E High impendance-coupled CMOS SRAM for improved single event immunity

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4835741A (en) * 1986-06-02 1989-05-30 Texas Instruments Incorporated Frasable electrically programmable read only memory cell using a three dimensional trench floating gate
DE3816358A1 (en) * 1988-05-13 1989-11-23 Eurosil Electronic Gmbh NON-VOLATILE STORAGE CELL AND METHOD FOR THE PRODUCTION THEREOF
US4964080A (en) * 1990-03-09 1990-10-16 Intel Corporation Three-dimensional memory cell with integral select transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4805148A (en) * 1985-11-22 1989-02-14 Diehl Nagle Sherra E High impendance-coupled CMOS SRAM for improved single event immunity

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IEEE CIRCUITS AND DEVICES MAGAZINE. Bd. 5, Nr. 1, Januar 1989, NEW YORK US Seiten 27 - 36; LU: 'ADVANCED CELL STRUCTURES FOR DYNAMIC RAMS ' siehe Seite 29, rechte Spalte, Zeile 14 - Seite 31, rechte Spalte, Zeile 42; Abbildungen 6,8,9 *
JEE JOURNAL OF ELECTRONIC ENGINEERING. Bd. 23, Nr. 230, Januar 1986, TOKYO JP Seite 18; 'NEC DEVELOPS MEMORY CELL ARCHITECTURE FOR 4-MEGABIT DRAM ' siehe das ganze Dokument *

Cited By (12)

* Cited by examiner, † Cited by third party
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WO1995031828A1 (en) * 1994-05-17 1995-11-23 Siemens Aktiengesellschaft Gain cell dram structure and process for producing the same
US5710072A (en) * 1994-05-17 1998-01-20 Siemens Aktiengesellschaft Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells
EP0766312A1 (en) * 1995-09-26 1997-04-02 Siemens Aktiengesellschaft Gain cell DRAM storage device
US5854500A (en) * 1995-09-26 1998-12-29 Siemens Aktiengesellschaft DRAM cell array with dynamic gain memory cells
US5710448A (en) * 1995-10-27 1998-01-20 Siemens Aktiengesellschaft Integrated polysilicon diode contact for gain memory cells
DE19727436C1 (en) * 1997-06-27 1998-10-01 Siemens Ag DRAM-cell arrangement with dynamic self-amplifying storage cells
EP0887862A2 (en) * 1997-06-27 1998-12-30 Siemens Aktiengesellschaft DRAM with gain memory cells
US6049105A (en) * 1997-06-27 2000-04-11 Siemens Aktiengesellschaft DRAM cell arrangement having dynamic self-amplifying memory cells, and method for manufacturing same
EP0887862A3 (en) * 1997-06-27 2005-05-11 Infineon Technologies AG DRAM with gain memory cells
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US6576948B2 (en) 1998-12-03 2003-06-10 Infineon Technologies Ag Integrated circuit configuration and method for manufacturing it

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US5327374A (en) 1994-07-05
EP0537203B1 (en) 1994-09-14
KR930701815A (en) 1993-06-12
EP0537203A1 (en) 1993-04-21
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JP3061857B2 (en) 2000-07-10
HK59696A (en) 1996-04-12

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