DE2754987C2 - Semiconductor storage device - Google Patents

Description

characterized,

that the storage elements are binary capacitors CMCl), MC2) , which switch from a first capacitance value to a second capacitance value at a threshold voltage and at least one of which is a binary capacitor with a variable threshold voltage, which is on the one hand a part of the surface of the semiconductor substrate (1 ) of the first conductivity type arranged semiconductor layer (2) of the second conductivity type, several superimposed insulating layers (3, 4), which are on part of the surface of the semiconductor layer (2) and on part of the surface before the semiconductor substrate (1) Formation of a charge trapping area are formed, and has a conductive layer (5) formed on the uppermost insulating layer (4), and the other hand over the semiconductor layer (2) with the node (Nu N ^) and over the conductive layer (5 ) is connected to the control signal line (MG) ,

that the first two field effect transistors (QW, Q \ 2) are connected with their drain electrodes to the source electrodes of the two second field effect transistors (Q 13, Q 14), and that the gate electrodes of the two second field effect transistors (Q 13, Q 14) are connected to a second control signal line (CLK) (FIG . 3).

2. Semiconductor memory device for energy-independent (non-volatile) storage of information, with a bistable circuit in the form of two first insulating-layer field effect transistors (Q 21, Q 22) for storing information at bo two nodes (N \, N ₂ ), each by connecting the gate electrode of one to the drain electrode of the other field effect transistor CQ21. Q 22) are formed in a semiconductor substrate (J), b5

with a reference potential line (Vss). which is connected to the source electrodes of both first field transistor (Q2i, Q 22), with two digit lines (D, D) that are connected to the nodes via two further field effect transistors (Q 23, <? 24), with a word line (W) that connects to the gate electrodes of the two further field effect transistors (Q 23, Q 24), and with at least two non-volatile memory elements connected between the nodes (Nu N ₂ ) and a control signal line (MG) , which store the information in the form of relative threshold voltages as a function of a control signal fed to them from the control signal line (MG) save the storage elements,

characterized,

that the storage elements are binary capacitors (MC 11. MC 12) which switch from a first capacitance value to a second capacitance value at a threshold voltage and at least one of which is a binary capacitor with a variable threshold voltage, one on a part of the surface. ; Semiconductor substrate (1) of the first conductivity type arranged semiconductor layer (2) of the second conductivity type.

a plurality of superposed insulating layers (3, 4) which are formed on a part of the surface of the semiconductor layer (2) and on a part of the surface of the semiconductor substrate (1) to form a charge trapping region, and one on the uppermost insulating layer ( 4) has formed conductive layer (5) and which on the other hand is connected via the semiconductor layer (2) to the node (Nu N ₂ ) and via the conductive layer (5) to the control signal line (MG) (Fig. 6).

The invention relates to a semiconductor storage device according to the preamble of claim 1 or 2.

Previous memory devices with insulating-layer field effect transistors (also referred to as MOS transistors) suffer from the disadvantage that the stored information is lost when the power supply is switched off. To eliminate this disadvantage an energy-independent semiconductor storage device with a bistable circuit has been developed (see Proceedings of the 7th Conference on Solid State Devices, Tokyo, 1975, pages 185-190), which has a plurality of MOS transistors and a number of energy-independent half-liter storage elements connected to the bistable circuit. At this Storage device, information is stored in normal state in the bistable circuit and at Interruption of the power supply loaded into the energy-independent semiconductor storage elements.

This already proposed energy-independent semiconductor memory device is shown in Fig. 1 and has enrichment MOS transistors QX-QA, depletion MOS transistors Q5 and <? 6 as well as with MOS transistors Q 3 and Q 4 connected in parallel, energy-independent memory elements, / .. B. Metal-Nitride-Oxide-Semiconductor Transistors (MNOS-) MT \ and MT2, on. A series of MOS transistors Qi,

Q 3 and Q 5 as well as a further row of the MOS transistors Q 2, Q 4 and (? 6 are each connected between a reference voltage source Kw and a main voltage source Kw. The MNOS transistors MTi and MT2 are connected to the gate electrodes with a control signal line MG respectively. the gates of the MOS transistors <? 3 and ζ) 4 are connected to a control signal line K. The MOS transistors Q i, Q2, Q5 and <? 6 form a normal flip-flop. At node or Verzweigungspunkien Nl and N2 signals Q and Q can be applied or removed. When the main voltage source Ko _{0 is} switched on, ie is in a stable state, a control signal K switches on the MOS transistors (? 3 and <? 4. In this way, the bistable circuit is operated as a normal flip-flop. When the Main voltage source Von is in the OFF transitional state, the control signal K causes the MOS transistors Q3 and QA to be blocked, and at the same time a write-in signal is applied to the gates of the MNOS transistors MTi and MTI via the control signal line MG N 1 and N 2 stored information entered into the transistors MTi and MTI independently of energy.

F i g. 2 illustrates the characteristic curve of p-channel MNOS transistors or energy-independent storage elements MTi and MT2. More specifically, in FIG. 2 is a hysteresis loop of the threshold voltage, the transistors MTi and illustrated with respect to the gate voltage Vc MT2 h When the control signal line, a positive pulse MG z. B. of +25 V and 1 ms, is applied, the threshold voltage V ₁ / shifts in the positive direction to +2 V. If, on the other hand, a negative pulse of z. B. -25 V and 1 ms applied to this control signal line MG , the threshold voltage V, h shifts in the negative direction to -6 V. The threshold voltage cn of +2 V and -6 V established in this way are in the MNOS transistors MTi and MT2 recorded as long as a voltage is not applied to their gate electrodes, which has a value greater than a predetermined value compared to the semiconductor substrate or the channel potentials (potentials at the nodes N 1 and / V 2) of the bistable circuit.

The information in the bistable circuit is checked to determine whether the potential at one of the nodes N I and Λ / 2 is higher or lower than the other potential. Between the potentials ar. there is always a relative difference between the nodes N 1 and N 2. When the information of the bistable circuit is transmitted to the MNOS transistors MTi and MT2 , this information is due to the voltage difference between the potential of a write pulse to be applied to the gate electrode of a MNOS transistor and the channel potential (potential of the relevant node) in a of the MNOS transistors MTi and MT2 (namely by changing the threshold voltage), while the information is written into the other MNOS transistor by the potential difference between the potential of the write pulse to be applied to the gate electrode of the other MNOS transistor and the channel pole ( Potential at the node corresponding to the other MNOS transistor) is prevented (ie, a change in the threshold voltage is prevented). When the Srjannunesauelle then reacts to the sound input

status passes, a read pulse is applied to the control signal line MG , so that the potentials at the nodes / Vl and / V 2 are returned to the potentials that were applied immediately before the writing process.

Furthermore, from US-PS 36 62 351 a memory device is known in which in a static random access memory Capacitors are used, which are parasitic capacitances When the power supply is switched on without a voltage pulse, these parasitic capacitances provide a defined Memory content However, this known memory device requires in addition to the two parasitic ones Capacities at least six field effect transistors, so a total of eight components, so that the effort is still considerable

It is therefore the object of the invention to provide a semiconductor storage device suitable for energy-independent storage to create that with only one voltage source and a low supply voltage requires the smallest possible number of components.

This object is achieved with a semiconductor memory device according to the preamble of the patent claim 1 or 2 according to the invention by the features contained in the respective characterizing part solved.

In the previous energy-independent storage device according to FIG. 1, however, there are still a few

jo solving problems. As shown in FIG. 2, in order to prevent information being written into the MNOS transistor in an erased or reset state (V, _h = +2 V), the effective gate voltage Vc, must be below -15V. As during the enrollment operation

j5 a voltage of -25 V is applied to the gate electrodes, the channel or node potential of the MNOS transistor must be below -10 V in order to prevent writing in order to reduce the effective gate voltage Va to below -15 V . As a result, the voltage of the main voltage source VOo must be below -10V. This assumes that in the manufacture of a static p-channel random access memory (RAM), which is compatible with a transistor-transistor logic circuit (TTL) with respect to the interface.

4 ^Λ > at is, the power source to be used must be of the dual power supply type so that it supplies -15 V for the main voltage source and + 5V for the reference voltage source. However, this type of power supply is disadvantageous while in use

such a high voltage is also disadvantageous from the standpoint of power saving. A major disadvantage, however, is that the number of storage devices according to FIG. 1 forming components is large. This memory device namely requires four elements more than the usual flip-flop, namely the MNOS transistors MTi and MT2 and the MOS transistors Q 3 and QA. If one is not shown that to which nodes Ni and N2 connected transfer gates or trans-

bo fer gates is required, this memory device is required ten components. This is a crucial one in terms of improving bit density Disadvantage.

A binary capacitor is to be understood as a capacitor that operates at a threshold voltage switches from a first capacity value to a second capacity value. This threshold voltage can be fixed or variable.

As a result of the invention, the number of components forming the memory device can be reduced to six, so that a higher degree of integration can be achieved. The number of connecting lines can also be be reduced, so that energy-independent semiconductor random access memory with little effort large capacity can be realized. The storage device can be powered by a single power supply low voltage can be controlled or fed, which results in a reduction in the power requirement. So it becomes a TTL (transistor-transistor-logic) power source and interface compatible for it Storage device allows.

In the following, preferred embodiments of the invention are explained in more detail in comparison to the prior art with reference to the drawing. It shows

F i g. 1 is a circuit diagram of a previous energy-independent semiconductor memory device.

Fig. 2 is a graph showing the relationship between the threshold voltage and the effective one Gate voltage of a metal-nitride-oxide-semiconductor or MNOS transistor provided in the memory device according to FIG. 1 or of the binary capacitor according to FIGS. 3 and 6,

3 is a circuit diagram of an embodiment of the semiconductor memory device according to the invention,

4 shows an enlarged scale Section through the in the memory device according to FIG. 3 provided binary capacitor,

Fig. 5 is a graph showing the relationship between the capacitance values and the threshold voltage values of the binary capacitor of Fig. 4 and

F i g. 6 shows a circuit diagram of a modified embodiment of the semiconductor memory device according to FIG the invention.

The Fi g. 1 and 2 have already been explained at the beginning.

The parts of FIG. 1 corresponding parts according to FIG. 3 are denoted by the same reference numerals as there and are therefore not explained in more detail. A pair of series-connected transistors ζ) 11 and Q 13 and a further pair of series-connected transistors Q 12 and Q 14 are shown in FIG. 3 connected between the main voltage _{source V DO} and the reference voltage source Vss so that they form an ordinary flip-flop. In contrast to FIG. 1, the voltage sources Vdd and Vss according to FIG. 3 each have -5 V and 0 V. This means that this is a single current or voltage supply. A node N 1 connected to the drain electrode of the MOS transistor Qw is connected directly to the gate electrode of the MOS transistor Q 12 and furthermore via a capacitor C 2 to the reference voltage source V «. A node N 2 at the drain electrode of the MOS transistor Qi2 is connected directly to the gate electrode of the MOS transistor Q 11 and furthermore via a capacitor C1 to the reference voltage source Vss. In addition, binary p-channel capacitors AiCl and MC2 with variable threshold voltage are provided. These capacitors are each connected on one side to the relevant node N 1 or N 2 , and on the other side jointly connected to the control signal line MG . The gate electrodes of the MOS transistors Q 13 and Q 14 are connected in common to a second control signal line CLK . The potentials at the nodes N 1 and N2 are with

Vl and V 2 respectively.

4 illustrates the structure in cross section of the binary capacitor. According to Figure 4, a p-type semiconductor layer 2 according to a doping method Ren partially formed on an n-type silicon semiconductor substrate 1. On part of the surface of the Semiconductor layer 2 and the semiconductor substrate 1 a SiOrFiIm 3 with a thickness of 2 nm (20 Å) is applied. Above the film or the layer 3 is still one

ίο SI iNU layer 4 with a thickness of about 60 nm (600 A) arranged. The laminate construction of the insulating layers 3 and 4 is similar to an ordinary one MNOS memory transistor, with a charge trapping area near the interface between layers 3 and 4 is present. On layer 4 is a conductive layer 5, e.g. B. an aluminum layer applied. The p-type semiconductor layer 2 is provided with a give away terminal, not shown, as one of the connections of the binary capacitor to the node Pin N 1 or N 2 is connected. The conductive layer 5 is connected to the control signal line MG as the other terminal. The characteristic curve of the binary capacitor of the MNOS transistor, which has a variable threshold value, is shown in FIG

2 ^r > illustrates

The threshold voltage of the MNOS device with the structure according to FIG. 4 shows according to FIG. 5 which in connection with F i g. 2 mentioned hysteresis characteristic. The capacitor CAf has between the conductive

jo the layer 5 and the p-layer 2 have a small (first) value depending on the area on which the SiO ₂ layer 3 and the p-layer 2 are arranged one above the other if there is no inversion layer or on the surface of the substrate 1 no inversion channel formed det, ie in a first state. When the inversion layer is formed, that is to say in a second state, the capacitor CM bcsiizt a large (second) value depending on the sum of the above-mentioned, superimposed areas and the Area of the channel. Depending on the voltage applied to the conductive layer 5 by the control signal line MG , the capacitor CAi is therefore switched from the first value to the second value and vice versa. In Fig. 5 is the threshold voltage in one state with via _n and in the other state with V7 // 1. More specifically, when a large positive pulse is applied to the conductive layer 5 through the control signal line MG , electrons are trapped in the interface between the insulating layers 3 and 4 gen, so that the threshold voltage, as from the Characteristic curve according to FIG. 2, shifts in the positive direction to the value Vr // 0 It is assumed that that the binary capacitor with the threshold voltage V77 / 0 is in an erased state from the control signal line AiG a large negative one Pulse is applied to the p-layer 2, the trapped electrons are released from the trap area between the insulating layers 3 and 4 driven out, so that the threshold value span voltage in the negative direction to the value Vthi ver pushes If the binary threshold voltage capacitor, the V77 / 1 has, this means that information is loaded into the capacitor. The threshold voltage of the binary capacitor is like this with variable, as well as the hysteresis curve according to Fi g. 2. In this way, the threshold voltage becomes V77 / 0 or Vn / 1 caused by the positive or negative pulse supplied via the control signal line AiC

is determined as long as there is no high voltage above a predetermined value the layer 5 is applied opposite the p-layer 2 or the substrate 1.

In the following it is assumed that the threshold voltages of the MOS transistors Q 11 - Q 14 each - 1.0 V and the threshold voltages VW ι and V / WC2 of the binary capacitors MCI and MC2 each Vm η - + 2V in the quenched state and VY // 1 = - 6 V in the write-in state. If, under this condition, the following applies: V _Mi - | = Vmο - + 2V and V / UC2 - Viii ι «- 6 V, the binary capacitors store the information» 1 «. In the case of Vmc \ = VrHi = -6 V and VW2 - V77 / 0 - + 2V, these capacitors store the information "0". The information stored in the bistable circuit can be further defined as follows: The circuit stores a "1" when Vi = -4 V and V2-0 V, and it stores a "0" when V _t = 0 V and V ; = * -4 V. Furthermore, the capacities at the nodes N 1 and N2 are designated with Cl and Cl, respectively.

In Fig. 3 it is assumed that the binary capacitors MC \ and MC2 are in the quenching state, ie VWi - V ₇ , / ₀ «+2 V and Vmc 2 = V77 / 0 = +2 V. When the power source is switched on, Vim becomes at a specified point in time a negative pulse of z. B. -25 V and 1 ms (write pulse) applied via the control signal line MG . As a result, the information contained in the bistable circuit is written into these binary capacitors MCl and MC2 . If the information of the bistable circuit is a "1", then Vi "-4 V and V2 - 0 V. In the case of the binary capacitor MC 2, which was previously in the erased state, -25 V between the conductive layer 5 and the p-layer 2 is applied so that the trapped electrons stored in the capacitor MC 2 are driven out and the threshold voltage assumes the value Vm 1, as described in connection with FIG. 2 has been explained. This means that the information present at the node N 2 has been loaded into the binary capacitor MC 2. In the case of the binary capacitor MC 1, the MOS transistor Q 11 is in the blocking state, so that Vi = -4 V is maintained. If under these conditions -25 V are applied to the capacitor MCl via the control signal line MG , the potential V, at the node N 1 changes as follows:

= -4 V + (-25 V) X

CM

CM + CZ

where CM means the capacitance of the binary capacitor AiCl. This means that -25 V is divided or divided by the capacitors CAi and C 2 and then applied to the node N 1, so that the voltage at this node N 1 is the sum of - If the ratio of CM to C 2 is approximately 1, the potential V _{1 is} equal to -16.5 V. In this case, only -8.5 V is applied across the binary capacitor AfCl so that the threshold voltage of the capacitor MCl is kept at Vm 0 . This prevents an inscription in the capacitor MC 1. More precisely: the threshold voltage of the capacitor MCl is kept at +2 V, while that of the capacitor MCl is changed to -6 V. As a result, the binary "1" becomes the bistable Circuit as »1« in the binary capacitor (s) loaded.

If the information in the bistable circuit is a "0" and thus Vi - 0 V and V2 = -4 V, the negative write pulse is applied to the binary capacitors MC I and MC2 while the threshold voltage V _Mi \ des binary capacitor MVl changed to -6 V and the threshold voltage Vmc-2 of the binary capacitor MC2 is kept at + 2 V. In this way, the information »0« is permanently loaded or entered.

The energy-independent information stored in the binary capacitors MCl and MC 2 is then fed back to the bistable circuit. For this purpose, the potentials Vi and V2 at the nodes N 1 and Nl are set to 0 V by means not shown, and the voltage on the control signal line CLK is also set to 0 V, while the transistors Q 13 and Q 14 are blocked. Under these conditions, the read signal going from 0 V to -5 V is applied to the binary capacitors MCl and MC 2. If the binary capacitors, as mentioned, store the information "!", The threshold voltages correspond to Vmc \ = +2 V and Vmc2 = -6 V. If the read signal is applied in this state, channels are formed in the binary capacitor MCl with the introduction of a large capacity. On the other hand, no channels are formed in the binary capacitor MC2, so that it has a small capacitance. Due to the voltage division by the large capacitance of the capacitor AfC 1 and the capacitance of the capacitor C2 and the small capacitance of the capacitor MCl and the capacitance of the capacitor C1, the gate voltage of the MOS transistor Q 12 is higher than that of the MOS transistor QW . As a result, the MOS transistor Q 12 is switched on, while the MOS transistor QW is blocked due to its feedback effect. This means that V, "- 4 V and V ₂ = 0 V and the information" 1 "is fed back into the bistable circuit. Then -5 V are applied to the control signal line CLK in order to turn on the MOS transistors Q 13 and Q 14. As a result of this switching through, the current source Vo ₀ supplies current to the nodes Nl and / V 2 in order to put the bistable circuit into static operation, whereupon the voltage of the control signal line MG is reduced to zero.

If the binary capacitors MCl and MC2 store the information "0", it is done in a similar way so this information "0" is read out for the bistable circuit.

Even if the threshold voltage difference between the binary capacitors AfC 1 and MC2, ie the difference between Vtoo and Vm 1, is comparatively small during the readout operation, the readout takes place in a satisfactory manner if the difference in the voltages at the nodes N i and N 2 can be determined or measured by the voltage division effected by the capacitors.

The construction of the binary capacitor is not limited to that of Fig. 4 equivalents for this purpose, for example, capacitors of the MlOS or metal-insulator-oxide-semiconductor or the MIS- or metal-insulator-semiconductor type of the type according to JA-OS 51-16 265, of the type with traps in the gate insulator or of the type in which the gate insulator or -Non-conductor from a ferroelectric insulator loading

stands.

In Fig. 6 shows a modified embodiment of the semiconductor memory device according to the invention, in which a series connection of an enhancement MOS transistor) 21 and a binary capacitor AfCIl with a variable threshold voltage and a further series connection of an enhancement MOS transistor Q22 and a binary capacitor MC 12 with variable threshold voltage between the reference voltage source Vw-0 and the control signal line MG are connected. The node N i is connected to the gate electrode of the MOS transistor Q 22 and via a capacitor C2 to the voltage source V «. The node Λ / 2 is connected to the gate electrode of the MOS transistor ζ) 21 and via a capacitor Cl to the voltage source Vss. The embodiment according to FIG. 6 differs from that according to FIG. 3 in the following points: The node N 1 is connected to a digit line D via a transmission gate or transfer gate Q23 , while the node N 2 via a transmission gate (? 24 with a further digit line D. These transmission gates ζ) 23 and Q 24 are connected to a signal word line W at the gate connections. During the writing or reading operation of the bistable circuit, the transmission gates Q 23 and Q 24 are switched through, with current being applied to the flip-flop or the bistable circuit via the digit lines D and Ö. When the information contained in the bistable circuit is loaded into the binary capacitors MCIl and MC \ 2 and vice versa, the transmission gates Q 23 and Q 24 are in the blocking state. This embodiment works with an even smaller number of MOS transistors than the embodiment according to FIG. 3.

In the described embodiments, two binary capacitors are coupled to two nodes and a single control signal line MG. However, two nodes can also be connected to a plurality of pairs of binary capacitors, and each pair of the binary capacitors can be connected to its own control signal line MG .

In the embodiments described, the two binary capacitors have a variable one Threshold voltage. Two types of binary capacitors are known: The fixed threshold voltage type and the variable threshold voltage type. In the first-mentioned type of capacitor, a first capacitance value changed to a second capacitance value in the case of a single, predetermined threshold voltage. In the device according to the invention determines the relative threshold voltage from one to the other binary capacitor to be stored Information as "1" or "0". For this reason, one binary capacitor can be used as such fixed threshold voltage and the other be designed as such with a variable threshold voltage. Optionally, a combination of a binary capacitor having a variable threshold voltage can be used with a first and a second threshold value and a binary fixed voltage capacitor with a threshold voltage lying between the first and second threshold value in the memory device can be used according to the invention.

In the embodiments described, the write and read operations are carried out as a function of the switched-on or switched-off state of the current or voltage source. The same operations can also be implemented in the switched-off state of the power source by regulating or controlling the control signal output to the control signal line MG in a predetermined manner.

In the described embodiments, the MOS transistors and the binary capacitors are all of the p-channel type. If the polarity of the supply voltage is reversed, however, these elements can also be replaced by those of the n-channel type. In this case, the current sources correspond to V _n 1, - +5 V and Vss -OV, for example.

For this purpose 2 sheets of drawings

Claims (1)

Patent claims: 1. Semiconductor storage device for energy-independent (non-volatile) storage of information, with a bistable circuit in the form of two first insulating-layer field effect transistors (Q 11, Q 12) for storing information at two nodes (Nl, N 2), which are each formed by connecting the gate electrode of one to the drain electrode of the other field effect transistor (Q 11, <? 12) in a semiconductor substrate (1), with a reference potential line (Vss). which is connected to the source electrodes of both first field effect transistors (Q 11, Q 12), with a main voltage source line (Vdd). which is connected to the drain electrodes of two second field effect transistors (Q 13, <? 14), and to at least two non-volatile memory elements connected between the nodes (Ni, N 2) and a first control signal line (MG), which store the information in the form of relative threshold voltages as a function of a control signal fed to them by the first control signal line (MG),