WO1991018338A1 - Source de courant pouvant etre commutee - Google Patents

Source de courant pouvant etre commutee Download PDF

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Publication number
WO1991018338A1
WO1991018338A1 PCT/US1990/005896 US9005896W WO9118338A1 WO 1991018338 A1 WO1991018338 A1 WO 1991018338A1 US 9005896 W US9005896 W US 9005896W WO 9118338 A1 WO9118338 A1 WO 9118338A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
transistor
coupled
sink
control line
Prior art date
Application number
PCT/US1990/005896
Other languages
English (en)
Inventor
James William Dawson
William Vincent Huott
Panagiotis Andrew Phillips
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Publication of WO1991018338A1 publication Critical patent/WO1991018338A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/267—Current mirrors using both bipolar and field-effect technology
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/04113—Modifications for accelerating switching without feedback from the output circuit to the control circuit in bipolar transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the present invention relates to current source and current mirror circuits, and more particularly to a switchable current source circuit.
  • Current source and current sink circuits often are configured in the form of a current mirror, where a current for driving a load tracks a fixed or predetermined reference current. If it is further desired to switch the load current on or off in response to a select, enable, clock or other input signal, it is possible to include a switching device in the mirror circuit. The type and location of the switching device chosen may, however, have a materially adverse impact on the magnitude or stability of the load current, circuit switching speed, power dissipation, circuit size, degree of control or other characteristics, which could be critical in a semiconductor integrated circuit environment where high density and small size are desired. Switchable current sources and current mirrors have been proposed in the prior art, e.g., U.S. Pat.
  • switches 24 and 26 do not carry the load current, but other problems are present. For example, two switches are required, and switch 24 will introduce some impedance between the gates of FETs 16 and 20 , resulting in unequal currents in the two branches of the current mirror, a significant disadvantage when precision control is desired with respect to a fixed reference current.
  • the present invention is intended to remedy the above-mentioned disadvantages and provide a current source circuit having a switching device capable of switching both the load current and the reference current on and off simultaneously, without affecting the relationship between the two currents, and without the need to pass the load or reference current through the switching device.
  • a current source circuit having a switching device capable of switching both the load current and the reference current on and off simultaneously, without affecting the relationship between the two currents, and without the need to pass the load or reference current through the switching device.
  • BICMOS circuits having both bipolar and FET devices on the same semiconductor chip
  • the present invention comprises first and second controllable current sources or sinks directly coupled to each other through a common control line; a fixed current sink or source directly coupled to the first controllable current source or sink; and a switching device directly coupled to the common control line.
  • the present invention comprises: a first current source transistor having its conduction path coupled between a first node and ground, and having its control terminal coupled to a second node; a second current source transistor having its conduction path coupled between an external circuit and ground, and having its control terminal coupled to the second node; a switching transistor having its conduction path coupled between the first node and the second node, and having its control terminal arranged to receive a select signal; a first impedance coupled between a voltage source and the first node; and a second impedance coupled between the second node and ground.
  • FIG. 1 is a functional block diagram of one embodiment of the present invention.
  • FIG. 2 is a partial schematic circuit diagram of one embodiment of FIG. 1.
  • FIG. 3 is a schematic circuit diagram of a specific embodiment of FIG. 2.
  • FIG. 4 is a partial schematic circuit diagram of an alternative embodiment of FIG. 1.
  • FIG. 5 is a schematic circuit diagram of the invention configured for use in a sense amplifier circuit.
  • FIG. 6 is a schematic circuit diagram of the invention configured for use in a bit line driver circuit.
  • FIG. 7 is a schematic circuit diagram of the invention configured for use in a word address receiver and true/complement generator circuit.
  • FIG. 8 is a schematic circuit diagram of the invention configured for use in a read/write control circuit.
  • FIG. 9 is a schematic circuit diagram of the invention configured for use in an OR/NOR logic circuit.
  • the present invention includes a first controllable current source or sink
  • element 10 directly coupled to a second controllable current source or sink 12 via a common control line 11.
  • Elements 10 and 12 may be either current sources or current sinks. Coupled to element 10 is a fixed current sink or source 16. If element 10 is a source, then element 16 should be a sink, and vice versa. In either case, element 16 is arranged to produce a fixed or predetermined reference current
  • load current which constitutes the "output" of the circuit, is preferably equal to or directly proportional to the reference current and is switchable in accordance with the invention, as will be described below.
  • FIG. 1 is a switching element 18 having an input terminal arranged to receive a switching or enabling signal as its input, the switching element output being directly coupled to the common control line 11.
  • switching element 18 is isolated from both the reference current and the load current, yet is able to control both simultaneously.
  • Another feature is that although the output of element 18 taps onto the control line 11 between the two controllable sources or sinks 10 and 12, the switching element itself does not separate the control terminals of elements 10 and
  • transistors Tl and T2 form first and second controllable current sinks 10 and 12, respectively, and are coupled together at their base terminals by common control line 11. Coupled to one end of the conductive path of Tl is a fixed current source Cl (16) , which sets a reference current flowing into node 1 (the collector of Tl) .
  • the source Cl is also coupled to a voltage source
  • the load branch of the circuit is formed by the series connection of the conductive path of T2 with ground, a load 14 and a source VCC. In this manner, the current Iload in the load branch will mirror the current Iref in the reference branch.
  • a third transistor, Nl comprises a switching element 18 and is coupled between node 1 and common control line 11. In this configuration, an impedance
  • Z is also included between line 11 and ground, in order to discharge the bases of Tl and 2 to ground for best operation.
  • Transistors Tl and T2 may be NPN bipolar transistors, transistor Nl may be an N-channel FET, impedance Z may be a resistor, and current source Cl may also be a resistor coupled to VCC, but the invention is not limited to the use of these particular device types.
  • Tl and T2 could be PNP bipolar transistors or FETs (either N-channel or P-channel)
  • Nl could be a P-channel FET
  • impedance Z could be an FET (N-channel or P-channel)
  • current source Cl could be a temperature or voltage compensation circuit, it being understood that transistor types should be properly matched.
  • impedance Z be substantially larger than any impedance inherently present in current source Cl , and that a BICMOS implementation be utilized.
  • the load 14 will typically be a current mode circuit, but the invention will also operate with other types of load circuits, with appropriate modifications as described below.
  • Switching device
  • Nl permits the load current (Iload) to be turned on and off by way of a select or enable signal applied to the control terminal of Nl (here, the gate of FET Nl) .
  • This provides several advantages over the constant current sources of the prior art, including the saving of power and the capability of performing additional logic with the loads of other current sources, if desired.
  • a further advantage of the invention of FIG. 2 is that by switching only the bases of Tl and T2 with device Nl, there is no appreciable difference between the current levels Iload and Iref set by Cl or by any other scheme. Since the base currents of Tl and T2 are typically more than an order of magnitude smaller than the collector currents of each, the current flowing through Nl is very small and device Nl can be a very small device. Among other advantages, this will present a very small load to the circuit driving the select/enable signal.
  • FIG. 4 shows an alternative embodiment of the invention using all FET devices for the current sources or sinks and the switching element.
  • PI is analogous to Tl in FIG. 2
  • P2 is analogous to T2
  • P3 is analogous to Nl.
  • the circuit of FIG. 4 has also been reoriented to form a switchable current source instead of the switchable current sink of FIG. 2.
  • the circuits of FIGS. 1 , 2 or 4 can be used to drive virtually any current-mode load circuit or any voltage-mode load circuit with an impedance low enough to prevent the transistor sourcing or sinking the load current (such as T2 in FIG. 2) from saturating. Even this, however, is not a limitation with the FET-only version shown in FIG.
  • the invention which comprises devices Tl, T2, Nl, Rl and R2 in this embodiment, controls a differential current switch formed by T3 , T4, R3 and R4.
  • Resistor Rl coupled to voltage source VCC, operates as the current source Cl of FIG. 1, and the impedance Z is provided by resistor R2.
  • the invention operates as a switchable current sink.
  • FIG. 5 shows an application of the invention in a sense amplifier circuit for use in a semiconductor random access memory.
  • a bit selection function is performed via devices Nl, N3 , N5, etc.
  • the sense amplifiers for the number of desired bit columns can all be dotted together as shown, with each sense amplifier having its own switchable current source (or sink) with a unique bit select input signal. In a typical application, only one bit select signal will be on (high) at any given time, selecting the corresponding sense amplifier/bit column. Also shown in this embodiment is the use of two switching devices in series for each column (such as Nl and
  • N2 N2 , one of which performs a read enable function and the other of which performs a bit select function.
  • bit line driver circuit for use in a memory array (FIG. 6) ; a word address receiver and true/complement generator circuit (FIG. 7) ; a read/write control circuit (FIG. 8) ; and a logic circuit, sii h as a switchable OR/NOR circuit (FIG.
  • device N2 operates as an impedance and, hence, is analogous to the impedance Z of FIG.
  • FIG. 9 a parallel, configuration of two switching devices (Nl and N2) is shown, which provides an overall "OR" function for the entire circuit. In addition, both outputs go high when the circuit is not selected.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Static Random-Access Memory (AREA)

Abstract

On décrit une source de courant pouvant être commutée et qui permet la commutation simultanée à la fois du courant de charge et du courant de référence d'un miroir de courant par l'intermédiaire d'un dispositif de commutation séparé. Le dispositif de commutation ne doit pas nécessairement porter tout le courant de charge ou de référence. Le circuit économise ainsi tout le courant lors de son interruption.
PCT/US1990/005896 1990-05-17 1990-10-15 Source de courant pouvant etre commutee WO1991018338A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US52542290A 1990-05-17 1990-05-17
US525,422 1990-05-17

Publications (1)

Publication Number Publication Date
WO1991018338A1 true WO1991018338A1 (fr) 1991-11-28

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PCT/US1990/005896 WO1991018338A1 (fr) 1990-05-17 1990-10-15 Source de courant pouvant etre commutee

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0570820A2 (fr) * 1992-05-20 1993-11-24 Siemens Aktiengesellschaft Circuit source de courant commutable et l'utilisation d'un tel circuit dans un détecteur de phase
EP1101287A1 (fr) * 1998-07-30 2001-05-23 Credence Systems Corporation Bascule mosfet a faible injection dans la charge

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4544878A (en) * 1983-10-04 1985-10-01 At&T Bell Laboratories Switched current mirror
US4740743A (en) * 1985-09-30 1988-04-26 Siemens Aktiengesellschaft Switchable bipolar current source
EP0357366A1 (fr) * 1988-08-30 1990-03-07 International Business Machines Corporation Circuit à miroir de courant amélioré

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4544878A (en) * 1983-10-04 1985-10-01 At&T Bell Laboratories Switched current mirror
US4740743A (en) * 1985-09-30 1988-04-26 Siemens Aktiengesellschaft Switchable bipolar current source
EP0357366A1 (fr) * 1988-08-30 1990-03-07 International Business Machines Corporation Circuit à miroir de courant amélioré

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0570820A2 (fr) * 1992-05-20 1993-11-24 Siemens Aktiengesellschaft Circuit source de courant commutable et l'utilisation d'un tel circuit dans un détecteur de phase
EP0570820A3 (en) * 1992-05-20 1993-12-15 Siemens Ag Switchable current source circuit and the use of such a circuit in a phase detector
EP1101287A1 (fr) * 1998-07-30 2001-05-23 Credence Systems Corporation Bascule mosfet a faible injection dans la charge
EP1101287A4 (fr) * 1998-07-30 2001-09-12 Credence Systems Corp Bascule mosfet a faible injection dans la charge

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