WO1991013465A1 - Electronic devices and methods of constructing and utilizing same - Google Patents
Electronic devices and methods of constructing and utilizing same Download PDFInfo
- Publication number
- WO1991013465A1 WO1991013465A1 PCT/US1991/001146 US9101146W WO9113465A1 WO 1991013465 A1 WO1991013465 A1 WO 1991013465A1 US 9101146 W US9101146 W US 9101146W WO 9113465 A1 WO9113465 A1 WO 9113465A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- ferroelectric
- portions
- metallic
- semiconductor
- insulator
- Prior art date
Links
- 238000000034 method Methods 0.000 title description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 39
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims abstract description 15
- 230000000946 synaptic effect Effects 0.000 claims abstract description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 11
- 230000015654 memory Effects 0.000 claims abstract description 11
- 230000001537 neural effect Effects 0.000 claims abstract description 6
- 239000012212 insulator Substances 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 15
- 239000011159 matrix material Substances 0.000 claims description 14
- 239000003990 capacitor Substances 0.000 claims description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 abstract description 8
- 210000002569 neuron Anatomy 0.000 description 6
- 230000010287 polarization Effects 0.000 description 6
- 238000013528 artificial neural network Methods 0.000 description 4
- 230000002269 spontaneous effect Effects 0.000 description 4
- 239000000872 buffer Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 229910003781 PbTiO3 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- -1 Ta^ Inorganic materials 0.000 description 1
- 229910001632 barium fluoride Inorganic materials 0.000 description 1
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 description 1
- 229910001634 calcium fluoride Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
- 238000001931 thermography Methods 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
- H01L29/803—Programmable transistors, e.g. with charge-trapping quantum well
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
Definitions
- the invention relates to bipolar three-terminal gated diodes; memory matrices including such diodes; neural synaptic networks including such diodes;
- DRAM Dynamic Random Access Memory
- bipolar transistors including such diodes; bipolar transistors; a JFET (Junction Field Effect Transistor) using such diode; GaAs and AlGaAs heterostructures; and methods of constructing and utilizing same.
- JFET Joint Field Effect Transistor
- a first embodiment of the invention provides an electronic device, comprising at least one first semiconductor portion comprising a first predetermined type of semiconductor material, and at least one second semiconductor portion comprising a second predetermined type of semiconductor material. At least a part of the second portion is contiguous with at least a part of the first portion. At least one insulator portion is contiguous with at least a part of the first and second portions. There is also included at least one metallic portion, and at least one ferroelectric portion having at least a part thereof disposed between at least a part of the insulator portion and a part of the metallic portion.
- a second embodiment provides an electronic device as described above, but wherein the insulator, ferroelectric and first metallic portions form a gate assemblage having at least one aperture therein. There is also provided at least one second metallic portion within the aperture and contiguous with at least a part of the insulator portion. The second metallic portion is contiguous with at least a part of the second semiconductor portion.
- a third embodiment provides a memory matrix comprising a plurality of bipolar three-terminal gated diodes which are reverse-biased, and wherein each diode takes the form of the electronic devices described herein.
- Another embodiment provides a neural synaptic network comprising a plurality of bipolar three-terminal gated diodes which take the form of the electronic devices described herein.
- Another embodiment provides a DRAM which uses the high dielectric constant of a ferroelectric and/or an insulator for dynamic storage without fully switching the ferroelectric from one polarization state to the other, and also uses a p-n junction as a "pass-gate" in an array.
- Another embodiment provides a bipolar transistor wherein the electronic device described herein can be incorporated as a junction in a npn or pnp bipolar transistor, either as a base, a collector or an emitter junction.
- Another embodiment provides a structure which uses the gated diode ensemble in a ferroelectric controlled p-n junction in a JFET.
- Another embodiment provides a structure wherein the electronic device described herein is used in GaAs and AlGaAs heterostructures.
- a further embodiment provides a ferroelectric gated diode which can be addressed by applying light to the ferroelectric.
- Fig. 1 is a schematic view of an electronic device according to a first embodiment.
- Fig. 2 is a schematic view of an electronic device according to a second embodiment.
- Fig. 3 shows a top view of the Fig. 2 device.
- Fig. 4 is applicant's proposed symbol for a ferroelectric gated diode.
- Fig. 5 shows a neural network according to the invention.
- Fig. 6 is applicant's symbol for a neuron assemblage as representing the elements enclosed in phantom line in Fig. 5.
- Fig. 7 shows a neural synaptic network according to the invention.
- Fig. 8 shows a plot of total junction capacitance as a function of the gate voltage.
- Fig. 9 shows another embodiment wherein the electronic device is used in GaAs and AlGaAs heterostructures.
- Fig. 10 shows a memory matrix according to the invention.
- Fig. 11 shows a device having the gate trenched in the semiconductor portion.
- Electronic devices described herein can be fabricated using the machines, techniques and methods disclosed in International Patent Application No. PCT/US89/05882 and U. S. Patent Application Serial No. 290,468.
- Fig. 1 shows electronic device 1 having first and second semiconductor portions 2 and 3.
- Ferroelectric portion 5 is sandwiched between insulator 4 and first metallic portion 6.
- portion 4 is comprised of yttrium oxide, CaF 2 , BaF 2 , Ta ⁇ , Si0 2 , Si 3 N 4 , or other linear dielectric silicon compounds which may be deposited and epitaxially regrown on Si, GaAs or InP semiconductors.
- Portion 4 may comprise a ferroelectric material which may or may not be the same as the material of portion 5.
- the assemblage of portions 4, 5 and 6 form a gate structure which is contiguous with a part of portions 2 and 3 and straddles the portions 3.
- First terminal 7 is electrically connected to portion 2.
- V j is connected to portion 3.
- Third terminal V G is electrically connected to portion 6.
- Portion 3 comprises a region of relatively high impurity or doping concentration.
- Depletion region 8 forms around portion 3.
- Portion 5 interacts with the electrical charge volume of region 8 by way of semiconductor surface modulation of region 8 or conductivity modulation.
- ferroelectric material as used herein is intended to include, but is not limited to, the fluoride family such as BaMnF ⁇ BaMgF 2 , etc., KN0 3 , and materials having a general composition of AB0 3 , such as PbTi0 3 , Pb j Zr y TiOa, Pb x La y Z ⁇ TK , and YMn0 3 , where Y can be any of the rare earth elements.
- the fluoride family such as BaMnF ⁇ BaMgF 2 , etc., KN0 3
- materials having a general composition of AB0 3 such as PbTi0 3 , Pb j Zr y TiOa, Pb x La y Z ⁇ TK , and YMn0 3 , where Y can be any of the rare earth elements.
- Figs. 2 and 3 show a second embodiment in the form of device 18 having first and second semiconductor portions 9 and 10.
- Gate assemblage 19 is formed by ferroelectric portion 12 sandwiched between insulator portion 11 and first metallic portion 13.
- Assemblage 19 has an opening 15.
- Portion 10, which comprises a region of relatively high doping concentration, straddles opening 15 to contact diametrically opposed portions of portion 11.
- portion 11 is comprised of yttrium oxide, or of the other materials discussed above in relation to Fig. 1.
- Second metallic portion 14 is disposed within opening 15 and is contiguous with a part of portions 10 and 11.
- First terminal 17 is electrically connected to portion 9.
- Second terminal V j is electrically connected to portion 14.
- Third terminal V G is electrically connected to portion 13.
- Depletion region 16 is formed between portions 9 and 10.
- Portion 12 interacts with the electrical charge volume of region 16 via semiconductor surface modulation of region 16 or conductivity modulation.
- Portion 5 or 12 is used to establish the level of leakage of the pn junction via extension of region 8 or 16, and an increase in current caused by thermal generation of carriers in region 8 or 16.
- the invention also contemplates a device wherein the ferroelectric portion is used to establish a capacitance level of the pn junction via the ferroelectric spontaneous polarization charge modulation of the total depletion region volume, including the depletion under the gated region.
- the device can also be used for DRAM architecture wherein the device uses the high dielectric constant of the ferroelectric and/or insulator for dynamic storage without fully switching the ferroelectric from one polarization state to the other, and/or use of the pn junction as a "pass-gate" in an array.
- the inventive device can also be used for constructing a bipolar transistor.
- the device can be incorporated as a junction in a npn or pnp bipolar transistor, either as a base, a collector or an emitter junction.
- the preferred configuration would be the base-collector junction by which the gain of the transistor is controlled by the state of the ferroelectric.
- the inventive device can also be used for fabricating a new type of JFET.
- the device would use the gated diode ensemble as a ferroelectric controlled pn junction in a configuration known as a JFET, wherein the ferroelectric gated diode is the gate junction.
- Fig. 4 illustrates a proposed symbol 20 for the ferroelectric gated diode according to the invention.
- the ferroelectric portion is designated by the reference number 21.
- the symbol 20 is used below in the explanation of the neural network 22.
- Fig. 5 shows network 22 composed of a ferroelectric gated diode or synaptic weight 20 connected to a neuron portion 23.
- the neuron portion 23 is enclosed in phantom lines.
- Fig. 6 presents a symbol 23 for showing the neuron portion of network
- Fig. 7 illustrates a neural synaptic network 30 having X-decoders 31, 32, 33 and 34 which are connected to neurons 35, 36, 37 and 38.
- Network 30 includes Y-decoders 39, 40, 41 and 42 which are connected, substantially transverse to the X-decoders, to neurons 43, 44, 45 and 46.
- Network 30 has typical synaptic weights 47 and 48 connected therein.
- the diode in its various configurations, including the optical configuration described below, can be used as the "weighted synaptic matrix" in neural networks.
- Such networks employ operational amplifiers, resistors, and capacitors to form an “analog storage” associative memory.
- the ferroelectric gated diode is essentially a programmable synaptic weight which can be set to a certain value during an interaction of a program being processed by such a neural network.
- the invention contemplates an optical configuration wherein the ferroelectric-gated diode can be addressed by applying light to the ferroelectric.
- the metallic gate should be transparent which can be achieved by various techniques, such as using either thin metallic film or using an indium tin oxide transparent electrode.
- the pyroelectric, as well as the ferroelectric, properties of the ferroelectric material are utilized.
- Such a device can be used for optically-read memories, infrared detectors, an optical memory, and a thermal imaging device using a matrix.
- the ferroelectric portion may be used to establish a capacitance level of the pn junction by way of the ferroelectric spontaneous polarization P s charge modulation of the total depletion region volume including the depletion under the gated region.
- Fig. 8 shows a plot wherein the abscissa represents the gate voltage V G which is equivalent to APg/Cp, where P s is the spontaneous polarization of the ferroelectric, A is the area of the gate, and C F is the ferroelectric gate capacitance.
- Fig. 8 the ordinate represents the total junction or diode capacitance.
- Point 1 along the abscissa V G represents point 2 represents The capacitance is modulated by voltage or the spontaneous polarization of the ferroelectric.
- Fig.9 shows another embodiment in the form of a high electron mobility transistor (HEMT) 50.
- HEMT 50 includes a metal portion 51, a ferroelectric portion 52, an AlGaAs portion 53 which in this case serves as the insulator portion, a gallium arsenide buffer layer 54, and a gallium arsenide portion 56.
- Portion 55 represents the two dimensional electron gas.
- Fig. 9 when used in the gallium arsenide and AlGaAs heterostructure, modulates gas 55 in the configuration known as the high electron mobility transistor.
- HEMT 50 With the ferroelectric gate, HEMT 50 becomes a storage cell for high speed memories.
- Fig. 10 shows a memory matrix 60 having row decoders 61 electrically connected to sense amplifiers and X-output buffers 62. Column decoders 63 are electrically connected to sense amplifiers and Y-output buffers 64. Interconnected in the array are ferroelectric gated diodes 67.
- Matrix 60 has read enable and write enable circuits 65, and gate control circuits 66. In the matrix array, it is preferable to have the diodes 67 reverse- biased.
- n-type regions and p-type regions shown in Figs. 1 and 2 may be reversed.
- Fig. 11 shows a device similar to Fig. 1, but in which the ferroelectric gate assemblage, including the metallic, the ferroelectric, and the insulator portions, is trenched within the first semiconductor portion, and in which the second semiconductor portion includes first and second portions disposed on opposite sides of the trenched assemblage.
- a region of the second semiconductor portion (the first second semiconductor portion) has a relatively high doping concentration.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920702049A KR920704360A (en) | 1990-02-26 | 1991-02-22 | Electronics, memory matrices and their neural networks |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US48427390A | 1990-02-26 | 1990-02-26 | |
US484,273 | 1990-02-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1991013465A1 true WO1991013465A1 (en) | 1991-09-05 |
Family
ID=23923463
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1991/001146 WO1991013465A1 (en) | 1990-02-26 | 1991-02-22 | Electronic devices and methods of constructing and utilizing same |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0517842A1 (en) |
JP (1) | JPH05503609A (en) |
KR (1) | KR920704360A (en) |
AU (1) | AU7479291A (en) |
WO (1) | WO1991013465A1 (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0568064A2 (en) * | 1992-05-01 | 1993-11-03 | Texas Instruments Incorporated | Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer |
US5436490A (en) * | 1991-10-26 | 1995-07-25 | Rohm Co., Ltd. | Semiconductor device having ferroelectrics layer |
US5523964A (en) * | 1994-04-07 | 1996-06-04 | Symetrix Corporation | Ferroelectric non-volatile memory unit |
US5572052A (en) * | 1992-07-24 | 1996-11-05 | Mitsubishi Denki Kabushiki Kaisha | Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer |
WO1997007546A1 (en) * | 1995-08-21 | 1997-02-27 | Symetrix Corporation | Metal insulator semiconductor structure with polarization-compatible buffer layer |
US6664115B2 (en) | 1992-10-23 | 2003-12-16 | Symetrix Corporation | Metal insulator structure with polarization-compatible buffer layer |
DE19610907B4 (en) * | 1995-03-22 | 2006-10-05 | Samsung Electronics Co., Ltd., Suwon | Ferroelectric semiconductor memory device and method for its production |
CN100466288C (en) * | 2005-06-30 | 2009-03-04 | 株式会社东芝 | Semiconductor device having ferroelectric film as gate insulating film and manufacturing method thereof |
WO2023204767A1 (en) * | 2022-04-20 | 2023-10-26 | National University Of Singapore | Inversion-type ferroelectric capacitive memory |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009218438A (en) * | 2008-03-11 | 2009-09-24 | Sony Corp | Solid-state imaging device, its manufacturing method, and electronic device |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2695397A (en) * | 1953-06-16 | 1954-11-23 | Bell Telephone Labor Inc | Ferroelectric storage circuits |
US2791761A (en) * | 1955-02-18 | 1957-05-07 | Bell Telephone Labor Inc | Electrical switching and storage |
US2791760A (en) * | 1955-02-18 | 1957-05-07 | Bell Telephone Labor Inc | Semiconductive translating device |
US3400383A (en) * | 1964-08-05 | 1968-09-03 | Texas Instruments Inc | Trainable decision system and adaptive memory element |
US3585415A (en) * | 1969-10-06 | 1971-06-15 | Univ California | Stress-strain transducer charge coupled to a piezoelectric material |
US3648258A (en) * | 1969-07-01 | 1972-03-07 | Sperry Rand Corp | Optical memory circuit |
US4161038A (en) * | 1977-09-20 | 1979-07-10 | Westinghouse Electric Corp. | Complementary metal-ferroelectric semiconductor transistor structure and a matrix of such transistor structure for performing a comparison |
US4482841A (en) * | 1982-03-02 | 1984-11-13 | Texas Instruments Incorporated | Composite dielectrics for low voltage electroluminescent displays |
US4677457A (en) * | 1985-01-28 | 1987-06-30 | U.S. Philips Corporation | Semiconductor device with bidimensional charge carrier gas |
US4814840A (en) * | 1985-08-09 | 1989-03-21 | Masahiro Kameda | High-density reprogrammable semiconductor memory device |
-
1991
- 1991-02-22 WO PCT/US1991/001146 patent/WO1991013465A1/en not_active Application Discontinuation
- 1991-02-22 AU AU74792/91A patent/AU7479291A/en not_active Abandoned
- 1991-02-22 KR KR1019920702049A patent/KR920704360A/en not_active Application Discontinuation
- 1991-02-22 EP EP91906321A patent/EP0517842A1/en not_active Withdrawn
- 1991-02-22 JP JP3505989A patent/JPH05503609A/en active Pending
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2695397A (en) * | 1953-06-16 | 1954-11-23 | Bell Telephone Labor Inc | Ferroelectric storage circuits |
US2791761A (en) * | 1955-02-18 | 1957-05-07 | Bell Telephone Labor Inc | Electrical switching and storage |
US2791760A (en) * | 1955-02-18 | 1957-05-07 | Bell Telephone Labor Inc | Semiconductive translating device |
US3400383A (en) * | 1964-08-05 | 1968-09-03 | Texas Instruments Inc | Trainable decision system and adaptive memory element |
US3648258A (en) * | 1969-07-01 | 1972-03-07 | Sperry Rand Corp | Optical memory circuit |
US3585415A (en) * | 1969-10-06 | 1971-06-15 | Univ California | Stress-strain transducer charge coupled to a piezoelectric material |
US4161038A (en) * | 1977-09-20 | 1979-07-10 | Westinghouse Electric Corp. | Complementary metal-ferroelectric semiconductor transistor structure and a matrix of such transistor structure for performing a comparison |
US4482841A (en) * | 1982-03-02 | 1984-11-13 | Texas Instruments Incorporated | Composite dielectrics for low voltage electroluminescent displays |
US4677457A (en) * | 1985-01-28 | 1987-06-30 | U.S. Philips Corporation | Semiconductor device with bidimensional charge carrier gas |
US4814840A (en) * | 1985-08-09 | 1989-03-21 | Masahiro Kameda | High-density reprogrammable semiconductor memory device |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5436490A (en) * | 1991-10-26 | 1995-07-25 | Rohm Co., Ltd. | Semiconductor device having ferroelectrics layer |
US5912486A (en) * | 1992-05-01 | 1999-06-15 | Texas Instruments Incorporated | Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer |
US5650646A (en) * | 1992-05-01 | 1997-07-22 | Texas Instruments Incorporated | Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer |
EP0568064A3 (en) * | 1992-05-01 | 1994-04-06 | Texas Instruments Inc | |
US5393352A (en) * | 1992-05-01 | 1995-02-28 | Texas Instruments Incorporated | Pb/Bi-containing high-dielectric constant oxides using a non-P/Bi-containing perovskite as a buffer layer |
EP0568064A2 (en) * | 1992-05-01 | 1993-11-03 | Texas Instruments Incorporated | Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer |
US5572052A (en) * | 1992-07-24 | 1996-11-05 | Mitsubishi Denki Kabushiki Kaisha | Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer |
US6664115B2 (en) | 1992-10-23 | 2003-12-16 | Symetrix Corporation | Metal insulator structure with polarization-compatible buffer layer |
US6310373B1 (en) | 1992-10-23 | 2001-10-30 | Symetrix Corporation | Metal insulator semiconductor structure with polarization-compatible buffer layer |
US5559733A (en) * | 1994-04-07 | 1996-09-24 | Symetrix Corporation | Memory with ferroelectric capacitor connectable to transistor gate |
US5523964A (en) * | 1994-04-07 | 1996-06-04 | Symetrix Corporation | Ferroelectric non-volatile memory unit |
DE19610907B4 (en) * | 1995-03-22 | 2006-10-05 | Samsung Electronics Co., Ltd., Suwon | Ferroelectric semiconductor memory device and method for its production |
WO1997007546A1 (en) * | 1995-08-21 | 1997-02-27 | Symetrix Corporation | Metal insulator semiconductor structure with polarization-compatible buffer layer |
CN100466288C (en) * | 2005-06-30 | 2009-03-04 | 株式会社东芝 | Semiconductor device having ferroelectric film as gate insulating film and manufacturing method thereof |
WO2023204767A1 (en) * | 2022-04-20 | 2023-10-26 | National University Of Singapore | Inversion-type ferroelectric capacitive memory |
Also Published As
Publication number | Publication date |
---|---|
AU7479291A (en) | 1991-09-18 |
JPH05503609A (en) | 1993-06-10 |
KR920704360A (en) | 1992-12-19 |
EP0517842A1 (en) | 1992-12-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5757051A (en) | Static memory cell and method of manufacturing a static memory cell | |
US5635407A (en) | HGCDTE S-I-S two color infrared detector | |
US5465249A (en) | Nonvolatile random access memory device having transistor and capacitor made in silicon carbide substrate | |
EP0526897B1 (en) | Three terminal tunnel device | |
US6013950A (en) | Semiconductor diode with external field modulation | |
US5684737A (en) | SRAM cell utilizing bistable diode having GeSi structure therein | |
Stellwag et al. | A vertically integrated GaAs bipolar DRAM cell | |
WO1991013465A1 (en) | Electronic devices and methods of constructing and utilizing same | |
EP0193842B1 (en) | Integrated semiconductor circuit with two epitaxial layers of different conductivity types | |
US3740620A (en) | Storage system having heterojunction-homojunction devices | |
US5710448A (en) | Integrated polysilicon diode contact for gain memory cells | |
Carns et al. | A novel high speed, three element Si-based static random access memory (SRAM) cell | |
US5461245A (en) | Article comprising a bipolar transistor with floating base | |
JP2734435B2 (en) | Tunnel transistor and storage circuit | |
JP3222166B2 (en) | Programmable resistance element | |
Fang et al. | A silicon double switching inversion-controlled switch for multiple-valued logic applications | |
US4720735A (en) | Phototransistor having a non-homogeneously base region | |
JPH088360B2 (en) | Tunnel transistor and manufacturing method thereof | |
JP2658934B2 (en) | Tunnel transistor | |
Koga et al. | Room temperature negative differential conductance in three-terminal silicon surface tunneling device | |
Dungan et al. | Room temperature dynamic memories for GaAs integrated circuits | |
JP3142067B2 (en) | Semiconductor device | |
JP2861590B2 (en) | Tunnel transistor | |
CA2117933A1 (en) | High-density read-only data storage | |
Levy | Application and integration of quantum effect devices for cellular VLSI |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AU JP KR |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FR GB GR IT LU NL SE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1991906321 Country of ref document: EP |
|
COP | Corrected version of pamphlet |
Free format text: PAGE 14,AMENDED CLAIMS,CORRECTED |
|
WWP | Wipo information: published in national office |
Ref document number: 1991906321 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1991906321 Country of ref document: EP |