JP2734435B2 - Tunnel transistor and storage circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tunnel transistor and a storage circuit, and more particularly to a tunnel transistor having a plurality of negative resistance characteristics and a multilevel storage circuit used as a basic element and a basic circuit of an ultra-high integrated circuit.

[0002]

2. Description of the Related Art Static memory cells and dynamic memory cells are used as basic circuits for storing data, and the integration density thereof has been increasing year by year with the improvement of fine processing technology. In the future, a memory with a larger capacity will be required. However, in recent years, the problem of heat generation and the limit of miniaturization have been reported, and it is not easy to further increase the degree of integration. It is necessary to configure a storage circuit with a small number of elements. Further, in order to further increase the storage capacity, a new storage circuit that stores a plurality of bits in a unit memory cell instead of the conventional 1 bit / memory cell is desired.

As one of the methods for forming a memory circuit with a small number of elements, silicon (Si)
OS-type field effect transistors (FETs) and Schottky junction field-effect transistors (MESFETs) having a structure in which a substrate is made of GaAs having electron mobility several times higher than that of Si and a gate electrode is formed directly on a conductive layer on the surface of the substrate. ) Has a different operating principle, and a device using a tunnel transistor having a negative resistance characteristic has been proposed. As the conventional tunnel transistor and storage circuit (bistable circuit), for example, there is one proposed by the present inventor (JP-A-5-41520: title of "semiconductor device").

[0004] This conventional tunnel transistor is an MO transistor.
Active use of the tunnel effect, which is a problem in the limit of miniaturization of SFET, enables multifunctional operation by using negative resistance characteristics together with a structure suitable for miniaturization, and increases the density of storage integrated circuits. To make it possible.

FIG. 6 is a schematic sectional view showing an example of the above-mentioned conventional tunnel transistor. In FIG.
A source 2 made of a degenerate semiconductor containing impurities having one conductivity type at a high concentration and an impurity having a high concentration of impurities having a conductivity type different from that of the source 2 and having a steep impurity distribution are provided on the upper side. Drain 3 and source 2
A degenerate channel layer 4 having the same conductivity type as that described above is formed, and the channel layer 4 is formed between the source and the drain.

An insulating layer 5 made of a material having a wide band gap is formed on the channel layer 4 and a part of each of the source 2 and the drain 3, and a gate electrode 6 is formed on the insulating layer 5. Is formed. Further, a source electrode 7 forming an ohmic junction with the source 2 and a drain electrode 8 forming an ohmic junction with the drain 3 are formed.

FIG. 7A shows a memory circuit using the conventional tunnel transistor and resistor, and FIG. 7B shows current-voltage characteristics of the memory circuit. In FIG. 7A, STT is a conventional tunnel transistor having a structure shown in FIG.
The terminal is connected to the output terminal, the gate is connected to the input terminal, and the drain is grounded. In FIG. 7B, the vertical axis indicates the current I and the horizontal axis indicates the voltage V, and indicates the characteristics T of the tunnel transistor, the load line L, the first stable point S1, and the second stable point S2.

The operation of the conventional tunnel transistor and the operation of the memory circuit are described below. I-GaAs (where i is an abbreviation that stands for intrinsic or non-doped semiconductor which can be regarded as substantially intrinsic): n ⁺ -Ga
As, the drain 3 p ⁺ -GaAs, the channel layer 4 n ⁺ -
GaAs, insulating layer 5 in the i-Al _0.5 Ga _0.5 As, aluminum (Al) to the gate electrode 6, an example will be described using gold (Au) to the source electrode 7 and drain electrode 8.

When the source electrode 7 is set to the ground potential, no voltage is applied to the gate electrode 6, and a positive voltage is applied to the drain electrode 8, the source 2 (n ⁺ -GaAs) and the drain 3
(P ⁺ -GaAs) and the channel layer 4 (n ⁺ -GaAs).
s) becomes forward biased. In this bias direction, the drain current flows more easily than in the reverse bias.
Below the voltage at which the carrier diffusion current does not become significant (GaAs
In the case of s, 0.7 V or less), this diffusion current hardly flows. However, between the channel layer 4 (n ⁺ -GaAs) and the drain 3 (p ⁺ -GaAs), a narrow Esaki diode (a tunnel diode formed by an n ⁺ -p ⁺ tunnel junction) is used. Tunnel current flows.

When the forward voltage between the source and the drain is increased, electrons in the conduction band of the channel layer 4 initially tunnel to the empty state of the valence band of the drain 3 because of the tunneling. The current increases. When the forward voltage between the source and the drain is further increased, the energy overlap between the conduction band and the valence band decreases, and the current decreases. Further, when the forward voltage between the source and the drain is increased, electrons in the conduction band of the channel layer 4 and holes in the drain 3 thermally cross the potential barrier at the junction, and the current (diffusion current) is again increased. Increase.

Accordingly, as shown by T in FIG. 7B, the voltage-current characteristic of this tunnel transistor becomes N-shaped, and a negative resistance characteristic portion in which the drain current decreases as the voltage increases appears. . Since the magnitude of the tunnel current depends on the concentration of electrons induced in the semiconductor channel layer 4,
Voltage applied to gate electrode 6 (that is, gate voltage)
As a result, the negative resistance characteristic is controlled, and the operation of a transistor having functionality can be obtained.

When the tunnel transistor and a resistor having an appropriate resistance value are connected in series, a storage circuit as shown in FIG. 7A can be formed. When the voltage-current characteristics as shown in FIG. 7B are obtained, there are two stable points S1 and S2 as outputs. Which state is set is determined by the history. Since the negative resistance characteristic of the tunnel transistor can be changed by the gate voltage as described above, a state having only one stable point can be created by appropriately selecting the gate voltage.

Therefore, by generating a state of only one stable point even for a moment by the pulse voltage, the subsequent state is determined to be closer to the state at that time, and the determined state is maintained as long as the input does not change. For this reason, this recording circuit becomes a static memory operated by an input pulse. That is, according to the conventional tunnel transistor, the functional operation utilizing the negative resistance characteristic enables
A storage circuit can be configured with only one tunnel transistor STT and one resistor R, that is, with half the number of elements than before.

[0014]

However, only one bit can be stored in one storage circuit using the above-mentioned conventional tunnel transistor, and the storage density of information can only be doubled. . Therefore, in order to further increase the storage density, a multi-valued storage circuit in which one storage circuit can store information of another bit is desired.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a novel tunnel transistor having a plurality of negative resistance characteristics and a storage circuit capable of storing multi-values using the tunnel transistor.

[0016]

In order to achieve the above object, a tunnel transistor according to the present invention comprises a source and a drain, which are formed on a substrate and are separated from each other, each of which is made of a semiconductor containing a high concentration of impurities; One or more connection regions formed on a substrate between a source and a drain and formed of a degenerated semiconductor having a high impurity concentration of a first conductivity type and a steep impurity distribution; A plurality of channel layers formed on the substrate so as to join between the connection region and the drain and inducing carriers of a second conductivity type different from the first conductivity type; a source, a drain, the connection region, and The semiconductor device has a structure including an insulating layer formed over a channel layer, and a source electrode, a drain electrode, and a gate electrode formed over the source, drain, and the insulating layer, respectively. .

In the tunnel transistor of the present invention,
At least one of the plurality of channel layers and the connection region between the source and the drain, between the plurality of channel layers and the connection region, between the source and the channel layer, and between the drain and the channel layer. A bond is formed.

Further, in order to achieve the above object, the storage circuit of the present invention has the above structure, wherein the drain electrode or the source electrode is connected to the output terminal, and the source electrode or the drain electrode is connected to the low potential side power supply terminal. A first tunnel transistor to which a reset pulse or a write pulse is applied to a gate electrode, one end connected to a connection point between the first tunnel transistor and the output terminal, and the other end connected to a high potential side power supply terminal. This is a configuration including a connected resistive load.

Further, the memory circuit of the present invention uses a second tunnel transistor having the same structure as the first tunnel transistor in place of the resistive load, and uses the gate electrode and the drain electrode of the second tunnel transistor. The source terminal is connected to a high potential side power supply terminal, and a source electrode is connected to a connection point between the first tunnel transistor and the output terminal.

In the storage circuit of the present invention, since the first tunnel transistor having a plurality of band-to-band tunnel junctions is used, its voltage-current characteristics have a plurality of negative resistance characteristics and a plurality of stable points. Can be configured to exist.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic sectional view showing a layer structure of a first embodiment of a tunnel transistor according to the present invention.
6, the same components as those in FIG. 6 are denoted by the same reference numerals. In FIG. 1, the channel layer 4 is divided into three portions, and a connection region 9 made of a degenerated semiconductor having a high impurity concentration and a steep impurity distribution containing impurities of a different conductivity type from the channel layer 4 is formed of these three channels. It is provided between layers 4. Therefore, in the first embodiment, there are three channel layers 4 and two connection regions 9, and five n ⁺ -p ⁺ inter-band tunnel junctions are formed between the source 2 and the drain 3. ing.

Next, with respect to the operation of the first embodiment, the substrate 1 is i-GaAs, and the source 2 is n ⁺ -GaAs.
s, the drain 3 p ⁺ -GaAs, the channel layer 4 n ⁺ -
GaAs, will be described insulating layer 5 in the _{i-Al 0.5 Ga 0.5 As,} Al gate electrode 6, Au to the source electrode 7 and drain electrode 8, the p ⁺ -GaAs the connection region 9 as an example.

When the source electrode 7 is set to the ground potential, no voltage is applied to the gate electrode 6, and a positive voltage is applied to the drain electrode 8, the left end of the p ⁺ -GaAs connection region 9 and p ⁺
A total of three n ⁺ -p ⁺ tunnel junctions between the left end of the -GaAs drain 3 and the channel layer 4 are forward-biased where a negative resistance appears, and each right end of the p ⁺ -GaAs connection region 9 is connected to the channel. A total of two n ⁺ -p ⁺ tunnel junctions with layer 4 are reverse biased exhibiting low resistance characteristics. Therefore, of the five n ⁺ -p ⁺ tunnel junctions, 3
One tunnel junction is forward biased and two tunnel junctions are reverse biased.

Since the reverse-biased tunnel junction has a much lower resistance than the forward-biased tunnel junction, the current between the source 2 and the drain 3 mainly depends on the high-resistance forward-biased tunnel junction. Is determined by the characteristics of Therefore, when a positive voltage is applied to the drain electrode 8, three negative resistance characteristics appear continuously.

On the other hand, when a negative voltage is applied to the drain electrode 8, the entire region between the left end of the p ⁺ -GaAs connection region 9 and the left end of the p ⁺ -GaAs drain 3 and the channel layer 4 is reduced. The three n ⁺ -p ⁺ tunnel junctions are reverse biased and a total of two n ⁺ -p ⁺ tunnel junctions between each right end of the p ⁺ -GaAs connection region 9 and the channel layer 4 have a negative resistance. The characteristic of the source-drain voltage and the drain current at this time is
As shown by a curve T in FIG. 4B, two continuous negative resistance characteristics appear. As described above, in this embodiment, a plurality of negative resistance characteristics that can be obtained only by one in the conventional tunnel transistor can be made to appear.

Next, a method of manufacturing the tunnel transistor according to the first embodiment will be described using the same materials as those used in the description of the operation.

First, on a semi-insulating GaAs substrate, a thickness of 50
0 nm i-GaAs and 14 nm thick tellurium (T
e) Doped n ⁺ -GaAs (Te = 1 × 10 ¹⁹ c
m ^-3 ) using molecular beam crystal growth (MBE: Moleculer Beam Epi)
taxy). Subsequently, a substrate position to be a source region is dug by etching, and selenium (Se) -doped n ⁺ -GaAs is buried therein by a vapor phase growth method to form the source 2. Subsequently, the positions of the substrate serving as the drain region and the connection region are removed by etching, and carbon (C) -doped p ⁺ -GaAs is added to the organic metal MBE (MO).
The drain 3 and the connection region 9 are formed by MBE (Metal Organic Moleculer Beam Epitaxy).

Subsequently, a 30 nm-thick i
-Al _0.5 Ga _0.5 As is grown by MBE to form the insulating layer 5. Finally, Al is deposited on the insulating layer and processed into a gate shape to form the gate electrode 6, and then Au is deposited on the n ⁺ -GaAs source and the p ⁺ -GaAs drain to form the source electrode 7 and Drain electrode 8
Is formed to complete the structure of the tunnel transistor of the first embodiment.

When the characteristics of the manufactured tunnel transistor were evaluated, three negative resistance characteristics were observed when a positive drain voltage was applied, and two negative resistance characteristics were observed when a negative drain voltage was applied. It has been confirmed that the magnitude of the negative resistance characteristic of is modulated by the gate voltage.

Next, a description will be given of a second embodiment of the tunnel transistor according to the present invention.

FIG. 2 is a schematic sectional view showing the layer structure of a second embodiment of the tunnel transistor according to the present invention.
In the figure, the same components as those in FIGS. 1 and 6 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 2, the source 21 is made of a degenerated semiconductor having a high impurity concentration and the same impurity type as the connection region 9 and having a steep impurity distribution. In the second embodiment, there are three channel layers 4 and two connection regions 9, and between the source 21 and the drain 3, there are 6 channels.
Two n ⁺ -p ⁺ interband tunnel junctions are formed.
In this structure, since the source 21 and the drain 3 have the same structure, there is a feature that the manufacturing process is simplified as compared with the first embodiment.

Next, regarding the operation of the second embodiment, the substrate 1 is i-GaAs, and the source 21 is p ⁺ -GaAs.
s, the drain 3 p ⁺ -GaAs, the channel layer 4 n ⁺ -
GaAs, will be described insulating layer 5 in the _{i-Al 0.5 Ga 0.5 As,} Al gate electrode 6, Au to the source electrode 7 and drain electrode 8, the p ⁺ -GaAs the connection region 9 as an example.

The source electrode 7 is set to the ground potential and the gate
No voltage is applied to the pole 6 and a positive voltage is applied to the drain electrode 8.
When applied, p⁺Each left end of p-GaAs connection region 9 and p⁺
The entire distance between the left end of the GaAs drain 3 and the channel layer 4
3 n in part⁺-P⁺Tunnel junction is a manifestation of negative resistance
Forward biased and p⁺-GaAs connection region 9
Right end and p⁺ -Right end of GaAs source 21 and channel layer
A total of three n between 4⁺-P⁺Tunnel junctions are low
Reverse biased showing anti-characteristics. Therefore, six
N⁺-P⁺Three of the tunnel junctions
Forward biased, three tunnel junctions in reverse
Be biased.

Therefore, in the second embodiment, since the source 21 and the drain 3 have a symmetric structure,
Even if a negative voltage is applied to the drain electrode 8, it is divided into three forward-biased tunnel junctions and three reverse-biased tunnel junctions as in the case where a positive voltage is applied. Therefore, when the drain voltage is applied in either direction, three negative resistance characteristics appear continuously.

Next, a method of manufacturing the tunnel transistor according to the second embodiment will be described using the same materials as those used in the description of the operation.

First, on a semi-insulating GaAs substrate, a thickness of 50
0 nm i-GaAs and 14 nm thick Te-doped n ⁺ -GaAs (Te = 1 × 10 ¹⁹ cm ⁻³ ) are grown by MBE. Subsequently, each position of the substrate serving as a source region, a drain region and a connection region is removed by etching, and C ⁺ -doped p ⁺ -GaAs is buried therein by a MOMBE method to form the source 21, the drain 3 and the connection region 9 respectively. I do.

Subsequently, a 30 nm-thick i
-Al _0.5 Ga _0.5 As is grown by MBE to form the insulating layer 5. Finally, Al is deposited on the insulating layer and processed into a gate shape to form the gate electrode 6, and then Au is deposited on the p ⁺ -GaAs source and the p ⁺ -GaAs drain to form the source electrode 7 and Drain electrode 8
Is formed to complete the structure of the tunnel transistor according to the second embodiment.

When the characteristics of the manufactured tunnel transistor were evaluated, three negative resistance characteristics were observed when positive and negative drain voltages were applied, and these negative resistance characteristics were large depending on the gate voltage. Was confirmed to be modulated.

Next, a description will be given of a third embodiment of the tunnel transistor according to the present invention.

FIG. 3 is a schematic sectional view showing the layer structure of a third embodiment of the tunnel transistor according to the present invention.
6, the same components as those in FIGS. 1, 2, and 6 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 3, the drain 31 is made of a degenerated semiconductor containing impurities of the same conductivity type as the source 2 and the connection region 9 at a high concentration. In the third embodiment, there are three channel layers 4 and two connection regions 9, and four n ⁺ -p ⁺ interband tunnel junctions are formed between the source 2 and the drain 31. . In this structure, since the source 2 and the drain 31 have the same structure, the manufacturing process is simplified as compared with the first embodiment. In addition, when there is no connection region 9, a normal transistor structure is used. The feature is that a composite circuit with the transistor (FET) can be easily formed.

Next, regarding the operation of the third embodiment, the substrate 1 is i-GaAs, and the source 2 is n ⁺ -GaAs.
s, the drain 31 n ⁺ -GaAs, a channel layer 4 n ⁺
-GaAs, be described insulating layer 5 in the _{i-Al 0.5 Ga 0.5 As,} Al gate electrode 6, Au to the source electrode 7 and drain electrode 8, the p ⁺ -GaAs the connection region 9 as an example.

When the source electrode 7 is set to the ground potential and a voltage is not applied to the gate electrode 6 but a positive voltage is applied to the drain electrode 8, the distance between each left end of the p ⁺ -GaAs connection region 9 and the channel layer 4 is increased. Are two n ⁺ -p ⁺ tunnel junctions,
P ⁺ -GaAs is biased in the forward direction where negative resistance appears.
2 between each right end of the s connection region 9 and the channel layer 4.
The two n ⁺ -p ⁺ tunnel junctions are reverse biased, exhibiting low resistance characteristics. Thus, of the four n ⁺ -p ⁺ tunnel junctions, two tunnel junctions are forward biased and two tunnel junctions are reverse biased.

Therefore, in the third embodiment, since the source 2 and the drain 31 have a symmetric structure,
Even if a negative voltage is applied to the drain electrode 8, it is divided into two forward-biased tunnel junctions and two reverse-biased tunnel junctions as in the case where a positive voltage is applied. Therefore, no matter which direction the drain voltage is applied, two negative resistance characteristics appear continuously.

Next, a method of manufacturing the tunnel transistor according to the third embodiment will be described using the same materials as those used in the description of the operation.

First, on a semi-insulating GaAs substrate, a thickness of 50
0 nm i-GaAs and 14 nm thick Te-doped n ⁺ -GaAs (Te = 1 × 10 ¹⁹ cm ⁻³ ) are grown by MBE. Subsequently, each position of the substrate serving as a source region and a drain region is dug by etching, and Se-doped n ⁺ -GaAs is buried therein by a vapor growth method to form the source 2 and the drain 31 respectively. continue,
The position of the substrate serving as the connection region 9 is removed by etching, and C-doped p ⁺ -GaAs is buried therein by the MOMBE method to form the connection region 9.

Subsequently, a 30 nm-thick i
-Al _0.5 Ga _0.5 As is grown by MBE to form the insulating layer 5. Finally, Al is deposited on the insulating layer and processed into a gate shape to form the gate electrode 6, and then Au is deposited on the p ⁺ -GaAs source and the p ⁺ -GaAs drain to form the source electrode 7 and Drain electrode 8
Is formed to complete the structure of the tunnel transistor according to the third embodiment.

When the characteristics of the manufactured tunnel transistor were evaluated, two negative resistance characteristics were observed when positive and negative drain voltages were applied, and these negative resistance characteristics were large depending on the gate voltage. Was confirmed to be modulated. In addition, a normal n-channel transistor manufactured at the same time exhibits depletion mode characteristics, and it has been confirmed that the transistor of this embodiment and a transistor of a normal structure can be easily mixed.

Next, a description will be given of a first embodiment of the storage circuit according to the present invention. FIG. 4A is a circuit diagram of a first embodiment of the storage circuit according to the present invention, and FIG. 4B is a voltage-current characteristic diagram thereof. In FIG. 4A, in the storage circuit of this embodiment, the drain or source of the tunnel transistor M-STT of the present invention is connected to the power supply voltage Vdd input terminal via the resistor R, while the output terminal OUT is connected.
, Its source or drain is grounded, and its gate is connected to the input terminal IN.

Here, the tunnel transistor M-STT
Assuming that the tunnel transistor according to the third embodiment shown in FIG. 3 is used and the resistor R has an appropriate resistance value,
The relationship between the drain-source voltage V and the drain current I of the tunnel transistor M-STT in FIG.
As described above, as shown by T in FIG.
It has two negative resistance characteristics, and outputs S1, S2 and S, which are the intersections of the resistor R with the load line L.
There are three stable points:

The storage circuit shown in FIG. 4A operates as a multi-value storage circuit that is in a stable state at any of three stable points by applying a reset pulse and a write pulse to the input.

Next, the operation of the storage circuit will be described. First, when a reset pulse of a positive polarity with respect to a predetermined voltage is input to the input terminal IN and the characteristics of the tunnel transistor M-STT are temporarily set to the characteristics indicated by TR in FIG. The state is uniquely determined in the initial state indicated by S1 near the intersection of the characteristic TR and the load line L.

Next, when a second write pulse V2 of negative polarity with respect to a predetermined voltage is applied to the gate of the tunnel transistor M-STT via the input terminal IN, the characteristics of the tunnel transistor M-STT instantaneously change as shown in FIG. (B) T2
, And then the stable state changes from S1 to the characteristic T2.
To the state shown by S2 near the intersection of the load line L with the load line L.

Next, a first transistor having a negative polarity with respect to a predetermined voltage and having a smaller absolute value of the peak value than the second write pulse V2 is applied to the gate of the tunnel transistor M-STT via the input terminal IN. When the write pulse V1 is applied, the characteristic of the tunnel transistor M-STT momentarily becomes the characteristic indicated by T1 in FIG.
The state moves to the state indicated by 1.

Similarly, a third transistor having a negative polarity with respect to a predetermined voltage at the gate of the tunnel transistor M-STT via the input terminal IN and having an absolute value of a peak value larger than that of the second write pulse V2. When the write pulse V3 is applied, the characteristic of the tunnel transistor M-STT momentarily becomes the characteristic indicated by T3 in FIG. 4B, and then the stable state shifts from the intersection of the characteristic T3 and the load line L to the state indicated by S3. I do.

As described above, as the write pulse, V1,
By applying V2 or V3 to the gate of the tunnel transistor M-STT, the characteristics are temporarily changed to T1 and T2 in FIG.
Alternatively, if T3 is set, the stable state after the application of the write pulse moves along the load line L and is uniquely determined by S1, S2, or S3. Therefore, the storage circuit having the configuration shown in FIG. 4A has a ternary value with a circuit configuration of a small number of elements such that one tunnel transistor M-STT of the present invention and one load resistor R are connected in series. A static memory (multi-value storage circuit) capable of storing a state is configured.

The operation of ternary storage was confirmed in a circuit configuration in which the tunnel transistor M-STT and the resistor R according to the third embodiment of the present invention were connected in series as shown in FIG. Note that, of course, the tunnel transistor of the other embodiment shown in FIGS. 1 and 2 can be used as the tunnel transistor M-STT.

Next, a description will be given of a second embodiment of the storage circuit according to the present invention. FIG. 5A is a circuit diagram of a storage circuit according to a second embodiment of the present invention, and FIG. 5B is a voltage-current characteristic diagram thereof. In FIG. 5A, in the storage circuit of this embodiment, the drain or the source of the first tunnel transistor M-STT1 of the present invention is connected to the source of the second tunnel transistor M-STT2 of the present invention. On the other hand, M-STT is connected to the output terminal OUT.
1 is connected to the ground, the gate of the M-STT1 is connected to the input terminal IN, and the gate and the drain of the second tunnel transistor M-STT2 are connected to the power supply voltage Vdd terminal.

That is, in this embodiment, the resistance R in the embodiment of FIG.
-STT2. Thus, when the tunnel transistors of the third embodiment shown in FIG. 3 are used as the tunnel transistors M-STT1 and M-STT2, respectively,
The voltage between the source and the drain current is indicated by T in FIG. 5B, and the load line is indicated by L 'in FIG. 5B, so that the outputs S1, S2 and S
There are three stable points:

Accordingly, the operation in this case is also the same as that shown in FIG.
This is the same as the storage circuit of the first embodiment shown in FIG. The storage circuit of this embodiment can also constitute a static memory (multi-value storage circuit) capable of storing a ternary state with a circuit configuration having a small number of elements, and furthermore, it is not necessary to separately form a resistor. It also has the advantage of being simple.

Actually, the tunnel transistors M-STT1 and M-STT2 according to the third embodiment of the present invention are
When a circuit connected in series as shown in FIG.
Normal ternary storage operation was confirmed. Note that the tunnel transistors of the other embodiments shown in FIGS. 1 and 2 can be used as the tunnel transistors M-STT1 and M-STT2.

The present invention is not limited to the above embodiment. For example, as a semiconductor material constituting a tunnel transistor, other than GaAs, other than Si, Ge,
The present invention can be applied to other semiconductors such as SiGe, InP, InGaAs, and GaSb. Further, the semiconductors of the substrate 1, the sources 2, 21, the drains 3, 31, the channel layer 4, and the connection region 9 may be not only homojunctions made of the same kind of semiconductor but also heterojunctions made of different kinds of semiconductors. Further, although Al _0.5 Ga _0.5 As was used as the insulating layer 5,
Other insulating semiconductors such as GaAs, InAlAs, and InP, and insulators such as SiO ₂ , Si ₃ N ₄ , and AlN may be used.

Although only Al is shown as the gate electrode material, other metals that form a Schottky junction or a low-resistance semiconductor material may be used. Further, in the above embodiment, the conductivity type of the channel layer 4 has been described as n-type. However, the present invention may be applied to the case where the conductivity type of all other regions is opposite to that of the embodiment so that the channel layer 4 becomes p-type. Clearly applicable. Further, although only two connection regions 9 have been described, depending on the number of desired negative resistance characteristics,
Obviously, one or three or more structures may be provided.

The load of the multilevel storage circuit is not limited to the resistor R shown in FIG. 4A and the tunnel transistor M-STT2 of the present invention shown in FIG. It is clear that other elements having non-linear characteristics may be used. Although only an example of a ternary storage circuit is shown here, it is apparent that a storage circuit with four or more values can be configured by changing the number of connection regions of the tunnel transistor of the present invention.

[0065]

As described above, according to the tunnel transistor of the present invention, since a band-to-band tunnel junction is formed between at least a plurality of channel layers and each of the connection regions, a plurality of negative resistance characteristics are obtained. Can continuously be realized.

Further, according to the storage circuit of the present invention, the voltage-
By connecting in series to a resistive load using a first tunnel transistor having a current characteristic having a plurality of negative resistance characteristics,
Since a plurality of stable points exist in the voltage-current characteristics, multi-value storage can be performed by one tunnel transistor, and the information storage density can be improved as compared with the related art.

In the memory circuit of the present invention, when a second tunnel transistor having the same structure as the first tunnel transistor is used as a load instead of a resistive load, it is necessary to separately manufacture a resistive load. Thus, two tunnel transistors can be manufactured by the same manufacturing process without using the same, so that a multi-valued memory circuit whose manufacturing process is simple can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a first embodiment of a tunnel transistor according to the present invention.

FIG. 2 is a schematic sectional view of a second embodiment of a tunnel transistor according to the present invention.

FIG. 3 is a schematic sectional view of a third embodiment of the tunnel transistor according to the present invention.

FIG. 4 is a circuit diagram and a voltage-current characteristic diagram of a first embodiment of the storage circuit according to the present invention.

FIG. 5 is a circuit diagram and a voltage-current characteristic diagram of a storage circuit according to a second embodiment of the present invention.

FIG. 6 is a schematic sectional view of an example of a conventional tunnel transistor.

FIG. 7 is a circuit diagram and a voltage-current characteristic diagram of an example of a conventional memory circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Substrate 2 Source 3 Drain 4 Channel layer 5 Insulating layer 6 Gate electrode 7 Source electrode 8 Drain electrode 9 Connection region 21 Source 31 Drain M-STT, M-STT1, M-STT2 Tunnel transistor R resistance of the present invention

Claims (6)

(57) [Claims] A source and a drain each formed of a semiconductor containing a high concentration of impurities and formed on the substrate at a distance from each other; and a source and a drain formed on the substrate between the source and the drain.
One or more connection regions made of a degenerated semiconductor having a steep impurity distribution containing impurities of the first conductivity type at a high concentration, and a junction between each of the source, one or more connection regions, and the drain. A plurality of channel layers formed on the substrate to induce carriers of a second conductivity type different from the first conductivity type; and an insulating layer formed on the source, drain, connection region, and channel layer. And a source electrode, a drain electrode, and a gate electrode formed on the source, drain, and insulating layers, respectively. 2. The semiconductor device according to claim 1, wherein the source is made of a degenerated semiconductor containing the same impurity of the second conductivity type as the channel layer at a high concentration, and the drain is the same as the first conductivity type of the connection region. 2. The tunnel transistor according to claim 1, comprising a degenerated semiconductor having a high impurity concentration and a steep impurity distribution. 3. The semiconductor device according to claim 1, wherein the source and the drain are made of a degenerated semiconductor having a high impurity concentration of the same first conductivity type as that of the connection region and a steep impurity distribution. The tunnel transistor as described. 4. The tunnel transistor according to claim 1, wherein the source and the drain are each made of a degenerated semiconductor containing the same impurity of the second conductivity type at a high concentration as the channel layer. 5. A first tunnel transistor having a drain electrode or a source electrode connected to an output terminal, a source electrode or a drain electrode connected to a low potential side power supply terminal, and a reset pulse or a write pulse applied to a gate electrode. A resistive load having one end connected to a connection point between the first tunnel transistor and the output terminal and the other end connected to a high-potential-side power supply terminal, wherein the first tunnel transistor is mounted on a substrate; A source and a drain, which are formed separately from each other and are made of a semiconductor containing a high-concentration impurity; and a high-concentration impurity of a first conductivity type formed on the substrate between the source and the drain. One or more connection regions made of a degenerate semiconductor having a steep impurity distribution, and each of the source, one or more connection regions, and a drain A plurality of channel layers formed on the substrate so as to bond between them and inducing carriers of a second conductivity type different from the first conductivity type, and on the source, drain, connection region, and channel layer. An insulating layer formed,
A memory circuit, comprising: a source electrode, a drain electrode, and a gate electrode formed on the source, the drain, and the insulating layer, respectively. 6. A high-potential-side power supply, wherein a second tunnel transistor having the same structure as the first tunnel transistor is used in place of the resistive load, and a gate electrode and a drain electrode of the second tunnel transistor are connected to the high-potential-side power supply. 6. The memory circuit according to claim 5, wherein the storage circuit is connected to a terminal, and a source electrode is connected to a connection point between the first tunnel transistor and the output terminal.