JPH05503609A - Electronic devices, their manufacture and use - Google Patents
Electronic devices, their manufacture and useInfo
- Publication number
- JPH05503609A JPH05503609A JP3505989A JP50598991A JPH05503609A JP H05503609 A JPH05503609 A JP H05503609A JP 3505989 A JP3505989 A JP 3505989A JP 50598991 A JP50598991 A JP 50598991A JP H05503609 A JPH05503609 A JP H05503609A
- Authority
- JP
- Japan
- Prior art keywords
- ferroelectric
- semiconductor
- insulator
- metal
- algaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title description 5
- 239000004065 semiconductor Substances 0.000 claims description 79
- 229910052751 metal Inorganic materials 0.000 claims description 53
- 239000002184 metal Substances 0.000 claims description 53
- 239000012212 insulator Substances 0.000 claims description 49
- 239000000463 material Substances 0.000 claims description 24
- 239000011159 matrix material Substances 0.000 claims description 24
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 23
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 12
- 230000001678 irradiating effect Effects 0.000 claims description 8
- 230000001537 neural effect Effects 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 210000000225 synapse Anatomy 0.000 claims 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 11
- 210000002569 neuron Anatomy 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000010287 polarization Effects 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000002269 spontaneous effect Effects 0.000 description 3
- -1 B aF2 Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000013528 artificial neural network Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- FGIUAXJPYTZDNR-UHFFFAOYSA-N potassium nitrate Chemical compound [K+].[O-][N+]([O-])=O FGIUAXJPYTZDNR-UHFFFAOYSA-N 0.000 description 2
- XPRGFWCOARUGAL-UHFFFAOYSA-N 3-anilino-1-phenylpyrrolidine-2,5-dione Chemical group O=C1N(C=2C=CC=CC=2)C(=O)CC1NC1=CC=CC=C1 XPRGFWCOARUGAL-UHFFFAOYSA-N 0.000 description 1
- 101150114751 SEM1 gene Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004481 Ta2O3 Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 description 1
- 229910001634 calcium fluoride Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005621 ferroelectricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000002222 fluorine compounds Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- PNDPGZBMCMUPRI-UHFFFAOYSA-N iodine Chemical compound II PNDPGZBMCMUPRI-UHFFFAOYSA-N 0.000 description 1
- 235000010333 potassium nitrate Nutrition 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000000946 synaptic effect Effects 0.000 description 1
- 230000005676 thermoelectric effect Effects 0.000 description 1
- 238000001931 thermography Methods 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
- 235000021419 vinegar Nutrition 0.000 description 1
- 239000000052 vinegar Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
- H01L29/803—Programmable transistors, e.g. with charge-trapping quantum well
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
Abstract
(57)【要約】本公報は電子出願前の出願データであるため要約のデータは記録されません。 (57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 電 デバイス それらの製゛法および１用法′本出願は、１９８９年、１２月２ ７日付は出願の国際特許出願出願番号ＰＣＴ／ＵＳ８９１０５８８２の一部継続 出願であり、国際特許出願出願番号ＰＣＴ／ＵＳ８９１０５８８２は、更に１９ ８８年１２月２７日付けの米国特許出願出願番号２９０，４６８の一部継続出願 であり、両出願の主題部分は参考としてここに添付される。[Detailed description of the invention] ELECTRICAL DEVICES THEIR MANUFACTURING METHOD AND 1 USE 'This application was filed on December 2, 1989. 7 is a partial continuation of the international patent application application number PCT/US89105882. The International Patent Application No. PCT/US89105882 is further filed under 19 Continuation-in-part of U.S. Patent Application No. 290,468 dated December 27, 1988 and the subject matter portions of both applications are hereby attached by reference.
皮表Ｕ 本発明は、バイポーラ−型三端子ゲートダイオード、この種のダイオードを用い たメモリーマトリックス、この種のダイオードを含むニューラルシナッブスネッ トワーク、この種のダイオードを含むＤＲＡＭ （ダイナミックランダムアクセ スメモリー）ユニット、バイポーラ−型トランジスター、この種のダイオードを 利用したＪＦＥＴ（接合電界効果トランジスター）、ガリュームひ素（ＧａＡｓ ）およびガリュームひ素アルミニューム（ＡＩＧａＡｓ）異種構造およびこの種 のダイオードの製造法および利用法に関する。Skin surface U The present invention uses a bipolar type three-terminal gate diode, and this type of diode. memory matrices, neural synaptic networks containing diodes of this type. network, DRAM containing this type of diode (dynamic random access memory) units, bipolar transistors, and diodes of this type. JFET (junction field effect transistor), gallium arsenide (GaAs) ) and gallium arsenide aluminum (AIGaAs) heterogeneous structures and this species Concerning the manufacturing and usage of diodes.
■ＩＬ術 先行技術は、ニー、ニス、グローブによる”半導体デバイスの物理と技術” （ 版権１９６７年、ジョンウィリーアンドサン）（”Ｐｈｙｓｉｃｓ ａｎｄ Ｔ ｅｃｈｎｏｌｏｇｙ ｏｆ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ Ｄｅｖｉｃｅｓ” ｂｙ Ａ、Ｓ、Ｇｒｏｖｅ、ｃｏｐｙｒｉｇｈｔ １９６７ ｂｙ Ｊｏｈｎ Ｗｉｌｅｙ ＆５ｏｎｓ、Ｉｎｃ）にて例示されていて、この主題部を参考とし てここに添付している。■IL technique The prior art is "Physics and Technology of Semiconductor Devices" by Nie, Niss, and Grove ( Copyright 1967, John Wiley and Son) ("Physics and T. technology of Sem1 conductor Devices” by A, S, Grove, copyright 1967 by John Wiley & 5ons, Inc.), and refer to this subject section. It is attached here.
先行技術ではないが、関連している技術は、電気電子学会回路とデバイス誌（Ｉ ＥＥＥ ＣＩＲＣＵＩＴＳＡＮＤ ＤＥＶｒＣＥＳ ＭＡＧＡＺＩＮＥ）の１９ ９０年１月号に掲載されているローリン、エッチ、パーカー （Ｌａｕｒｅｅｎ Ｈ，Ｐａｒｋｅｒ）およびアル、エフ、タシュ（Ａｔ Ｆ、Ｔａ５ｃｈ）によ る”６４メガバイトおよび２５６メガバイトＤＲＡＭ用の強誘電体物質” （” Ｆｅｒｒｏｅｌｅｃｔｒｉｃ Ｍａｔｅｒｉａｌｓ Ｆｏｒ ６４Ｍｂ ａｎｄ ２５６Ｍｂ ＤＲＡ Ｍ ｓ”）というタイトルの論文に例示されていて、こ こにその全部を参考として添付する。Related technology, although not prior art, is published in the Institute of Electrical and Electronics Engineers of Japan Journal of Circuits and Devices (IEEJ). EEE CIRCUITSAND DEVrCES MAGAZINE) 19 Laureen, Ecchi, Parker published in the January 1990 issue by H, Parker) and Al, F, Tasch (AtF, Ta5ch). "Ferroelectric materials for 64 MB and 256 MB DRAM" (" Ferroelectric Materials For 64Mb and 256Mb DRAMs”). All of them are attached here for reference.
え匪二】ｊ 本発明にによる第一実施例は、予め設定された第一のタイプの半導体材料を含む 第一の半導体部分を少なくとも含み、かつ、予め設定された第二のタイプの半導 体材料を含む第二の半導体部分を少なくとも含む電子デバイスを提供する。第二 の部分の少なくとも一部は、第一の部分の少なくとも一部と接触している。少な くとも一つの絶縁体部分が、第一の部分の一部および第二の部分の一部と接触し ている。少なくとも一つの金属部分が含まれ、絶縁体部分の少なくとも一部と金 属部分の少なくとも一部との間に少なくともその一部が設けられた少なくとも一 つの強誘電体部分が含まれる。Eiji】j A first embodiment according to the invention comprises a predetermined first type of semiconductor material. a predetermined second type of semiconductor including at least the first semiconductor portion; An electronic device is provided that includes at least a second semiconductor portion that includes a body material. second At least a portion of the portion is in contact with at least a portion of the first portion. little at least one insulator portion is in contact with a portion of the first portion and a portion of the second portion; ing. includes at least one metal part, at least a portion of the insulator part and gold at least one part of which is located between at least part of the generic part; Contains two ferroelectric parts.
第二の実施例は、上述の電子デバイスを提供するが、絶縁体部分、強誘電体部分 、第一金属部分は、少なくとも一つの開口部を有するゲート機構を構成する。開 口部には、少なくとも一つの第二金属部分が設けられ、第二金属部分は、少なく とも絶縁部分の一部と接触している。A second embodiment provides the electronic device described above, but with an insulator part and a ferroelectric part. , the first metal portion constitutes a gate mechanism having at least one opening. Open The mouth portion is provided with at least one second metal portion, and the second metal portion includes at least one second metal portion. Both are in contact with part of the insulating part.
第二の金属部分は、第二の半導体部分の少なくとも一部と接触している。The second metal portion is in contact with at least a portion of the second semiconductor portion.
第三の実施例は、逆バイアスされた複数のバイポーラ−型三端子ゲートダイオー ドを含むメモリーマトリックスを提供し、各ダイオードは、上述の電子デバイス として形成している。A third embodiment includes a plurality of reverse-biased bipolar three-terminal gate diodes. a memory matrix containing a diode, each diode connected to the electronic device described above. It is formed as
他の実施例は、ここで説明の電子デバイスとして形成されているバイポーラ−型 三端子ゲートダイオードの複数を含むニューラルシナッブスネットワークを提供 する。Other embodiments include bipolar devices configured as electronic devices as described herein. Provides a neural synabs network containing multiple three-terminal gated diodes do.
他の実施例は、一つの分極状態から他の分極状態へ強誘電体部分を完全に変換す ることなく、動的記憶のために、強誘電体部分および絶縁体部分またはそのいず れかの高誘電率を用い、また更に、アレーの”パスゲート”としてｐ−ｎ接合を 用いたＤＲＡＭを提供する。Other embodiments include completely converting the ferroelectric portion from one polarization state to another. ferroelectric and/or insulating parts for dynamic storage without Furthermore, using the high dielectric constant of the p-n junction as a “pass gate” in the array We will provide the DRAM used.
他の実施例は、ベース接合、コレクター接合、あるいはエミッター接合のいずれ かとして、ｎｐｎまたはｐｎｐバイポーラ−型トランジスターでの接合部として 用いられた、上述の電子デバイスを含むバイポーラ−型トランジスターを提供す る。Other embodiments include either a base junction, a collector junction, or an emitter junction. As a junction in an npn or pnp bipolar transistor. The present invention provides a bipolar transistor including the above-mentioned electronic device. Ru.
他の実施例は、ＪＦＥＴで強誘電体制御のｐ−ｎ接合でゲートダイオードの調和 を利用した構造を提供する。Another example is the harmonization of gate diodes with ferroelectrically controlled p-n junctions in JFETs. Provides a structure using
他の実施例は、上述の電子デバイスがＧａＡｓおよびＡｌＧａＡｓ異種構造体に てもちいられた構造を提供する。Another embodiment is that the electronic device described above is made of GaAs and AlGaAs heterogeneous structures. Provide a useful structure.
他の実施例は、強誘電体に光を照射することにより指定可能な強誘電体ゲートダ イオードを提供する。Another embodiment is a ferroelectric gate dimmer that can be specified by irradiating the ferroelectric with light. provide an iode.
図１は、第一の実施例による電子デバイスの概略図である。FIG. 1 is a schematic diagram of an electronic device according to a first embodiment.
図２は、第二の実施例による電子デバイスの概略図である。FIG. 2 is a schematic diagram of an electronic device according to a second embodiment.
図３は、図２のデバイスの平面図である。FIG. 3 is a top view of the device of FIG. 2.
図４は、強誘電体ゲートダイオードを表す出願人提案のシンボルである。FIG. 4 is the applicant's proposed symbol representing a ferroelectric gated diode.
図５は、本発明によるニューラルネットワークを示す。FIG. 5 shows a neural network according to the invention.
図６は、図５の点線で囲まれた要素を示すニューロン機構を表す出願人提案のシ ンボルである。FIG. 6 is a diagram of the applicant's proposed neuron mechanism showing the elements enclosed by the dotted line in FIG. It is a symbol.
図７は、本発明によるニューラルシナッブスネットワークを示す。FIG. 7 shows a neural synabs network according to the invention.
図８は、ゲート電圧の関数としての総接合容量をプロットした図である。FIG. 8 is a plot of total junction capacitance as a function of gate voltage.
図９は、ＧａＡ ｓおよびＡｌＧａＡｓ異種構造体に電子デバイスを応用した他 の実施例である。Figure 9 shows the application of electronic devices to GaAs and AlGaAs heterogeneous structures. This is an example.
図１０は、本発明による記憶マトリックスを示す。FIG. 10 shows a storage matrix according to the invention.
図１１は、半導体部分に堀こまれたゲートを有すデバイスを示す。FIG. 11 shows a device with a gate drilled into the semiconductor portion.
ここで説明の電子デバイスは、国際特許出願出願番号ＰＣＴ／ＵＳ ８９１０５ ８８２および米国特許出願出願番号２９０，４６８にて開示されている装置、技 術、および方法を用いて製造可能である。The electronic device described herein bears International Patent Application No. PCT/US 89105. 882 and U.S. Patent Application No. 290,468. It can be manufactured using techniques and methods.
図１は、第一および第二半導体部分２．３を有す電子デバイス１を示す。強誘電 体部分５は、絶縁体部分４および第一金属部分６により挟まれている。必要条件 ではないが、部分４は、Ｓ １ＳＧａＡｓ、またはＩｎＰの半導体上に蒸着 され、再成長したエピタキシャル層となった酸化イットリューム、ＣａＦ２、Ｂ ａＦ２、Ｔａ２Ｏ３，５ｉ０３、Ｓｉ３Ｎ４または他の線形誘電シリコン化合物 により構成されるのが好ましい。部分４は、部分５の材料と同じかまたは異なっ た強誘電体材料を含む。FIG. 1 shows an electronic device 1 with a first and a second semiconductor part 2.3. ferroelectric The body portion 5 is sandwiched between the insulator portion 4 and the first metal portion 6. Requirements However, part 4 is deposited on a S1SGaAs or InP semiconductor. Yttrium oxide, CaF2, B aF2, Ta2O3, 5i03, Si3N4 or other linear dielectric silicon compounds It is preferable that the Part 4 is the same or different material from part 5 Contains ferroelectric materials.
部分４．５および６からなる機構は、部分２および部分３の一部と接触し、部分 ３にまたがる。The mechanism consisting of parts 4.5 and 6 is in contact with parts 2 and part 3, and It spans 3.
第一端子７は、部分２に電気的に接続されている。第二端子ＶＪは、部分３に接 続されている。第三端子ＶＧは、部分６に電気的に接続されている。The first terminal 7 is electrically connected to the portion 2 . The second terminal VJ is connected to part 3. It is continued. The third terminal VG is electrically connected to the portion 6.
部分３は、相対的に高い不純物濃度即ち、ドーピング濃度を有す領域を含む。空 乏領域８は、部分３の周囲に形成される。部分５は、領域８の半導体表面変調即 ち、導電率変調によって領域８の電荷容積と相互作用する。Portion 3 includes a region with a relatively high impurity concentration or doping concentration. Sky A depletion region 8 is formed around the portion 3 . Portion 5 corresponds to the semiconductor surface modulation of region 8. In other words, it interacts with the charge volume of region 8 by conductivity modulation.
ここで強誘電体材料という用語は、ＢａＭｎＦ２、Ｂａ Ｍ ｇ Ｆ ２、その 他の弗化物と、ＫＮＯ３と、ならびに、ＰｂＴｉＯ２、Ｐ ｂｘＺ ｒｙＴ ｉ ０３、Ｐ ｂｘＬ ａｙＺ ｒｚＴｉ０３およびＹ Ｍ ｎ Ｏ３といったＡ ＢＯ３を共通組成物として有す材料とを意味しているが、特にこれらに限定する 訳ではない。ここで、Ｙはいかなる希土類元素でもよい。The term ferroelectric material here refers to BaMnF2, BaMgF2, its Other fluorides, KNO3, and PbTiO2, PbxZryTi A such as 03, P bxL ayZ rzTi03 and Y M n O3 means materials having BO3 as a common composition, but is particularly limited to these It's not a translation. Here, Y may be any rare earth element.
図２および図３は、第一および第二の半導体部分９．１０を有すデバイス１８と して構成する第二の実施例である。ゲート機構１９は、絶縁体部分１１および第 一金属部分１３により挟まれる強誘電体部分１２によって構成されれている。機 構１９は、開口部１５を有す。部分１０は、相対的に高ドーピング濃度の領域を 含み、開口部１５に跨っていて、互いに相対している部分１１を接触させている 。必要条件ではないが、部分１１は、酸化イットリュームで形成されるか、また は、図１で説明されたその他の材料で形成されることが好ましい。2 and 3 show a device 18 having first and second semiconductor portions 9.10. This is a second embodiment configured as follows. The gate mechanism 19 includes the insulator portion 11 and the It is composed of a ferroelectric part 12 sandwiched between two metal parts 13. machine The structure 19 has an opening 15. Portion 10 includes a region of relatively high doping concentration. straddles the opening 15 and brings the opposing parts 11 into contact with each other. . Although not a requirement, portion 11 may be formed of yttrium oxide or is preferably formed of other materials as described in FIG.
第二の金属部分１４は、開口部１５に設けられ、部分１０の一部および部分１１ の一部と接触する。A second metal portion 14 is provided in the opening 15 and includes a portion of portion 10 and portion 11. come into contact with some of the
第一端子１７は、部分９に電気的に接続されている。The first terminal 17 is electrically connected to the portion 9 .
第二端子ＶＪは、部分１４に電気的に接続されている。The second terminal VJ is electrically connected to the portion 14.
第三端子ＶＧは、部分１３に電気的に接続されている。The third terminal VG is electrically connected to the portion 13.
空乏領域１６は、部分９および部分１０の間に形成される。部分１２は、領域１ ６の半導体表面変調即ち、導電率変調によって領域１６の電荷容積と相互作用す る。Depletion region 16 is formed between portion 9 and portion 10 . Part 12 is area 1 6 interacts with the charge volume of region 16 by modulation of the semiconductor surface, i.e. conductivity modulation. Ru.
部分５または部分１２は、領域８または領域１６の延長部のｐｎ接合による漏れ のレベルを安定化し、領域８または領域１６内の熱生成キャリヤーにより発生す る電流の増加を安定化するのに利用される。Portion 5 or portion 12 is leakage due to the pn junction of the extension of region 8 or region 16. to stabilize the level of heat generated by heat-generated carriers in region 8 or region 16 It is used to stabilize the increase in current caused by
本発明はまた、強誘電体部分がゲート領域の空乏層を含む総空乏領域部の強誘電 自発分極電荷変調によるｐｎ接合の容量レベルを安定化するのに利用されるデバ イスを考慮している。The present invention also provides that the ferroelectric portion includes the ferroelectric portion of the total depletion region including the depletion layer of the gate region. A device used to stabilize the capacitance level of a pn junction by spontaneous polarization charge modulation. I'm considering chairs.
本デバイスは、一つの分極状態から他の分極状態へ強誘電体部分を完全に変換す ることなく、動的記憶のために、強誘電体および絶縁体またはそのいずれかの高 誘電率と、および、アレーの“パスゲート“とじてｐｎ接合とを両方またはいず れか一方を使用するようなデバイスのＤＲＡＭアーキテクチャ−に利用すること が可能である。This device completely converts the ferroelectric portion from one polarization state to the other. of ferroelectrics and/or insulators for dynamic memory without The dielectric constant and/or the pn junction through the “pass gate” of the array. For use in DRAM architecture of devices that use one or the other. is possible.
本発明は、また、バイポーラ−型トランジスターを製造するのに利用することも 可能である。デバイスは、ベース接合部、コレクター接合部、またはエミッター 接合部のいずれかとしてｐｎｐまたはｎｐｎバイポーラ−型トランジスターに於 ける接合部として応用可能である。The invention can also be used to manufacture bipolar transistors. It is possible. The device can be a base junction, a collector junction, or an emitter In a pnp or npn bipolar transistor as either a junction It can be applied as a joint for
好適な実施例としては、強誘電体の状態によってトランジスターの利得が制御さ れるベースコレクター接合がある。In a preferred embodiment, the gain of the transistor is controlled by the state of the ferroelectric material. There is a base collector junction.
本発明によるデバイスは、また、新型のＪＦＥＴを構成するのに応用可能である 。デバイスは、ＪＦＥＴとして知られれる構造で強誘電体制御のｐｎ接合として ゲートダイオード調和効果を用い、強誘電体ゲートダイオードはゲート接合であ る。The device according to the invention can also be applied to construct a new type of JFET. . The device is a ferroelectrically controlled p-n junction with a structure known as a JFET. Using the gated diode harmonic effect, the ferroelectric gated diode is Ru.
図４は、本発明による強誘電体ゲートダイオードを表すここで提案のシンボル２ ０を示す。強誘電体部分は、参照番号２１で示される。シンボル２０は、ニュー ラルネットワーク２２の説明で使用される。Figure 4 shows the proposed symbol 2 representing a ferroelectric gated diode according to the invention. Indicates 0. The ferroelectric portion is designated with reference number 21. Symbol 20 is the new used in the description of the physical network 22.
図５は、ニューロン部２３に連結された強誘電体ゲートダイオードまたはシナラ プス荷重２０を含むネットワーク２２を示す。ニューロン部２３は点線で囲まれ ている。FIG. 5 shows a ferroelectric gated diode or synarater connected to the neuron section 23. 2 shows a network 22 including a push load 20. The neuron part 23 is surrounded by a dotted line. ing.
図６は、ネットワーク２２のニューロン部を表すためのシンボル２３を示す。FIG. 6 shows a symbol 23 for representing the neuron part of the network 22. In FIG.
図７は、ニューロン３５．３６．３７および３８へ接続されているＸデコーダー ３１．３２．３３および３４を有すニューラルシナッブスネットワーク３０を示 す。Figure 7 shows the X decoder connected to neurons 35, 36, 37 and 38. 31. 32. Shows a neural synabs network 30 with 33 and 34. vinegar.
ネットワーク３０は、Ｘデコーダーを実質的に横断している、ニューロン４３． ４４．４５および４６へ接続されているＹデコーダー３９．４０．４１および４ ２を含む。ネットワーク３ｏは、内部で接続されている代表的なシナラプス荷重 ４７および４８を有す。Network 30 includes neurons 43 . which substantially traverse the X decoder. Y decoder 39.40.41 and 4 connected to 44.45 and 46 Contains 2. Network 3o is a typical synalapse load connected internally. 47 and 48.
デバイスは、後述の光学的構造を含む、種々の構造にラプスマトリックス”とし て利用可能である。この種のネットワークは、”アナログ値記憶”連想記憶装置 を形成するために演算増幅器、抵抗およびコンデンサーを用いる。強誘電体ゲー トダイオードは本質的には、この種のニューラルネットワークにより処理される プログラムの相互作用の期間中にある値に設定可能である、プログラマブルシナ ッブス荷重である。The device incorporates a lapse matrix into various structures, including the optical structure described below. available. This type of network is an “analog value memory” associative memory device. An operational amplifier, resistor, and capacitor are used to form the . ferroelectric game The diode is essentially processed by this kind of neural network. A programmable scenario that can be set to a value during a program's interaction. This is the load.
本発明は、光学的構造も考慮していて、強誘電体ゲートダイオードが強誘電体に 光を照射することによって指定可能となる。金属ゲートは、薄膜金属フィルムを 使用したり、または、インジューム酸化第一錫透明電極を使用したりする種々の 方法により、透明にする必要がある。The present invention also takes into account the optical structure, in which the ferroelectric gate diode becomes a ferroelectric material. It can be specified by irradiating it with light. metal gate thin metal film various methods using transparent indium tin oxide electrodes Depending on the method, it needs to be transparent.
この構造にて使用する場合、強誘電性を有しかつ熱電効果を有す強誘電体が使用 される。このようなデバイスは、光学読みとり記憶装置、赤外線検出器、光記憶 装置およびマトリックスを用いた熱イメージ形成装置に利用可能である。When used in this structure, a ferroelectric material that has ferroelectricity and thermoelectric effect is used. be done. Such devices include optical read storage devices, infrared detectors, optical storage devices, etc. It can be used in thermal imaging devices using devices and matrices.
図１ないし図４では、強誘電体部分が、ゲート領域の空乏層を含む総空乏領域部 の強誘電自発分極ＰＳ電荷変調によるｐｎ接合の容量レベルを安定化するのに利 用される。1 to 4, the ferroelectric portion is the total depletion region including the depletion layer in the gate region. It is useful for stabilizing the capacitance level of p-n junction by ferroelectric spontaneous polarization PS charge modulation. used.
図８では、横軸がゲート電圧ＶＧを表し、これはＡＰＳＡはゲートの面積であり 、ＣＦは、強誘電ゲート容量である。In Figure 8, the horizontal axis represents the gate voltage VG, which means that APSA is the area of the gate. , CF is the ferroelectric gate capacitance.
図８では、縦軸ＣＪは、総合接合容量またはダイオード容量を表す。横軸ＶＧに 沿った点１は、ＡＰＳＩ／ＣＦＩを、点２はＡ Ｐ’ Ｓ２／ ＣＦ２を、点３ はＡＰＳ３／ＣＦ３を表す。In FIG. 8, the vertical axis CJ represents the total junction capacitance or diode capacitance. On the horizontal axis VG Point 1 along the line is APSI/CFI, point 2 is A P' S2/CF2, point 3 is represents APS3/CF3.
容量は、電圧かまたは、強誘電体の自発分極によって変調される。Capacitance is modulated by voltage or by spontaneous polarization of the ferroelectric.
図９は、高電子移動度トランジスター（ＨＥＭＴ）５０として実現された他の実 施例である。ＨＥＭＴ５０は金属部分５１、強誘電体部分５２、この場合絶縁体 として動作するＡ Ｉ ＧａＡｓ部分５３、ガリュームひ素バファ一層５４、お よびガリュームひ素部分５６を含む。FIG. 9 shows another implementation realized as a high electron mobility transistor (HEMT) 50. This is an example. The HEMT 50 has a metal part 51, a ferroelectric part 52, and in this case an insulator. AI GaAs portion 53, gallium arsenide buffer layer 54, and and a gallium arsenic moiety 56.
部分５５は、二次元電子ガスを表す。Portion 55 represents a two-dimensional electron gas.
図９のデバイスは、ガリュームひ素またはＡＩＧａＡＳ異種構造体に用いられた 場合、高電子移動度トランジスターと知られる構造に於いてガス５５を変調する 。強誘電体ゲートにより、ＨＥ Ｍ Ｔ ５０は、高速記憶装置の記憶素子とな る。The device of Figure 9 was used for gallium arsenide or AIGaAS heterogeneous structures. In this case, the gas 55 is modulated in a structure known as a high electron mobility transistor. . The ferroelectric gate allows the HEMT50 to function as a memory element in high-speed memory devices. Ru.
図１０は、センス増幅器およびＸ出カバファー６２に電気的に接続されている行 デコーダー６１を有す記憶マトリックス６ｏを示す。列デコーダー６３は、セン ス増幅器およびＹ出カバファー６４に電気的に接続されている。アレー内で接続 されているのは、強誘電体ゲートダイオード６７である。FIG. 10 shows the rows electrically connected to the sense amplifier and X-output buffer 62. A storage matrix 6o with a decoder 61 is shown. The column decoder 63 It is electrically connected to the output amplifier and the Y output buffer 64. Connect within an array What is shown is a ferroelectric gate diode 67.
マトリックス６０は、リードイネーブル回路およびライトイネーブル回路６５、 並びにゲート制御回路６６を有す。マトリックスアレーでは、ダイオード６７を 逆バイアスすることが好ましい。The matrix 60 includes a read enable circuit and a write enable circuit 65, It also has a gate control circuit 66. In matrix array, diode 67 is Reverse biasing is preferred.
図１および図２に示されるｎ型およびｐ型頭域は、互いに入れ換えてもよい。The n-type and p-type head regions shown in FIGS. 1 and 2 may be interchanged with each other.
図１１は、図１に類似のデバイスを示すが、ここでは、金属部分、強誘電体部分 、および絶縁体部分を含む強誘電体ゲート機構は第一の半導体部分に埋め込まれ 、第二の半導体部分は、埋め込まれた機構を挟んで互いに反対側に位置する第一 の部分および第二の部分を含む。図１のデバイスのように、第二の半導体部分の 領域（第二半導体の第一部分）は相対的に高いドーピング濃度を有する。FIG. 11 shows a device similar to FIG. 1, but here the metal part, the ferroelectric part , and a ferroelectric gate mechanism including an insulator portion is embedded in the first semiconductor portion. , the second semiconductor portion is located on opposite sides of the embedded feature. and a second part. As in the device of FIG. The region (first part of the second semiconductor) has a relatively high doping concentration.
以上の実施例は、説明の為であり、本発明はこれらに限定されない。The above examples are for illustrative purposes only, and the invention is not limited thereto.
Ｆｉｇ、 １０ 要約書 電荷容積が強誘電体部分（５）によって制御される半導体接合を有すデバイス（ １）。 強誘電体（５）は、ゲート制御ダイオードまたはトランジスターを提供 するために、ｐｎ接合の漏れのレベルを安定化する。バイポーラ−型、三端子、 ゲートダイオードは、記憶マトリックス、ニューラルシナッブスネットワーク、 ＤＲＡＭユニット、バイポーラ−型トランジスター、ＪＦＥＴ、およびガリュー ムひ素およびＡｌＧａＡｓ異種構造に用いられる。Fig, 10 abstract A device ( 1). Ferroelectric (5) provides a gated diode or transistor In order to stabilize the level of pn junction leakage. Bipolar type, three terminals, Gated diodes are memory matrices, neural synabs networks, DRAM unit, bipolar transistor, JFET, and Galyu Used for muarsenic and AlGaAs heterostructures.
補正書の翻訳文提出書 （特許法第１８４条の７第１項） 平成４年８月２５日 １、国際出願の番号 ＰＣＴ／ＵＳ ９１１０１１４６ ２、発明の名称 電子デバイス、それらの製造法 および利用法 ３、特許出願人 住 所 アメリカ合衆国 ８０９００ コロラド、コロラド・スプリングス、マ ーク・ダブリング・プルバード５０５５、スィート １００ 名 称 ジンメトリックス・コーポレーション４、代理人 東京都文京区本郷３丁目３０番９号 〒１１３ 本郷ゼットニスビル２階 電 話 （０３） ３８１４−５９２１ （代表）請求の範囲 １．少なくとも、第一の予め定められたタイプの半導体材料を含む第一の半導体 部分と、 少なくとも、第二の予め定められたタイプの半導体材料を含む第二の半導体部分 と、 前記第二の部分の少なくとも一部は、前記第一の部分の少なくとも一部と接触し ていて、 少なくとも一つの絶縁体部分が、前記第一の部分の一部および前記第二の部分の 一部と接触するように設けられていて、 少なくとも一つの金属部分と、 前記絶縁体部分の少なくとも一部と前記金属部分の少なくとも一部との間に少な くともその一部が設けられた少なくとも一つの強誘電体部分とを含み、前記第二 の部分の少なくとも一部は、前記第一の部分に於いて画定された凹部内に設けら れることで、前記第一の部分と前記第二の部分との間に形成される空乏領域を有 すｐ−ｎ接合が前記第一の部分と前記第二の部分と前記強誘電体部分は、導電率 変調即ち前記領域の半導体表面変調により前記領域の電荷容積と相互作用するこ とを特徴とする電子デバイス。Submission of translation of written amendment (Article 184-7, Paragraph 1 of the Patent Act) August 25, 1992 1. International application number PCT/US 91101146 2. Name of the invention Electronic devices and their manufacturing methods and usage 3. Patent applicant Address: United States of America 80900 Colorado Springs, MA Park Doubling Pullbird 5055, Suite 100 Name: Jinmetrics Corporation 4, Agent 3-30-9 Hongo, Bunkyo-ku, Tokyo 113 Hongo Zettnis Building 2nd floor Telephone: (03) 3814-5921 (Representative) Scope of Claims 1. a first semiconductor comprising at least a first predetermined type of semiconductor material; part and a second semiconductor portion comprising at least a second predetermined type of semiconductor material; and, At least a portion of the second portion is in contact with at least a portion of the first portion. and At least one insulator portion covers a portion of the first portion and a portion of the second portion. It is set up so that it comes into contact with a part of the at least one metal part; There is a small gap between at least a portion of the insulator portion and at least a portion of the metal portion. at least one ferroelectric portion, at least a portion of which is provided; at least a portion of the portion is provided within a recess defined in the first portion. and a depletion region formed between the first portion and the second portion. The first part, the second part and the ferroelectric part have a conductivity of a p-n junction. interaction with the charge volume of said region by modulation, i.e. modulation of the semiconductor surface of said region. An electronic device characterized by.
３、第二の半導体部分の第一および第二の部分を含み、前記第一および前記第二 の部分は、異なったドーピング濃度を有し、それぞれが前記絶縁体部分の異なっ た部分と組合わさるように配置され、前記第二の半導体部分の前記第一の部分は 、相対的により高いドーピング濃度を有し、 前記全ての部分がバイポーラ−型デバイスを構成していることを特徴とする請求 の範囲第１項に記載のデバイス。3. a first and a second portion of a second semiconductor portion; portions have different doping concentrations, each with a different doping concentration of the insulator portion. the first portion of the second semiconductor portion is arranged to be combined with the first portion of the second semiconductor portion; , has a relatively higher doping concentration, A claim characterized in that all the parts constitute a bipolar device. The device according to scope 1.
４、前記デバイスは、逆バイアスのバイポーラ−型、三端子ゲートダイオードで あり、 前記第一の部分に電気的に接続された第一の端子と、前記第二の部分に電気的に 接続された第二の端子と、前記金属部分に電気的に接続された第三の端子とを含 むことを特徴とする請求の範囲第１項に記載のデバイス。4. The device is a reverse-biased bipolar, three-terminal gated diode. can be, a first terminal electrically connected to the first part; and a first terminal electrically connected to the second part. a second terminal electrically connected to the metal part; and a third terminal electrically connected to the metal part. A device according to claim 1, characterized in that the device comprises:
５、第一および第二の金属部分を含み、前記強誘電体部分は、ゲート機構として 、前記絶縁体部分と前記第一金属部分に挟まれて設けられていて、前記ゲート機 構は、自身に中央開口部を有し、前記中央開口部は、前記第一金属部分、前記強 誘電体部分お□よび前記絶縁体部分を貫通して伸びていて、す領域を含み、前記 絶縁体部の互いに相対して配置されている部分と接触するために、前記開口部に 跨っていて、前記第二の金属部分は、前記開口部内に設けられ前記第二の部分の 一部および前記絶縁体部分と接触していることを特徴とする請求の範囲第１項に 記載のデバイス。5. comprising first and second metal parts, said ferroelectric part as a gate mechanism; , provided between the insulator part and the first metal part, and the gate machine The structure has a central opening therein, and the central opening is connected to the first metal part and the strong part. extending through the dielectric portion □ and the insulator portion; into said opening for contacting the parts of the insulator part which are arranged opposite to each other. the second metal portion is disposed within the opening and extends over the second metal portion; Claim 1, characterized in that the part is in contact with the insulator part. Devices listed.
６、前記絶縁体部分はＡｌＧａＡｓを含み、前記デバイスは、ＧａＡｓおよびＡ ｌＧａＡｓの異種構造で使用され、 前記デバイスは、ＨＥＭＴ構成にて前記ＡｌＧａＡｓ構造で二次元ガスを変調す ることを特徴とする請求の範囲第１項に記載のデバイス。6. The insulator portion includes AlGaAs, and the device includes GaAs and AlGaAs. used in heterogeneous structures of lGaAs, The device modulates a two-dimensional gas with the AlGaAs structure in a HEMT configuration. A device according to claim 1, characterized in that:
７、前記部分は、半導体表面電位を一定にすることで前記強誘電体部分を記憶素 子として用いるゲート制御ダイオードを含むように、配置され、動作可能に接続 されていることを特徴とする請求の範囲第１項に記載のデバイ８、前記金属部分 は、透明であり、 前記ダイオードは、前記強誘電体部分に光を照射することで指定可能であること を特徴とする請求の範囲第７項に記載のデバイス。7. The ferroelectric portion is made into a memory element by keeping the semiconductor surface potential constant. arranged and operably connected to include a gated diode used as a gated diode. The device 8 according to claim 1, characterized in that the metal portion is is transparent; The diode can be specified by irradiating the ferroelectric portion with light. 8. A device according to claim 7, characterized in that:
９、複数の逆バイアス、バイポーラ−型、三端子ゲートダイオードを含み、前記 ダイオードの各々が、少なくとも、第一の予め定められたタイプの半導体材料を 含む第一の半導体部分と、 少なくとも、第二の予め定められたタイプの半導体材料を含む第二の半導体部分 と、 前記第二の部分の少なくとも一部は、前記第一の部分の少なくとも一部と接触し ていて、 少なくとも一つの絶縁体部分が、前記第一の部分の一部および前記第二の部分の 一部と接触するように設けられていて、 少なくとも一つの金属部分と、 前記絶縁体部分の少なくとも一部と前記金属部分の少なくとも一部との間に少な くともその一部が設けられた少なくとも一つの強誘電体部分とを含み、前記第二 の部分の少なくとも一部は、前記第一の部分に於いて画定された凹部内に設けら れることで、前記第一の部分と前記第二の部分との間に形成される空乏領域を有 すｐ−ｎ接合が前記第一の部分と前記第二の部分との間に形成され、 前記強誘電体部分は、導電率変調即ち前記領域の半導体表面変調により前記領域 の電荷容積と相互作用することを特徴とする記憶マトリックス。9, including a plurality of reverse-biased, bipolar, three-terminal gated diodes; Each of the diodes comprises at least a first predetermined type of semiconductor material. a first semiconductor portion including; a second semiconductor portion comprising at least a second predetermined type of semiconductor material; and, At least a portion of the second portion is in contact with at least a portion of the first portion. and At least one insulator portion covers a portion of the first portion and a portion of the second portion. It is set up so that it comes into contact with a part of the at least one metal part; There is a small gap between at least a portion of the insulator portion and at least a portion of the metal portion. at least one ferroelectric portion, at least a portion of which is provided; at least a portion of the portion is provided within a recess defined in the first portion. and a depletion region formed between the first portion and the second portion. a p-n junction is formed between the first portion and the second portion; The ferroelectric portion has a conductivity modulation, that is, a semiconductor surface modulation of the region. A memory matrix characterized by interacting with a charge volume of.
１１、第二の半導体部分の第一および第二の部分を含み、前記第一および前記第 二の部分は、異なったドーピング濃度を有し、それぞれが前記絶縁体部分の異な った部分と組合わさるように配置され、前記第二の半導体部分の前記第一の部分 は、相対的により高いドーピング濃度をいることを特徴とする請求の範囲第９項 に記載のマトリックス。11, comprising first and second portions of a second semiconductor portion; The two parts have different doping concentrations, each having a different doping concentration of the insulator part. the first portion of the second semiconductor portion; has a relatively higher doping concentration. Matrix described in.
１２、第一および第二の金属部分を含み、前記強誘電体部分は、ゲート機構とし て、前記絶縁体部分と前記第一金属部分に挟まれて設けられていて、前記ゲート 機構は、自身に中央開口部を有し、前記中央開口部は、前記第一金属部分、前記 強誘電体部分および前記絶縁体部分を貫通して伸びていて、前記第二の部分は、 相対的に高いドーピング濃度を有す領域を含み、前記絶縁体部の互いに相対して 配置されている部分と接触するために、前記開口部に跨っていて、前記第二の金 属部分は、前記開口部内に設けられ前記第二の部分の一部および前記絶縁体部分 と接触していることを特徴とする請求の範囲第９項に記載のマトリックス。12, comprising first and second metal parts, said ferroelectric part serving as a gate mechanism; the gate is provided between the insulator portion and the first metal portion; The mechanism has a central opening therein, said central opening being connected to said first metal part, said extending through the ferroelectric portion and the insulator portion, the second portion comprising: including regions having a relatively high doping concentration, opposite each other of said insulator portions; the second gold plate straddles the opening to contact the disposed portion; The connecting portion is provided within the opening and includes a portion of the second portion and the insulator portion. 10. A matrix according to claim 9, characterized in that it is in contact with.
１３、前記絶縁体部分はＡｌＧａＡｓを含み、前記デバイスは、ＧａＡｓおよび ＡｌＧａＡｓの異種構造で使用され、 前記デバイスは、ＨＥＭＴ構成にて前記ＡｌＧａＡｓ構造で二次元ガスを変調す ることを特徴とする請求の範囲第９項に記載のマトリックス。13. The insulator portion includes AlGaAs, and the device includes GaAs and used in heterogeneous structures of AlGaAs, The device modulates a two-dimensional gas with the AlGaAs structure in a HEMT configuration. 10. The matrix according to claim 9, characterized in that:
１４、前記部分は、半導体表面電位を一定にすることで前記強誘電体部分を記憶 素子として用いるゲート制御ダイオードを含むように、配置され、動作可能に接 続されていることを特徴とする請求の範囲第９項に記載のマトリックス。14. The part stores the ferroelectric part by keeping the semiconductor surface potential constant. arranged and operably connected to include a gated diode used as a device. 10. A matrix as claimed in claim 9, characterized in that the matrix is connected to one another.
１５、前記金属部分は、透明であり、 前記ダイオードは、前記強誘電体部分に光を照射することで指定可能であること を特徴とする請求の範囲第９項に記載のマトリックス。15. The metal part is transparent; The diode can be specified by irradiating the ferroelectric portion with light. 10. A matrix according to claim 9, characterized in that:
１６、アナログ値記憶連想記憶装置を形成するために複数の抵抗、コンデンサー 、演算増幅器、およびプログラマブルシナッブス荷重を含み： 各前記プログラマブルシナッブス荷重は、バイポーラ−型三端子ゲートダイオー ドを含み； 前記ダイオードは、 少なくとも、第一の予め定められたタイプの半導体材料を含む第一の半導体部分 と、 少なくとも、第二の予め定められたタイプの半導体材料を含む第二の半導体部分 と、 前記第二の部分の少なくとも一部は、前記第一の部分の少なくとも一部と接触し ていて、 少なくとも一つの絶縁体部分が、前記第一の部分の一部および前記第二の部分の 一部と接触するように設けられていて、 少なくとも一つの金属部分と、 前記絶縁体部分の少なくとも一部と前記金属部分の少なくとも一部との間に少な くともその一部が設けられた少なくとも一つの強誘電体部分とを含み、 前記第 二のされた凹部内に設けられることで、前記第一の部分と前記第二の部分との間 に形成される空乏領域を有すｐ−ｎ接合が前記第一の部分と前記第二の部分との 間に形成され、 前記強誘電体部分は、導電率変調即ち前記領域の半導体表面変調により前記領域 の電荷容積と相互作用することを特徴とするニューラルシナッブスネットワーク 。16. Multiple resistors and capacitors to form an analog value storage associative memory device Includes , operational amplifiers, and programmable synabs loads: Each programmable synabs load is a bipolar three-terminal gate diode. Including de; The diode is a first semiconductor portion comprising at least a first predetermined type of semiconductor material; and, a second semiconductor portion comprising at least a second predetermined type of semiconductor material; and, At least a portion of the second portion is in contact with at least a portion of the first portion. and At least one insulator portion covers a portion of the first portion and a portion of the second portion. It is set up so that it comes into contact with a part of the at least one metal part; There is a small gap between at least a portion of the insulator portion and at least a portion of the metal portion. at least one ferroelectric portion, at least a portion of which is provided; between the first part and the second part by being provided in the second recessed part; A p-n junction having a depletion region formed between the first portion and the second portion formed between The ferroelectric portion has a conductivity modulation, that is, a semiconductor surface modulation of the region. A neural synabbus network characterized by interacting with the charge volume of .
１８、前記絶縁体部分はＡｌＧａＡｓを含み、前記デバイスは、ＧａＡｓおよび ＡｌＧａＡｓの異種構造体で使用され、 前記デバイスは、ＨＥＭＴ構成にて前記ＡｌＧａＡｓ構造体で二次元ガスを変調 することを特徴とする請求の範囲第１６項に記載のネットワーク。18, the insulator portion includes AlGaAs, and the device includes GaAs and used in AlGaAs heterogeneous structures, The device modulates a two-dimensional gas with the AlGaAs structure in a HEMT configuration. 17. The network according to claim 16, characterized in that:
１９、前記部分は、半導体表面電位を一定にすることで前記強誘電体部分を記憶 素子として用いるゲート制御ダイオードを含むように、配置され、動作可能に接 続されていることを特徴とする請求の範囲第１６項に記載のネットワーク。19. The part stores the ferroelectric part by keeping the semiconductor surface potential constant. arranged and operably connected to include a gated diode used as a device. 17. The network according to claim 16, characterized in that the network is connected to
２０、前記金属部分は、透明であり、 前記ダイオードは、前記強誘電体部分に光を照射することで指定可能であること を特徴とする請求の範囲第１６項に記載のネットワーク。20. The metal part is transparent; The diode can be specified by irradiating the ferroelectric portion with light. 17. The network according to claim 16, characterized in that:
２１、第二の半導体部分の第一および第二の部分を含み、前記第二の半導体部分 の前記第一の部分は、相対的に高いドーピング濃度の領域を含み、 前記金属部分、前記強誘電体部分および前記絶縁体部分より構成される機構は、 前記第一の半導体部分内に堀こまれて設けられ、前記堀こまれて設けられた機構 の両側に実質的に相対して前記第二の半導体部分の前記第一および前記第二の部 分が設けられていることを特徴とする請求の範囲第１項に記載の電子デバイス。21, comprising first and second portions of a second semiconductor portion, said second semiconductor portion; the first portion of includes a region of relatively high doping concentration; The mechanism constituted by the metal part, the ferroelectric part, and the insulator part, a mechanism provided by being dug into the first semiconductor portion; and a mechanism provided by being drilled into the first semiconductor portion. said first and said second portions of said second semiconductor portion substantially opposite opposite sides of said second semiconductor portion; 2. The electronic device according to claim 1, wherein the electronic device is provided with a minute.
２２、第二の半導体部分の第一および第二の部分を含み、前記第二の半導体部分 の前記第一の部分は、相対的に高いドーピング濃度の領域を含み、 前記金属部分、前記強誘電体部分および前記絶縁体部分より構成される機構は、 前記第一の半導体部分内に堀こまれて設けられ、前記堀こまれて設けられた機構 の両側に実質的に相対して前記第二の半導体部分の前記第一および前記第二の部 分が設けられていることを特徴とする請求の範囲第９項に記載の記憶マトリ・ソ クス。22, comprising first and second portions of a second semiconductor portion, said second semiconductor portion; the first portion of includes a region of relatively high doping concentration; The mechanism constituted by the metal part, the ferroelectric part, and the insulator part, a mechanism provided by being dug into the first semiconductor portion; and a mechanism provided by being drilled into the first semiconductor portion. said first and said second portions of said second semiconductor portion substantially opposite opposite sides of said second semiconductor portion; The storage matrix solution according to claim 9, characterized in that Kusu.
２３、第二の半導体部分の第一および第二の部分を含み、前記第二の半導体部分 の前記第一の部分は、相対的に高いドーピング濃度の領域を含み、 前記金属部分、前記強誘電体部分および前記絶縁体部分より構成される機構は、 前記第一の半導体部分内に堀こまれて設けられ、前記堀こまれて設けられた機構 の両側に実質的に相対して前記第二の半導体部分の前記第一および前記第二の部 分が設けられていることを特徴とする請求の範囲第１６項に記載のニューラルシ ナツブスネ国際調査報告23, comprising first and second portions of a second semiconductor portion, said second semiconductor portion; the first portion of includes a region of relatively high doping concentration; The mechanism constituted by the metal part, the ferroelectric part, and the insulator part, a mechanism provided by being dug into the first semiconductor portion; and a mechanism provided by being drilled into the first semiconductor portion. said first and said second portions of said second semiconductor portion substantially opposite opposite sides of said second semiconductor portion; The neural simulation according to claim 16, characterized in that: Natsubune International Investigation Report
Claims (20)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US48427390A | 1990-02-26 | 1990-02-26 | |
| US484,273 | 1990-02-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05503609A true JPH05503609A (en) | 1993-06-10 |
Family
ID=23923463
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3505989A Pending JPH05503609A (en) | 1990-02-26 | 1991-02-22 | Electronic devices, their manufacture and use |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0517842A1 (en) |
| JP (1) | JPH05503609A (en) |
| KR (1) | KR920704360A (en) |
| AU (1) | AU7479291A (en) |
| WO (1) | WO1991013465A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009218438A (en) * | 2008-03-11 | 2009-09-24 | Sony Corp | Solid-state imaging device, its manufacturing method, and electronic device |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3374216B2 (en) * | 1991-10-26 | 2003-02-04 | ローム株式会社 | Semiconductor device having ferroelectric layer |
| EP0568064B1 (en) * | 1992-05-01 | 1999-07-14 | Texas Instruments Incorporated | Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer |
| US5572052A (en) * | 1992-07-24 | 1996-11-05 | Mitsubishi Denki Kabushiki Kaisha | Electronic device using zirconate titanate and barium titanate ferroelectrics in insulating layer |
| US6310373B1 (en) * | 1992-10-23 | 2001-10-30 | Symetrix Corporation | Metal insulator semiconductor structure with polarization-compatible buffer layer |
| US6664115B2 (en) | 1992-10-23 | 2003-12-16 | Symetrix Corporation | Metal insulator structure with polarization-compatible buffer layer |
| US5523964A (en) * | 1994-04-07 | 1996-06-04 | Symetrix Corporation | Ferroelectric non-volatile memory unit |
| KR0141160B1 (en) * | 1995-03-22 | 1998-06-01 | 김광호 | Ferroelectric memory and manufacturing method thereof |
| JP4851740B2 (en) * | 2005-06-30 | 2012-01-11 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| WO2023204767A1 (en) * | 2022-04-20 | 2023-10-26 | National University Of Singapore | Inversion-type ferroelectric capacitive memory |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2695397A (en) * | 1953-06-16 | 1954-11-23 | Bell Telephone Labor Inc | Ferroelectric storage circuits |
| US2791761A (en) * | 1955-02-18 | 1957-05-07 | Bell Telephone Labor Inc | Electrical switching and storage |
| NL202404A (en) * | 1955-02-18 | |||
| US3400383A (en) * | 1964-08-05 | 1968-09-03 | Texas Instruments Inc | Trainable decision system and adaptive memory element |
| US3648258A (en) * | 1969-07-01 | 1972-03-07 | Sperry Rand Corp | Optical memory circuit |
| US3585415A (en) * | 1969-10-06 | 1971-06-15 | Univ California | Stress-strain transducer charge coupled to a piezoelectric material |
| US4161038A (en) * | 1977-09-20 | 1979-07-10 | Westinghouse Electric Corp. | Complementary metal-ferroelectric semiconductor transistor structure and a matrix of such transistor structure for performing a comparison |
| US4482841A (en) * | 1982-03-02 | 1984-11-13 | Texas Instruments Incorporated | Composite dielectrics for low voltage electroluminescent displays |
| NL8500218A (en) * | 1985-01-28 | 1986-08-18 | Philips Nv | SEMICONDUCTOR DEVICE WITH TWO-DIMENSIONAL CARRIER GAS. |
| JPH0715953B2 (en) * | 1985-08-09 | 1995-02-22 | 株式会社リコー | Rewritable memory device and manufacturing method thereof |
-
1991
- 1991-02-22 WO PCT/US1991/001146 patent/WO1991013465A1/en not_active Application Discontinuation
- 1991-02-22 JP JP3505989A patent/JPH05503609A/en active Pending
- 1991-02-22 EP EP91906321A patent/EP0517842A1/en not_active Withdrawn
- 1991-02-22 AU AU74792/91A patent/AU7479291A/en not_active Abandoned
- 1991-02-22 KR KR1019920702049A patent/KR920704360A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009218438A (en) * | 2008-03-11 | 2009-09-24 | Sony Corp | Solid-state imaging device, its manufacturing method, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| AU7479291A (en) | 1991-09-18 |
| EP0517842A1 (en) | 1992-12-16 |
| WO1991013465A1 (en) | 1991-09-05 |
| KR920704360A (en) | 1992-12-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4633438A (en) | Stacked semiconductor memory | |
| JPH05503609A (en) | Electronic devices, their manufacture and use | |
| JPS6167953A (en) | Semiconductor memory device and manufacture thereof | |
| US5712498A (en) | Charge modulation device | |
| US3623030A (en) | Semiconductor-ferroelectric memory device | |
| JPS5846866B2 (en) | dynamic memory cell | |
| US3906544A (en) | Semiconductor imaging detector device | |
| US4079358A (en) | Buried junction MOS memory capacitor target for electron beam addressable memory and method of using same | |
| Okano et al. | Nonvolatile programmable two-terminal diodes using a ferroelectric semiconductor | |
| Metzger | Unimolecular rectifiers and proposed unimolecular amplifier | |
| US3891936A (en) | Low frequency field effect amplifier | |
| Noble et al. | Parasitic leakage in DRAM trench storage capacitor vertical gated diodes | |
| KR900003028B1 (en) | Semiconductor integrated circuit device | |
| US4426655A (en) | Memory cell resistor device | |
| US4432074A (en) | Process for the operation of a CID arrangement | |
| Mantese et al. | Polarization-graded ferroelectrics: The dielectric analogues of semiconductor junctions devices | |
| JP2952828B2 (en) | Semiconductor device and storage element using the same | |
| Levy | Application and integration of quantum effect devices for cellular VLSI | |
| Lewis et al. | Monolithic HgCdTe charge injection devices | |
| Inoue | Memory effect on a Series Connection of a Ferroelectric Capacitor and a pn Diode | |
| JPS5848468A (en) | Semiconductor device | |
| Eugster et al. | Planar field-effect coupled quantum wires | |
| JPS63310167A (en) | Semiconductor device | |
| Ling | The development of a vertically integrated gallium arsenide bipolar/FET (BiFET) DRAM cell | |
| Possin et al. | BEAMOS-A new electron beam digital memory device |