WO1991012665A1 - Circuit de logique a couplage par l'emetteur a entrees a extremite individuelle et differentielle - Google Patents
Circuit de logique a couplage par l'emetteur a entrees a extremite individuelle et differentielle Download PDFInfo
- Publication number
- WO1991012665A1 WO1991012665A1 PCT/US1990/004587 US9004587W WO9112665A1 WO 1991012665 A1 WO1991012665 A1 WO 1991012665A1 US 9004587 W US9004587 W US 9004587W WO 9112665 A1 WO9112665 A1 WO 9112665A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- ended
- input
- differential
- signal
- input means
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
Definitions
- the present invention relates generally to the field of Emitter Coupled Logic (ECL) circuits, and specifically to an ECL circuit accepting single-ended and differential inputs.
- ECL Emitter Coupled Logic
- a basic ECL circuit consists of a differential amplifier.
- the differential amplifier consists of two parallel current paths, each controlled by an input level. Each input level provides a base voltage for a transistor controlling the current path. The digital state of the differential amplifier is determined by which of the two paths pass the most current.
- ECL circuit There are two ways in which an ECL circuit is typically configured. The most common configuration is where one input to the differential amplifier is held constant at a fixed intermediate voltage, thereby allowing the other input to control the state of the differential amplifier (i.e., single-ended operation). In an alternative configuration, each of the complimentary outputs from a previous gate may be connected as complimentary inputs to the differential amplifier (i.e., differential operation).
- the present invention provides an ECL circuit capable of simultaneously responding to single-ended and differential inputs.
- the ECL circuit comprises a single- ended input, a differential input, logic means responsive to the single-ended and differential inputs for determining an output state, and output means for communicating the output state to external devices.
- Each input i.e., the single-ended input and the two complementary portions of the differential input, provides a base voltage for a control transistor.
- the differential input has half the voltage swing of the single-ended input and the high level of the differential input is halfway between the high and low levels of the single-ended input. In this way, an active single-ended input will exert more control over the current paths than the differential input. When the single-ended input is inactive, the differential input will exert control over the current paths.
- Figure 1 is a schematic diagram of a prior art ECL current switch
- Figure 2 is a schematic diagram of an ECL current switch using single-ended and differential signals
- Figure 3 is a waveform diagram showing typical signal voltage levels according to the embodiment shown in Figure 2;
- Figure 4 is a schematic diagram of an ECL circuit capable of supplying the voltage levels of Figure 3.
- FIG. 5 is a schematic diagram of an ECL latch capable of responding simultaneously to single-ended and differential inputs.
- an ECL circuit is controlled by single-ended and differential inputs, each input providing a base voltage for a control transistor in a current switch.
- the inputs are comprised of a single-ended input and the two complementary portions of a differential input.
- the differential input In order to allow the single-ended input to override the differential input when the"single-ended input is active, the differential input has half the voltage swing of the single-ended input and the high level of the differential input is halfway between the high and low levels of the single-ended input. In this way, an active single-ended input will exert control over the current switch.
- FIG 1 is a schematic diagram of a prior art ECL switch 10.
- a logic operation in the ECL switch 10 consists of steering the current through either of two transistors, 14 or 16, to V cc .
- the state of the switch 10 is determined by the resultant voltage drop across resistors 12 or 18.
- the net voltage swing is determined by the values of the resistors 12 and 18 and the magnitude of the current.
- FIG. 2 is a schematic diagram of an ECL current switch 20 according to a preferred embodiment of the present invention.
- a logic operation in the ECL switch 20 consists of steering the current through one of the transistors, 14 or 16, to V cc .
- the SE input is single-ended varying from -1.7 volts to -0.9 volts.
- the +DF and -DF inputs are complementary portions of a differential input varying from -1.7 volts to -1.3 volts.
- Figure 3 is a waveform diagram of the voltage levels of the inputs to the ECL switch 20 of Figure 2. Traces / +SE and '-SE' show that single-ended input SE / has a voltage swing of approximately 0.8 volts ranging from
- FIG. 4 is a schematic diagram of an ECL circuit 34 that provides the voltage levels for differential inputs +DF and -DF.
- the differential input is set at half the voltage swing of the single-ended input and the high level of the differential input is halfway between the high and low levels of the single-ended input.
- Outputs / +DF and -DF / are the complementary portions of a differential input and have a voltage swing of approximately 0.4 volts ranging from -1.3 volts to -1.7 volts.
- the output low voltage is dependent upon the value of the resistors 36 through which the current source must flow.
- the output low voltage level can be selected by choosing appropriate values for the resistors 36.
- the resistors 36 can be selected in many different combinations, each of which yields the correct amount of total resistance between t e base of output transistor 38 or 40 and V cc .
- FIG. 5 is a schematic diagram of an ECL latch 42 according to a preferred embodiment of present invention.
- Transistors 44 and 46 comprise a first differential amplifier, which is cross-coupled through transistors 48 and 50 to form a latch element.
- Transistors 54 and 56 comprise a second differential amplifier, the state of which is controlled by the data input 'D' connected to the base of transistor 56.
- Transistors 58 and 60 form a third differential amplifier, which controls current flow in conductors 62 and 64.
- the third differential amplifier is controlled by a single-ended input / SE and differential inputs / -DF / and / +DF'.
- an ECL circuit which is capable of simultaneously responding to single-ended and differential inputs.
- the ECL circuit comprises a single-ended input, a differential input, logic means responsive to the single-ended and differential inputs for determining a digital output state, and output means for communicating the output state to external devices.
- the single-ended input and the two complementary portions of the differential input each provide a base voltage for a control transistor in a current switch.
- the differential input has half the voltage swing of the single-ended input and the high level of the differential input is halfway between the high and low levels of the single-ended input. In this way, an active single-ended input will exert control over the current switch. When the single-ended input is inactive, the differential input will exert control over the current switch.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
Un circuit ECL (de logique à couplage par l'émetteur) est capable de répondre simultanément à des entrées à extrémité individuelle et différentielle; le circuit ECL comprend une entrée à extrémité individuelle, une entrée différentielle, une logique répondant aux entrées à extrémités individuelle et différentielle afin de déterminer un état de sortie numérique, ainsi qu'une sortie permettant de communiquer l'état de sortie à des dispositifs extérieurs. Chaque entrée, c'est-à-dire, l'entrée à extrémité individuelle ainsi que les deux parties complémentaires de l'entrée différentielle fournissent une tension de base à un transistor de commande. Afin de permettre à l'entrée à extrémité individuelle de prendre la priorité sur l'entrée différentielle, cette dernière présente la moitié de l'excursion des tensions de l'entrée à extrémité individuelle et le niveau élevé de l'entrée différentielle se situe à mi-chemin entre les niveaux élevé et faible de l'entrée à extrémité individuelle. Ainsi, une entrée à extrémité individuelle active est prépondérante dans la régulation des chemins de courant par rapport à l'entrée différentielle. Lorsque l'entrée à extrémité individuelle est inactive, l'entrée différentielle est prépondérante dans la régulation des chemins de courant.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US47758890A | 1990-02-09 | 1990-02-09 | |
US477,588 | 1990-02-09 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1991012665A1 true WO1991012665A1 (fr) | 1991-08-22 |
Family
ID=23896547
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1990/004587 WO1991012665A1 (fr) | 1990-02-09 | 1990-08-14 | Circuit de logique a couplage par l'emetteur a entrees a extremite individuelle et differentielle |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO1991012665A1 (fr) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3953746A (en) * | 1974-07-29 | 1976-04-27 | Honeywell Information Systems, Inc. | Selector latch gate |
EP0167339A2 (fr) * | 1984-06-30 | 1986-01-08 | Sony Corporation | Circuit logique |
EP0341732A2 (fr) * | 1988-05-13 | 1989-11-15 | Fujitsu Limited | Circuit logique |
-
1990
- 1990-08-14 WO PCT/US1990/004587 patent/WO1991012665A1/fr unknown
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3953746A (en) * | 1974-07-29 | 1976-04-27 | Honeywell Information Systems, Inc. | Selector latch gate |
EP0167339A2 (fr) * | 1984-06-30 | 1986-01-08 | Sony Corporation | Circuit logique |
EP0341732A2 (fr) * | 1988-05-13 | 1989-11-15 | Fujitsu Limited | Circuit logique |
Non-Patent Citations (2)
Title |
---|
IBM Technical Disclosure Bulletin, vol. 32, no. 1, June 1989, (New York, US), "Implementation of an over-writing ECL logic", pages 152-153 * |
Radio Fernsehen Elektronik, vol. 26, no. 1, January 1977, M. Auer et al.: "Komplexe ECL-Schalt-kreise", pages 10-24 * |
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