WO1991011826A1 - Structure de transistor a effet de champ de technologie mos a capacitance de grille reduite et methode de fabrication - Google Patents

Structure de transistor a effet de champ de technologie mos a capacitance de grille reduite et methode de fabrication Download PDF

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Publication number
WO1991011826A1
WO1991011826A1 PCT/US1991/000396 US9100396W WO9111826A1 WO 1991011826 A1 WO1991011826 A1 WO 1991011826A1 US 9100396 W US9100396 W US 9100396W WO 9111826 A1 WO9111826 A1 WO 9111826A1
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Prior art keywords
gate
substrate
region
drain
insulation layer
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PCT/US1991/000396
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English (en)
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Fred L. Quigg
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Quigg Fred L
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Application filed by Quigg Fred L filed Critical Quigg Fred L
Priority to EP91904230A priority Critical patent/EP0513185B1/fr
Priority to DE69126521T priority patent/DE69126521T2/de
Priority to KR1019920701848A priority patent/KR100226874B1/ko
Priority to JP03504415A priority patent/JP3092940B2/ja
Priority to CA002073966A priority patent/CA2073966C/fr
Publication of WO1991011826A1 publication Critical patent/WO1991011826A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to metal-oxide- semiconductor field effect transistors (MOSFETs) and, in particular, to an improved structure of a MOSFET having reduced gate capacitance and increased switching speed.
  • MOSFETs metal-oxide- semiconductor field effect transistors
  • Fig. la shows a representative vertical MOSFET with the gate-source parasitic capacitance (C_ q ) and the gate-drain parasitic capacitance (C__) shown. Also shown in Fig. la is the drain-source parasitic capacitance ( C DS>-
  • a positive voltage V_ D is applied to drain terminal 20, while a low voltage (e.g., ground) is applied to source regions 30 and body regions 34.
  • Source regions 30 and body regions 34 which constitute the emitter and base of a parasitic NPN bipolar transistor, are imperfectly shorted together by contacts 36 to prevent these regions from being forward biased.
  • Conductive gate 38 is insulated from source regions 30 and body regions 34 by a - 2 - gate oxide.
  • FIG. lb A basic equivalent circuit for the MOSFET of Fig. la is shown in Fig. lb. As shown in Fig. lb, for the gate 50 to have a voltage V G necessary to fully turn on MOSFET 52, both Cl_ib and Ct.-> n U must be fully charged.
  • Capacitance will be considered herein to approximate zero. Also shown in Fig. lb is input gate current I (__x and current I charging capacitor C-,-. Note that source region 30, Body region 34, and drain 40 form a parasitic
  • a vertical MOSFET such as shown in Fig. la, is typically a polysilicon gate device, where the gate 38 is used as a diffusion mask to self-align source regions 30 and body regions 34.
  • the MOSFET is off, with Vl_ab_ below the threshold voltage VX.
  • Input gate current IG_ is shared between C-, D and C _ according to their capacitance ratio.
  • the threshold voltage V- is reached and the MOSFET begins to turn on, lowering the drain-to-source voltage V . This changing V,..
  • the depletion region under the gate decreases since the potential of drain 40 under gate 38 is lowered due to this region being pulled down by the increasing ohmic channel between N-type source region 30 and N-type drain 40.
  • capacitance C G _ is increasing due to this narrowing of the effective insulation between the plates of the equivalent capacitor C... As this capacitance increases, a decreasing dv/dt of the drain-to-source voltage V, ⁇ results. This increase in capacitance C,, ⁇ is reflected in the curved lower portion of V shown in Fig. 2.
  • dV__ will be a negative value
  • dV-,- will be a negative value
  • (1-A ⁇ ) is equal to (1 + voltage gain) .
  • RF radio frequency
  • the value C GD (1-A ⁇ is at least three times greater than C , and thus any reduction of capacitance C G _ will significantly lower the switching time of the MOSFET, or significantly raise the usable operating frequency.
  • Capacitance is calculated using the equation:
  • C is the capacitance
  • e_ is the permittivity of empty space (8.85 x 10 coul 2/newton2-m2) ;
  • K is the dielectric constant (3.9 for SiO and 11.7 for Si) ;
  • A is the plate area; and t is the dielectric thickness.
  • capacitance may be reduced by decreasing the plate area or increasing the dielectric thickness.
  • the prior art has attempted to reduce the parasitic gate capacitance of a MOSFET by reducing the area of the gate and/or increasing the effective dielectric thickness between the gate and the drain.
  • FIG. 3 Two types of approaches which have been previously used to reduce C are shown in Figs. 3 and 4 where, in Fig. 3, an increased thickness of dielectric 60 is formed over drain 62 to provide an increased dielectric thickness between gate 64 and drain 62.
  • the gate-source capacitance C Gg is essentially unchanged, since the thickness of the dielectric separating gate 64 from source region 66 is assentially unchanged.
  • Prior art Fig. 4 illustrates an approach where an N channel vertical MOSFET uses two separate gates 70 and 72 commonly connected to a gate voltage V-,. Since the effective area of the gate over drain 76 is decreased, the C G-,,D_. is also decreased.
  • gate 64 may be misaligned with respect to raised dielectric portion 60, causing part of the device to have low gain.
  • a center portion of the gate oxide 70 over drain 76 must be masked and protected while body regions 78 and source regions 74 are formed self-aligned with the gate.
  • the width of gate elements 72 is subject to mask and photoresist variations, which cause variations in C across a wafer and from lot to lot.
  • the critical masking steps required to form raised dielectric portion 60 in Fig. 3 and to perform the precise etching of the gate in Fig. 4 require a relatively precise alignment of the mask, or relatively precise process and mask control, thus inevitably resulting in lower yields and variable performance devices.
  • Another drawback to the MOSFET in Fig. 3 is the imperfect short across the emitter-base of the parasitic bipolar transistor. Under certain adverse conditions, the bipolar transistor may be turned on to the extent of causing secondary breakdown and device failure. Manufacturers have addressed this problem by: 1) reducing the depth of the N+ source diffusion to lower beta; 2) moving the P+ body contact region closer to the channel region to reduce resistance between the emitter and base; and 3) reducing the lateral dimension of the N+ source region to lower the resistance between the emitter and base.
  • a vertical MOSFET is formed having a lower gate portion overlying the channel region of the MOSFET and separated from the channel region by a thin gate oxide layer.
  • An upper gate portion is formed overlying the drain of the MOSFET and separated from the drain by a relatively thick self-aligned oxide layer.
  • the MOSFET since the dielectric thickness between the upper gate portion and the drain is relatively large, the MOSFET exhibits a lower gate-drain capacitance (C G_O_) value, while the threshold voltage of the MOSFET remains relatively unchanged.
  • the upper gate portion may be electrically connected to the lower gate portion or may be electrically isolated from the lower gate portion. If the upper gate portion is electrically isolated from the lower gate portion, a separate gate voltage may be connected to the upper gate portion to allow the upper gate portion to either act as a field plate or act to augment the fields generated by the lower gate portion to enhance the current handling capabilities of the MOSFET.
  • a preferred method of forming the resulting MOSFET having this lowered C G _ allows the source and body regions to be precisely aligned with the drain edge of the lower gate portion, and allows an ion implant damaged body contact region to be formed directly under, and self-aligned to, the source region, which ensures the parasitic bipolar transistor remains inoperative.
  • Fig. la illustrates a prior art vertical MOSFET.
  • Fig. lb is a schematic diagram illustrating an equivalent circuit for the MOSFET of Fig. la.
  • Fig. 2 is a graph showing representative gate charge characteristics of a MOSFET.
  • Fig. 3 illustrates a first prior art MOSFET having reduced gate-drain capacitance.
  • Fig. 4 illustrates a second prior art MOSFET having reduced gate-drain capacitance.
  • Fig. 5 illustrates an embodiment of the invention wherein a MOSFET for very high frequency (VHF) operation is made to have a relatively low C Q ⁇ .
  • VHF very high frequency
  • Figs. 6-12 illustrate various process steps used in one embodiment of a method for forming the VHF MOSFET of Fig. 5.
  • Fig. 13 illustrates an alternative embodiment of a MOSFET capable of ultra high frequency (UHF) operation having a low in accordance with the present invention where upper and lower gates are formed.
  • Fig. 14 illustrates the MOSFET of Fig. 13 with an upper gate coupled to source voltage.
  • Fig. 15 illustrates an alternative embodiment of a MOSFET having a low C GD in accordance with the present invention where an upper gate is removed.
  • Fig. 16a illustrates an alternative embodiment of a MOSFET capable of UHF to super high frequency (SHF) operation having a very low C GD in accordance with the present invention where a lower gate and an upper gate terminate over a portion of the channel region.
  • Fig. 16b illustrates with dashed lines the improved gate charge characteristics of the MOSFET of Fig. 16a.
  • Figs. 17 and 18 illustrate process steps used to form the MOSFET of Fig. 16.
  • Fig. 19 illustrates an alternative embodiment of a MOSFET having a very low C__ in accordance with the present invention which utilizes an overhanging upper gate to eliminate etching of a vertical portion of the gate.
  • Fig. 20 illustrates a process step used to form the MOSFET of Fig. 19.
  • Fig. 21 illustrates an alternative embodiment of a MOSFET having a low C in accordance with the present invention which utilizes a split upper gate.
  • Fig. 22 illustrates an alternative embodiment of a MOSFET having a low C- n in accordance with the present invention which utilizes separate gates overlying an oxide layer of a single thickness.
  • Fig. 23 shows a schematic representation of a MOSFET having an upper gate and a lower gate.
  • Fig. 24 illustrates an embodiment of a lateral MOSFET having a low C Gn in accordance with the present invention.
  • Fig. 5 shows an embodiment of the invention capable of VHF operation, where conductive gate 80, formed of either Al, Al containing Si, or Al containing Cu and Si, or any other compatible gate material, is formed over drain 82 with a first thickness of oxide 86 therebetween. In one embodiment, oxide 86 is 10,000 A thick. Gate 80 is also formed over P body regions 88 with a second thickness of oxide 90 therebetween. In one embodiment, oxide 90 is 900 A thick. Also shown in Fig. 5 is N+ source region 92 and P+ body contact region 94, with conductive source contact 96 shorting together N+ source region 92 and P+ body contact region 94. N+ drain contact 95 is shown contacting a bottom surface of drain 82.
  • oxide layer 86 is significantly thicker than oxide layer 90, the capacitance between gate 80 and drain 82 will be relatively low due to this increased dielectric thickness, while the capacitance between gate 80 and source region 92 will not significantly change.
  • the thickness of gate oxide layer 90 is dictated by design considerations to provide a desired threshold voltage V ⁇ and dielectric breakdown voltage.
  • a gate-to- source voltage V__ will cause the field created between gate 80 and N+ source region 92 and between gate 80 and P- body region 88 to invert the channel region within P- body region 88, causing an ohmic channel to be created between N+ source region 92 and N- drain 82.
  • This inversion of P- body region 88 is primarily due to the field created by the portion of gate 80 located above thin oxide layer 90.
  • the portion of gate 80 overlying thick oxide layer 86 has a reduced effect on the conductance of the MOSFET and provides shielding over drain 82.
  • Figs. 6-12 illustrate a method to form the structure of Fig. 5.
  • an epitaxial layer 98 of N-type conductivity, having an impurity concentration of approximately 3 x 10E15 atoms/cm 3 to achieve a breakdown voltage of between 80 to 100 V is deposited on an N+ substrate and has formed over it silicon dioxide layer 100 having a thickness of preferably 10,000 A.
  • Oxide layer 100 would be formed to have a thickness of 7,000 A for embodiments using two metal layers (a gate layer and a source layer) . This two metal layer embodiment is illustrated on the right hand side of Fig. 5.
  • Oxide layer 100 may be formed by wet oxidation at approximately 1,000°C for 3-5 hours. Over oxide layer 100 is then formed silicon nitride layer 102 by a chemical vapor deposition (CVD) process at approximately 790°C to achieve a thickness of approximately 1,000 A.
  • CVD chemical vapor deposition
  • oxide layer 100 and silicon nitride layer 102 are etched by using a conventional positive photoresist, contact masking technique and an anisotropic etch to expose portion 104 of substrate 98.
  • a LamTM dry etcher is used.
  • the exposed portion 104 of substrate 98 is to coincide with the desired location of the body-source diffusion.
  • boron is implanted into substrate 98 through exposed portion 104 and diffused to form P body region 106.
  • boron ions are implanted at an energy of 70KeV with a dosage of
  • the implanted ions are diffused by a ramp up and dwell diffusing process, where the temperature of the wafer is ramped from 900°C to 1,100°C at a rate of approximately 8°C/minute and held for approximately 2.5 hours and then ramped down to 900°C for one hour (including ramping time) in an N atmosphere, to form P body region 106 having a depth of approximately two microns.
  • the required characteristics of P body region 106 will depend on the desired breakdown voltage of the device and will be readily apparent to one of ordinary skill in the art.
  • an additional boron implant is conducted to form P+ contact region 108 within P body region 106.
  • boron ions are implanted at an energy of approximately lOOKeV with a dosage of 10E15 to 10E16/cm 2.
  • the implant energy is calculated to form P+ region 108 at a depth below the surface of substrate 98 where it is desired to have P+ region 108 interface with a subsequently formed source region.
  • the wafer is dipped in a 10:1, H 0:HF solution for approximately 45 seconds to remove oxide layer 107, and arsenic is implanted to form N+ source region 110 at the surface of substrate 98.
  • arsenic ions are implanted at an energy of approximately 40KeV with a dosage of 10E16/cm .
  • silicon dioxide layer 112 is deposited at 400°C over the surface of the wafer to a thickness of approximately 500 A to prevent any out- diffusing of arsenic ions forming source region 110.
  • the impurities within N+ source region 110 and P+ body contact region 108 are then driven-in for approximately 30 minutes at approximately 1,000°C so that N+ source region 110 extends approximately 0.3 microns beneath the surface of substrate 98. During this drive-in period, P+ body contact region 108 and P body region 106 also diffuse.
  • an oxide etchant is used to remove oxide layer 112 and a portion of oxide layer 100 so as to leave overhanging silicon nitride portion 114.
  • the wafer is immersed in any oxide etch solution with a known and controlled etch rate.
  • any oxide etch solution with a known and controlled etch rate.
  • H_0 to one part ammonium fluoride may be used at 25°C for a period calculated to create the desired overhanging of nitride portion 114 relative to P body 106.
  • a 1.4 micron overhang of nitride portion 114 is satisfactory.
  • the wafer is immersed in hot phosphoric acid (or an equivalent thereof) at a temperature of approximately 160°C for one hour to remove silicon nitride portion 114 and the remainder of silicon nitride layer 102 over oxide layer 100.
  • the wafer is gradually ramped up to a temperature of 920° in a tube furnace for approximately 15 minutes in a dry 0, atmosphere to form a thin layer of oxide 50-100 A thick.
  • Silicon dioxide layer 116 is then grown over the surface of the wafer at approximately 920°C for approximately 25 minutes in an atmosphere of wet 0_ to a thickness of 2500-3000 A over N+ source region 110.
  • An increased thickness of oxide layer 116 is inherently formed over N+ source region 110.
  • the portion of oxide layer 116 over P body region 106, forming the gate oxide, will be approximately 900 A at this stage.
  • a portion of oxide layer 116 over source region 110 is etched to expose a portion of source region 110.
  • an additional etch is conducted to etch source region 110 through to expose P+ body contact region 108.
  • a conductive metal layer is then formed over the surface of the wafer by the deposition of either Al, Al containing Si, Al containing Cu and Si, or any other conventional metal layer to a thickness of approximately one micron.
  • aluminum, copper, and silicon are sputtered over the surface of the wafer.
  • a metal layer containing Si is preferred to minimize migration of the metal atoms into the silicon substrate.
  • metal source contact 96 preferably comprises a WTi barrier layer in contact with the source region overlaid by approximately 1 micron of Au.
  • Source contact 96 contacts N+ source region 92 and also contacts P+ contact region 94 through N+ source region 92, due to source region 92 and P+ contact region 94 being so highly doped as to be in ohmic contact with each other. Ohmic contact is further enhanced by implant damage to the crystalline substrate.
  • source region 92 is anisotropically etched completely through in the contact area so that source contact 96 directly contacts both P+ body contact region 94 and N+ source region 92. Any embodiment herein may be formed with a tungsten (W) or refractory metal silicide layer deposited prior to the formation of source contact 96 to prevent migration of atoms and/or to reduce contact resistance.
  • W tungsten
  • refractory metal silicide layer deposited prior to the formation of source contact 96 to prevent migration of atoms and/or to reduce contact resistance.
  • source contact 96 it is desirable to form source contact 96 close to the channel region to minimize on- resistance.
  • the method described in Figs. 6-12 and Fig. 5 forms a MOSFET having a low gate-drain capacitance C G__D, wherein source region 92, body contact region 94, and body region 88 are formed self-aligned with the drain edge portion of gate 80.
  • this method to form a VHF MOSFET there are no critical alignment tolerances, which makes this above described process one that will inherently result in a high yield of MOSFETs on a wafer.
  • the portion of gate 80 formed over thick oxide portion 86 is connected to the portion of gate 80 formed over thin oxide portion 90 by a vertical gate portion.
  • the metal layer is formed by a method which will intentionally provide poor step coverage, such as by an evaporation process, so that the vertical portion of gate 80 will be relatively thin compared to the horizontal portions of gate 80.
  • Such a resulting structure, having relatively thin vertical portions of gate 80 is then isotropically etched using a commercially available wet aluminum etch containing phosphoric acid, assuming gate 80 is composed of Al, so as to isolate the portion of gate 80 formed above thick oxide portion 86 from the portion of gate 80 formed above thin oxide portion 90.
  • This embodiment is shown in Fig. 13, where upper gate 120 and lower gates 124 result.
  • the remaining elements in the MOSFET of Fig. 13 are similar to those in Fig. 5 and are formed using a process similar to that described with respect to Fig. 5.
  • the source contact is preferably an overlay metal (such as shown on the right hand side of Fig. 5) .
  • This allows P body region 88 to be relatively narrow ( ⁇ 10 microns) for low drain-to-source capacitance C DS -
  • the various figures do not incorporate a two metal layer for simplicity.
  • gate voltage is applied to lower gates 124, while a separate voltage is applied to upper gate 120.
  • a positive voltage applied to upper gate 120 will make upper gate 120 effective in creating additional carriers in the N- drain 82 and increasing the current handling capability of the MOSFET.
  • a negative voltage on upper gate 120 will increase the breakdown voltage of the MOSFET.
  • Fig. 14 a structure identical to Fig. 13 is shown except that upper gate 120 is connected to the source voltage instead of to an upper gate voltage.
  • upper gate 120 acts as a field plate for increasing the depletion region in drain 82 when the MOSFET is in its off state. This serves to enhance the breakdown voltage of the MOSFET.
  • upper metal gate 120 of Fig. 13 is removed using a wet etch process.
  • mask 125 shown in dashed outline, is first formed to expose a center portion of the gate metal over oxide 86. The wet etch process removes the exposed metal and also removes the gate metal adjacent the exposed portion. Gate voltage is applied to gates 124 to invert the channel regions in P body regions 88.
  • lower gate 140 is formed so as to only overlap a portion of the channel region in P body region 88, while upper gate 144 overlaps the remaining portion of the channel region in P body region 88. This configuration further reduces the C G..D. of the
  • Fig. 16a The structure of Fig. 16a is formed using a method similar to that described with respect to Fig. 5, except that after drive-in of N+ source region 92 and P+ contact region 94, the oxide etch, previously discussed with respect to Fig. 11, is conducted for less time so as to etch away less of oxide layer 100 under silicon nitride layer 102. This is shown in Fig. 17.
  • the terminating portion of oxide layer 100 is located above an exposed portion of P body region 88 where it is desired for lower gate 140 and upper gate 144 to interface. Lateral dimensions of one embodiment are shown in Fig. 17.
  • silicon nitride layer 102 is removed, and oxide layer 116 is grown. 5 As shown in Fig. 16a, oxide 116 is etched, and source region 92 and body contact region 94 are optionally etched in order to short these regions together by a metal source contact. A metal conductive layer is then deposited, preferably by evaporation, so as to provide a
  • Source contact 148 may also be formed later through an opening in a subsequently deposited oxide layer
  • Fig. 19 illustrates another embodiment of the invention which is a variation of the structure of Fig.
  • the structure may be formed without any requirement for an isotropic etch to etch away a vertical portion of the metal layer initially connecting upper gate 144 to lower gate 140.
  • nitride layer 102 is partially etched to 40-50% of its original thickness. This completely removes overhanging nitride portion 114.
  • the sidewalls of oxide portion 100, shown in Fig. 20, is then re-etched 1,000-2,000 A to create a new small overhanging nitride portion 114A.
  • a metal layer is then deposited by, for example, evaporation, and a vertical portion is not formed on a sidewall of oxide layer 100.
  • the resulting structure is masked and etched to form the structure of Fig. 19. Fig.
  • FIG. 21 shows a higher frequency embodiment of the invention which is a variation of the MOSFETs having a separate upper gate.
  • upper gates 160 and 162 are shown separated by a gap. This structure results in a lower drain-to-upper gate capacitance C Cons due to less upper gate area over drain 82. High current capability is retained by the field created by upper gates 160 and 162.
  • This split upper gate configuration may be used in any of the above-described embodiments including Fig. 5, where gate 80 overlying oxide 86 may be opened up to further reduce C__.
  • source contact 96 is preferably comprised of a 2,000 A WTi barrier layer under a 9,000 A Au layer in an overlay (two layer metal) configuration.
  • a metal source contact is to directly contact both the P+ body contact region and the N+ source region, as shown in Fig. 19, platinum silicide is preferably used as a contact layer under the WTi to improve ohmic contact.
  • the starting material is an N+ (antimony) ⁇ l-0-0> silicon substrate with an 8 micron epitaxial layer formed therein having a resistivity of 1.5 ⁇ cm.
  • Oxide layer 86 has a thickness of 7,000 A.
  • Gate oxide 90 has a thickness of 800 A.
  • the body opening mask through which body region 88 impurities are implanted is 8.5 microns wide.
  • the space between gates 124 is approximately 25 microns.
  • the source contact mask opening is 2 microns.
  • the gate 124, 160, 162 length is approximately 2.5 microns.
  • the implant doses are as follows: For P body region 88: 5 x 10E13/cm 2 at 70KeV using boron ions; For P ⁇ ++ bbooddyy ccoonnttaacctt rreegion 94: 1 x 10E15/cm 2 at
  • the resulting structure has the following electrical properties:
  • a Faraday shield is preferably connected to the source contact and placed between the gate bonding pad and the drain to prevent pad capacitance from becoming part of C .
  • the upper gate described with respect to Figs. 13, 14, 16a, 19, and 21 is deposited on the same thickness of oxide as the lower gate and separated from the lower gate by a masking and etch process.
  • a representative embodiment is shown in Fig. 22, where gates 152 and 154 are formed over a same thickness of oxide 156. Further, both gates 152 arid 154 may or may not overlie a portion of the channel region.
  • the remaining elements in Fig. 22 are identical to those shown in Fig. 5.
  • Fig. 23 shows a new schematic representation of the resulting structures described herein which utilize a separate upper gate and lower gate.
  • Fig. 24 shows a lateral MOSFET in accordance with another embodiment of the invention, where gate portion 160 is formed over thick oxide 86, and gate portion 162 is formed over thin oxide 90. Gate portions 160 and 162 may be separated as described with respect to Fig. 13.
  • the MOSFET of Fig. 24 is formed using steps similar to those used to form the vertical MOSFET of Fig. 5, except, in Fig. 23, N+ drain contact region 168 is formed in a top surface of substrate 82.
  • Substrate 82 may be of an N or P type. If substrate 82 is of a P type, P body region 88 may be deleted.

Abstract

Selon une réalisation, on obtient une structure verticale de transistor à effet de champ de technologie MOS (MOSFET) possédant une partie inférieure de grille (124) recouvrant la partie du canal du MOSFET séparée de celui-ci par une mince couche d'oxyde de grille (90). On réalise une partie supérieure de grille (120) recouvrant le drain du MOSFET et séparée de celui-ci par une couche d'oxyde (86) relativement épaisse. Selon cette réalisation particulière, bien que l'épaisseur du diélectrique entre la partie supérieure de grille (120) et le drain (82) soit relativement forte, le MOSFET présente une valeur de capacitance grille-drain (CGD) réduite, tandis que la tension de seuil du MOSFET reste pratiquement inchangée. La partie supérieure de grille (120) peut être reliée électriquement à la partie inférieure de grille (124) ou peut en être électriquement isolée. Une méthode de réalisation préférée du MOSFET résultant possédant cette CGD réduite permet l'alignement précis de la source (92) et des régions du corps (88) avec le bord du drain de la partie inférieure de grille (124).
PCT/US1991/000396 1990-02-01 1991-01-22 Structure de transistor a effet de champ de technologie mos a capacitance de grille reduite et methode de fabrication WO1991011826A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP91904230A EP0513185B1 (fr) 1990-02-01 1991-01-22 Structure de transistor a effet de champ de technologie mos a capacitance de grille reduite et methode de fabrication
DE69126521T DE69126521T2 (de) 1990-02-01 1991-01-22 Mosfet-struktur mit verminderter steuerelektrodenkapazität und herstellungsverfahren
KR1019920701848A KR100226874B1 (ko) 1990-02-01 1991-01-22 감소된 게이트 용량을 갖는 mosfet구조체 및 그 형성방법
JP03504415A JP3092940B2 (ja) 1990-02-01 1991-01-22 減少させたゲート容量を有するｍｏｓｆｅｔ構成体及びその製造方法
CA002073966A CA2073966C (fr) 1990-02-01 1991-01-22 Mosfet a capacitance de grille reduite; methode de fabrication

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US47350490A 1990-02-01 1990-02-01
US473,504 1990-02-01

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JP (1) JP3092940B2 (fr)
KR (1) KR100226874B1 (fr)
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AU (1) AU640993B2 (fr)
CA (1) CA2073966C (fr)
DE (1) DE69126521T2 (fr)
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EP0586835A1 (fr) * 1992-09-11 1994-03-16 Motorola, Inc. Dispositif DMOS à grande vitesse avec une basse capacité de grille/drain
US6093588A (en) * 1995-02-21 2000-07-25 Stmicroelectronics, S.R.L. Process for fabricating a high voltage MOSFET
WO2004066395A3 (fr) * 2003-01-21 2004-09-02 Univ Northwest Dispositif semi-conducteur a grille isolee a puissance de commutation rapide
US6825536B2 (en) * 2001-10-29 2004-11-30 Power Integrations, Inc. Lateral power MOSFET for high switching speeds
DE19905421B4 (de) * 1999-02-10 2005-07-28 Semikron Elektronik Gmbh Leistungshalbleiterbauelement mit reduzierter Millerkapazität
US9508846B2 (en) 2014-04-18 2016-11-29 Stmicroelectronics S.R.L. Vertical MOS semiconductor device for high-frequency applications, and related manufacturing process
CN108565289A (zh) * 2018-06-26 2018-09-21 南京方旭智芯微电子科技有限公司 超结场效应管及超结场效应管的制造方法

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WO1994019830A1 (fr) * 1993-02-23 1994-09-01 Thunderbird Technologies, Inc. Transistor a effet de champ a seuil de fermi, a courant de saturation eleve et a courant de fuite faible
US6150675A (en) * 1996-07-16 2000-11-21 Siemens Aktiengesellschaft Semiconductor component with a control electrode for modulating the conductivity of a channel area by means of a magnetoresistor structure

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US4290077A (en) * 1979-05-30 1981-09-15 Xerox Corporation High voltage MOSFET with inter-device isolation structure
US4455565A (en) * 1980-02-22 1984-06-19 Rca Corporation Vertical MOSFET with an aligned gate electrode and aligned drain shield electrode
JPS58153368A (ja) * 1982-03-09 1983-09-12 Toshiba Corp 絶縁ゲ−ト型電界効果トランジスタ
US4969020A (en) * 1985-02-26 1990-11-06 Nissan Motor Company Limited Semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0586835A1 (fr) * 1992-09-11 1994-03-16 Motorola, Inc. Dispositif DMOS à grande vitesse avec une basse capacité de grille/drain
US6093588A (en) * 1995-02-21 2000-07-25 Stmicroelectronics, S.R.L. Process for fabricating a high voltage MOSFET
DE19905421B4 (de) * 1999-02-10 2005-07-28 Semikron Elektronik Gmbh Leistungshalbleiterbauelement mit reduzierter Millerkapazität
US6825536B2 (en) * 2001-10-29 2004-11-30 Power Integrations, Inc. Lateral power MOSFET for high switching speeds
WO2004066395A3 (fr) * 2003-01-21 2004-09-02 Univ Northwest Dispositif semi-conducteur a grille isolee a puissance de commutation rapide
US8063426B2 (en) 2003-01-21 2011-11-22 North-West University Fast switching power insulated gate semiconductor device
US9508846B2 (en) 2014-04-18 2016-11-29 Stmicroelectronics S.R.L. Vertical MOS semiconductor device for high-frequency applications, and related manufacturing process
CN108565289A (zh) * 2018-06-26 2018-09-21 南京方旭智芯微电子科技有限公司 超结场效应管及超结场效应管的制造方法

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JPH05507385A (ja) 1993-10-21
ATE154469T1 (de) 1997-06-15
AU640993B2 (en) 1993-09-09
AU7252791A (en) 1991-08-21
JP3092940B2 (ja) 2000-09-25
EP0513185A4 (en) 1993-05-05
KR100226874B1 (ko) 1999-10-15
DE69126521D1 (de) 1997-07-17
CA2073966A1 (fr) 1991-08-02
DE69126521T2 (de) 1997-09-25
SG48388A1 (en) 1998-04-17
CA2073966C (fr) 2001-05-08
EP0513185A1 (fr) 1992-11-19
EP0513185B1 (fr) 1997-06-11

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