WO1990016084A1

WO1990016084A1 - An improved programmable semi-conductor resistive element

Info

Publication number: WO1990016084A1
Application number: PCT/US1990/002630
Authority: WO
Inventors: John Millard Caywood
Original assignee: Xicor, Inc.
Priority date: 1989-06-20
Filing date: 1990-05-10
Publication date: 1990-12-27
Also published as: EP0478573A1; EP0478573A4

Abstract

A programmable integrated circuit resistive element (10) having a linear voltage-current curve is disclosed. The element is constructed from an EEPROM cell. Linearity is achieved by adjusting the floating gate to substrate capacitance (Cs) relative to the total floating gate capacitance (Cs+Cp+Ce).

Description

AN IMPROVED PROGRAMMABLE SEMI-CONDUCTOR RESISTIVE ELEMENT

FIELD OF THE INVENTION

The present invention relates to variable impedance elements and, more particularly, to a programmable semi-conductor resistive resistance element,

BACKGROUND OF THE INVENTION

Although there have been very impressive improvements made in recent years in the speed of Von Neuman computers, there is a practical speed limit for such machines. As a result, there has been increasing interest in parallel processing systems. One type of parallel processing system receiving increased attention is referred to as a neuro-networ since it resembles the type of networks found in biological systems.

Neuro-networks are constructed from processing elements referred to as neurons. Each neuron includes a number of inputs and a single output. For any given set of inputs, the output is generated by calculating a weighted sum of the inputs and then transforming that sum using a nonlinear function. The weighted sum in question is typically generated by connecting each of the inputs to an operational amplifier via a resistor. Each resistance is inversely related to the weight factor for the input to which it is connected.

A typical neuro-network consists of one or more layers of neurons. The inputs to the neurons in the first layer are connected to the inputs of the neuro- -2-

network. The outputs of each layer form the inputs to the next layer. The outputs of the last layer form the processor outputs.

Consider a neuro-network processor for performing optical pattern recognition. In such problems, printed characters scanned by a camera are to be translated into the corresponding ASCII code. Each character is mapped onto an nxm array of pixels. Each pixel forms one input of the neuro-network. The number of pixels is typically in the hundreds. The number of neurons in the first layer is likewise in the hundreds. Since each neuron in the first layer must be connected to each of the inputs by a resistor, the number of resistors in the first layer is in the tens of thousands.

The resistance value of each of the resistors is determined by adjusting the resistors to minimize the error in the observed neuro-network output when known patterns are inputted thereto. Algorithms for calculating the values of these resistors are known to the computer arts. These calculations require an iterative processes which may be modeled on conventional digital computers.

A practical neuro-network must be constructed from at most a few standardized parts having resistance values which may be programmed after the part has been fabricated. In principle, one could construct a neuro- network optimized for each computing task. In this case, the above described resistance values would be calculated and a custom integrated circuit designed. Each resistor would be fabricated with its precise resistance value. Unfortunately, the cost of manufacturing a customized integrated circuit for each application is prohibitive in many potential applications of neuro-networks. The total market for pattern recognition computers of any given type is often too small to permit the necessary economies of scale.

In addition, there are applications in which the values of the resistors must be changed after the neuro-network has been assembled. For example, a neuro-network designed to recognize one set of patterns may need to be reprogrammed when a new pattern is encountered.

In addition, it may be advantageous to calculate the resistance values using the neuro-network itself. The calculation of the resistance values is a time consuming iterative process which would benefit greatly from parallel processing. If the resistance values could be updated with sufficient speed, the correct values could be determined using the actual neuro-networ .

Such a self-programming neuro-network would also have the advantageous of compensating for inhomgenities in the components of the neuro-network. As noted above, a large neuro-network has hundreds of amplifiers for performing the summing operations. Each amplifier is connected to a non-linear transform circuit for transforming the weighted sum of the inputs into the neuron output. In any large scale integrated circuit, the performances of the amplifiers and trans¬ form circuits will be different in different portions of the chip. Hence, the values of the resistors calculated on the assumption that all amplifiers and transform circuits behave identically may be in error. If the actual amplifiers and transform circuits are used to determine the resistance values, such errors may be avoided. Further, since greater variation in the amplifiers and other circuits can be tolerated, a higher production yield would be obtained from the integrated circuit fabrication line.

The prior art methods for providing programmable resistors have been economically prohibitive. For example, one method of constructing a variable resistor is to combine the resistances of a number of fixed resistors. For example, a number of resistors can be included in a circuit with gates such that selected resistors are connected to form a resistor in the neuro-network. Each gate is operated by one bit of a storage register. The resistance value is programmed by storing a binary number in the storage register. The storage register can be constructed from EEPROM cells to guarantee that the resistance values do not change when power is lost. In such a scheme, a single neuro-network resistor having a resistance value that can be set to one part in 100 would require a minimum of seven fixed resistors, seven gates, and seven EEPROM cells. As pointed out above, a practical neuro-network requires tens of thousands of such resistors. Hence, a programmable neuro-network would require millions of fixed resistors and EEPROM cells. The silicon area needed to provide an integrated circuit with this number of elements is too large to be practical.

Broadly, it is an object of the present invention to provide an improved resistance element for use in neuro-networks.

It is a further object of the present invention to provide a resistance element which may be programmed.

It is yet another object of the present invention to provide a resistance element that requires less silicon area to construct that prior art resistance elements.

It is a still further object of the present invention to provide a non-volatile resistance element.

These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.

SUMMARY OF THE INVENTION

The present invention comprises a resistive element which comprises a portion of an integrated circuit. The resistive element includes a substrate of semiconductive material having drain and source regions therein, a channel region disposed between said source and drain regions, and a floating gate electrode overlying a portion of said channel region. The floating gate electrode is capacitively coupled to the channel region and to the integrated circuit, the capacitance of these couplings being C_s and C_τ, respectively. C_s and C_τ are chosen such that C_s/C_τ is between 0.3 and 0.7.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a cross-sectional view the preferred embodiment of a resistive element according to the present invention. Figure 2 is a top view the preferred embodiment of a resistive element according to the present invention.

Figure 3 is a schematic drawing of a circuit which is electrically equivalent to the preferred embodiment of a resistive element according to the present invention.

Figure 4 is a schematic drawing of a simple neuro-network utilizing the present invention.

Figure 5 illustrates the a transformation function of the type commonly utilized in neuro- networks.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A resistance element according to the present invention is structurally similar to a conventional eeprom cell. A resistance element according to the present invention is illustrated in Figures 1-3 at 10. Figure 1 is a cross-sectional view of resistance element 10. Figure 2 is a top view of resistance element 10, and Figure 3 is a circuit which is electrically equivalent to resistance element 10.

Resistance element 10 is fabricated on a substrate 12 of a first conductivity type into which three substrate regions 20, 22, and 36, of the opposite conductivity type are formed by appropriate ion implantation or diffusion. The substrate regions are disposed in surface 23.

Resistance element 10 also includes three electrically isolated conducting layers 14, 16, and 18. These conducting layers are preferably constructed from polysilicon. Layer 16 has a first portion 24 which is capacitively coupled to conducting layer 14. These is also capacitive coupling between the conducting layer 16 and the channel region of the MOS transistor formed by the overlay of the conducting layer 16 and the thin oxide region which defines the location of the channel. The capacitive coupling between layer 16 and the channel region is represented by capacitor C_g shown in Figure 3. The overlap region between portion 26 of layer 16 and layer 14 is represented in Figure 3 by tunneling region 28.

Capacitor C_s could be formed entirely from the capacitance which occurs naturally between the gate and channel of an enhancement type MOS transistor. However, the value of such capacitors varies greatly depending upon the relative values of the gate and drain potentials. This leads to a resistive element whose current conduction may vary in a nonlinear manner with drain voltage depending on the value of the gate potential. To avoid this complication, the preferred embodiment of the present invention employs a depletion implanted region 22 which has a constant capacitive coupling to conducting layer 16. This constant capacitance value may be chosen to linearize the current response of resistive element 10.

Layer 18 has a first portion 30 extending between substrate regions 20 and 22 and spaced from surface 23. Layer 18 also includes a second portion 32 which is capacitively coupled to layer 16. This capacitive coupling is represented in Figure 3 by tunneling capacitor region 34. Layer 18 will be referred to as the programming electrode, since data is stored in the resistance element 10 by causing electrons to tunnel from layer 16 to layer 18. The capacitance between layers 16 and 18 will be referred to as C_p.

layer 14 and substrate region 36 extend generally parallel with each other. As will be explained in more detail below, substrate region 36 and layer 14 are common to a number of resistance elements in a neuro-network according to the present invention. Layer 14 will be referred to as the erase electrode since the resistance element is erased by causing electrons to tunnel from layer 14 to layer 16. The capacitance of the coupling between electrodes 14 and 16 will be referred to as C_e.

To simplify Figures 1-2 the various oxide or other dielectric layers which are formed on the substrate and on each layer during the fabrication of resistance element 10 to electrically isolate it from the next level of semi-conductor material deposited on the device have been omitted. The requirements for the thicknesses of such materials are well known to those skilled in the eeprom arts.

As best seen in Figure 1, portion 30 of layer

18 forms the gate of an enhancement mode transistor 38 having a channel 40 disposed between substrate regions 20 and 22. Substrate regions 20 and 22 form the drain and source of transistor 38, respectively. A third portion 42 of layer 16 forms the gate of an insulated gate transistor 44, also referred to herein as the floating gate transistor. Transistor 44 is an enhancement mode transistor in the preferred embodiment, but could also be a depletion transistor. Substrate region 36 forms the source of transistor 48. Layer 14 overlies the channel 50 of transistor 48. Transistors 44 and 48 are connected to each other by region 52 between channel 46 and channel 50 of transistors 44 and 48, respectively. Region 52 is best described as a virtual junction. The combination of transistors 44 and 48 is equivalent to a single enhancement mode transistor having two adjacent gates. Here, portion 42 of layer 16 forms the first gate and layer 14 forms the second gate adjacent to said first gate.

Before describing the manner in which a resistance element according to the present invention is operated in a neuro-network, some advantages of a resistance element according to the present invention will be discussed. It is important that the effective resistance of a resistance element for use in a neuro- network be independent of the voltage across the resistance element for the range of voltage inputs to the neuro-network. Each neuron in the neuro-network performs a weighted sum of the inputs thereto. The weights in this sum are determined by the resistances of the resistance element used to connect the inputs to the operational amplifier which performs the summing operation. If the resistances vary with the input voltages, an incorrect result for the weighted sum will occur.

A floating gate transistor according to the present invention is a significantly better "resistor" than a typical CMOS FET. In a non-floating gate CMOS FET, the relationship between the current flowing from the drain to the source, I^_g, and the potential differences between the drain and the source (V_ds) and the gate and the source (V„_s) is given by

^Ids=^kvdsC ^(vgs^"vT>^"vds/^2] > (l) where Vm is the threshold voltage of the device. V_τ and k are constants which dependent on the geometry of the FET and the materials used to construct it. Eq. (1) takes into account first order effects and is valid for V_ds<(Vg_S-V_T) . From Eq. (1) , it is clear that the device will only act as an ideal resistor if (V-_g-Vi ) is much larger than V_ds/2. In this case, the device acts as a resistor whose resistance is determined by V__. If this condition is not satisfied, the effective resistance becomes a function of ^_s. As pointed out above, this condition is to be avoided.

A resistance element according to the present invention avoids this problem. For a floating gate transistor, it can be shown that

^vgs=^v0^+fvds' ⁽²⁾

where V_Q is the potential on the floating gate at a V_ds equal to zero volts and f is the capacitive coupling ratio. The capacitive coupling ratio is equal to C_s divided (C_s+Cp+C_e) . Thus, for a floating gate transistor,

^Ids^=kvdsC (^V0"^VT⁺⁽f-⁰•5⁾ V_ds] (3)

It is clear from Eq. (3) that if f=0.5, then the floating gate transistor acts as a resistor with a conductance of a[(V₀-V_T]. That is, the conductance is independent of V_ds and is determined by the charge stored on the floating gate.

In the case of resistive element 10, it is clear that the current is determined by more than the floating gate potentials. However, if the conductances of transistors 40 and 50 are much greater than the conductance of transistor 46, the current is approximately as described by Eq. (3) , and the ensemble can be made to approximate a resistor with a conduct- ance of k(V₀-V_T) . Methods for making the conductances of transistors 40 and 50 much greater than that of transistor 46 by appropriate biases and sizing are well known to those skilled in the art.

The manner in which charge is transferred to floating gate 16 is analogous to the scheme used to program a eeprom. A bias potential V_R is applied to layer 14, and a reference potential V_G is applied to substrate region 36. To minimize power consumption during the tunneling of electrons across either tunneling region 28 or tunneling region 34, V_R and V_G are selected so that no current is developed in channel 50. Accordingly, the gate-source voltage, (V_R-V_G) , of transistor 48 is normally biased negatively in the preferred embodiment of the present invention during tunneling so that transistor 48 remains in a "cutoff" condition irrespective of the drain voltage at virtual junction 52.

The amount of charge to be stored on floating gate 16 is determined by a data potential V_D applied to substrate region 20. Concurrently with applying V_D to substrate region 20, a control potential, V_H is applied to layer 18. V_H is selected to invert the conductivity of channel 40 sufficiently to conduct the full data potential, V_D to substrate region 22 through turned on transistor 38. V_H and V_D, when V_D is at its highest value, are selected to ensure that sufficient potential difference exists across the tunneling region 28 so that electrons tunnel to layer 16. When V_D is its lowest state, and V_H is set as described above, sufficient potential difference exists across tunneling region 34 so that electrons tunnel from layer 16 to layer 18.

For example, when V_D is high and V_H is sufficiently high, substrate regions 20 and 22 will be at V_D. In this case, the potential difference between layer 18 and substrate region 22 will be small. Floating gate 16 will also attempt to reach a high potential because of the capacitive coupling of capacitor C_s and the capacitive effects of tunneling region 34 and channel 46. As the potential of floating gate 16 goes high, a small potential difference will exist across tunneling region 34 and a large potential difference will exist across tunneling region 28.

Consequently, electrons will tunnel from layer 14 to floating gate 16.

Conversely, when V_D is low, the potential of substrate region 22 is also low,. The capacitance C_s between portion 24 of floating gate 16 and substrate region 22 as well as the capacitive effects of tunneling element 28 and channel region 46 will attempt to capacitively hold floating gate 16 low upon the application of V_H to layer 18. Therefore, the potential difference across tunneling region 34 will be large. As a result, electrons will tunnel from floating gate 16 to layer 18.

The manner in which the present invention may used to construct a neuro-network is illustrated in Figures 4 and 5. Figure 4 is a schematic diagram of a single "neuron" 400 which can be used as the basic building block of a feed-forward neuro-network. Neuron 400 calculates a weighted sum of the signals on presented on input lines 401. That is, neuron 400 calculates a function, g(s) where

s = Σ w^ (4)

where J is the voltage on the ith input line 401 and w^ is a weight value. The function, g(s) , is a non¬ linear function having a shape of the type shown in Figure 5. The shape of g(s) is not critical to the operation of a neuro-network constructed from such neurons; however, the shape does affect the computational ease with which the values of the weights, w^, can be calculated. The preferred form of g(s) is a sigmoidal curve.

In neuron 400, the summing function is carried out by operational amplifier 403. A feedback network comprising resistor 400 and diode pairs 405 and 406 controls the shape of g(s) . At absolute voltages below the sum of the zener and diode voltages, the output voltage, V_out is equal to the input current to amplifier 403 multiplied by the resistance of resistor 404.

The input current to amplifier 403 is the sum of the currents flowing through each resistance element 402. The current through any given resistance element 402 is proportional to the voltage on the input lin*

401 connect thereto. The constant of proportionality depends on the charge stored on the floating gate 411 of the resistance element. Hence, by changing the charge on floating gate 411 of the resistance element

402 connected to the ith input line, the value of w^ can be set.

The operation of neuron 400 is controlled by the voltages on word line 412 and source select line 410. To change the charge on the floating gates 410, source select line 410 is set to a low potential and word line 412 is set to a high potential. A voltage indicative of the desired stored charge on each floating gate 411 is placed on the corresponding input line 401 connected to the resistance element 402 containing the floating gate in question. The value of ^ is inversely related to the value of the voltage placed on the ith input line.

To operate the neuron in the computational mode, both source select line 410 and wordline 412 are set to approximately 5 volts. The output of operational amplifier 403 will then be proportional to g(s).

Although the above discussion has utilized a floating gate transistor of a particular configuration, it will be apparent to those skilled in the art that other floating gate transistor designs having programming and erase electrodes may be utilized. For example, U.S. Patent 4,314,265 to R. Simko and assigned to Xicor, Inc., and which is hereby incorporated by reference, describes another electrically-alterable non-volatile memory device having a floating gate and programming and erase electrodes. In the device taught therein, the programming electrode is coupled to the floating gate by a capacitance C_p, and the erase electrode is coupled to the floating gate by a capacitance C_e. Charge is transferred between the programming and erase electrodes in a manner analogous to that described above. Although this device is of a substantially different geometry than the device shown in Figures 1-3, it may also be utilized as a resistance element provided that the capacitive coupling ratio,

C_s/(C_p+C_e+C_s) , is substantially equal to 0.5. Here, C_s is the capacitance between the floating gate and the substrate.

It will also be apparent to those skilled in the art that devices having less linearity may be constructed by utilizing capacitive coupling ratios somewhat different that 0.5. It will also be apparent to those skilled in the art that because of second order effects, the best linearity may be achieved with a coupling ration which is slightly different than 0.5. In the preferred embodiment of the present invention, the capacitive coupling ratio is preferably in the range of 0.3 to 0.7.

There has been described herein a resistance element which is particularly well adapted for constructing neuro-networks. Various modifications to the present invention will become apparent to those skilled in the art from the foregoing description and accompanying drawings. Accordingly, the present invention is to be limited solely by the scope of the following claims.

Claims

-16-WHAT IS CLAIMED IS:

1. A resistive element comprising a portion of an integrated circuit, said resistive element comprising: a substrate of semiconductive material having drain and source regions therein; a channel region disposed between said source and drain regions; a floating gate electrode overlying a portion of said channel region and being capacitively coupled thereto and to said integrated circuit, the capacitive coupling being C_s and C_τ, respectively, wherein C_s/C_τ is between 0.3 and 0.7.

2. The resistive element of Claim 1 wherein said integrated circuit comprises: a programing electrode capacitively coupled to said floating gate electrode and adapted for allowing electrons to tunnel from said floating gate electrode to said programing electrode, the capacitance of said coupling being C-,; and an erasing electrode capacitively coupled to said floating gate electrode and adapted for allowing electrons to tunnel to said floating gate electrode from said erasing electrode, the capacitance of said coupling being C_e, wherein C_S/(C_S+C +C_e) is between 0.3 and 0.7,

3. A resistive element comprising: a substrate of a first conductivity type including therein first, second, and third substrate regions of the opposite conductivity type; a first channel region of said first conductivity type disposed between said first and second substrate regions; a second channel region of said first conductivity type disposed between said second and third substrate regions; a first electrode overlying a portion of said first substrate region, said first channel region, and a portion of said second substrate region, said first electrode being spaced from said substrate and insulated therefrom; a second electrode overlying a portion of said third substrate region and a portion of said second channel region, said second electrode being spaced from said substrate and insulated therefrom; a third electrode overlying said second substrate region and the portion of said second channel region which does not underlie said second electrode, said third electrode being spaced from said substrate and insulated therefrom, said third electrode including a first tunneling region adapted for allowing electrons to tunnel from said third electrode to said first electrode when said first electrode is at a sufficiently large positive potential with respect to said third electrode, said third electrode further including a second tunneling region adapted for allowing electrons to tunnel from said second electrode to said third electrode when said third electrode is at a sufficiently large positive potential with respect to said second electrode, wherein the capacitance between said third electrode and said substrate being C_g, the capacitance between said first and third electrodes being C^, and the capacitance between said second and third electrodes being C₂, and wherein

is between 0.3 and 0.7.