JP2002246487A - Semiconductor device and semiconductor operation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an MFMISFET semiconductor device and a semiconductor operation device, which have sufficient functions as a memory element, enable execution of accurate difference (absolute) operation without causing change of polarization vector and are driven a with small power consumption. SOLUTION: In the MFMISFET, a switch 10 for turning connection between a control gate 8 and a signal line 9 'on/off' is disposed in the control gate 8. The control gate 8 becomes electrically floating, by turning the switch 10 'off', keeping the control gate 8 provided with a prescribed potential, and it is not thereafter affected by a voltage applied to the control gate 6 and the polarized state of a charge storage film 7 does not change.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a so-called MFMI
The present invention relates to an SFET-type semiconductor device and a semiconductor arithmetic device having a plurality of such semiconductor devices and executing a predetermined arithmetic process.

[0002]

2. Description of the Related Art Recently, a ferroelectric memory (Metal-Ferroelectric-Metal-Insulator-Semiconductor) having a so-called floating gate structure and using a ferroelectric material for a dielectric film has been proposed.
Research on conductor FET (MFMISFET) has been active. This MFMISFET is expected as a semiconductor memory that can write and erase information without using a high voltage unlike an EEPROM using a paraelectric material for a dielectric film, and can realize a drastic reduction in power consumption. Have been.

By the way, for one input data composed of a plurality of elements, analog-digital fusion processing for selecting and outputting data closest to the input data from a template to a predetermined relationship with the input data is performed at a device level. Have been proposed by the present inventors.

As one mode of this semiconductor arithmetic device, a difference value for each element between the vectors is calculated corresponding to an input vector, and a vector satisfying a predetermined condition, for example, a difference absolute value is calculated based on the difference value. There is a method that selects a vector having the smallest sum (Manhattan distance) from the data group.

In order to realize such a semiconductor arithmetic device, a plurality of EEPROMs are arranged in a matrix and each EEPROM is read in consideration of reading out the floating gate potential.
A source follower is configured for the PROM. Specifically, stores the elements T _i of the template vector T to the i-th EEPROM, followed by the EEPROM
_Is applied. At this time, the E
The floating gate potential of the EPROM is (T _i -X _i )
(Correctly, a value obtained by adding a constant potential to the value), and the difference calculation is realized. Each EEP in this sense
ROM functions as a "processor", not just a storage element.

[0006]

As described above, the MF
Since the MISFET is a semiconductor element capable of realizing low power consumption, it is conceivable to configure the above-described semiconductor arithmetic device by using the MFMISFET instead of the EEPROM.

However, the MFMISFET can fix the read potential to a predetermined appropriate potential at which the polarization vector does not change in order to simply use it as a storage element. Since the analog signal X _i is further input while the potential T _i is applied, there is a problem that the polarization vector changes due to the input X _i and accurate difference calculation cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has a sufficient function as a storage element, and performs an accurate difference (absolute) calculation without causing a change in polarization vector. To be able to perform,
An MFMISFET type semiconductor device driven with low power consumption, and a plurality of such
It is an object of the present invention to provide a semiconductor computing device that executes digital fusion processing at a device level.

[0009]

Means for Solving the Problems As a result of intensive studies, the present inventors have reached the following aspects of the invention.

A semiconductor device according to the present invention includes a source / drain, a first electrode in an electrically floating state provided through the source / drain and a first insulating film, A second insulating film that does not include a ferroelectric material and is provided on a portion thereof; and a second insulating film provided so as to face the portion of the first electrode via the second insulating film. , A third insulating film having at least one layer containing a ferroelectric material provided on another portion of the first electrode, and the first insulating film via the third insulating film.
A third electrode provided so as to face the other portion of the first electrode, and a switch connected to the third electrode for turning on / off a connection between the third electrode and a predetermined signal line. And a switch.

In one aspect of the semiconductor device of the present invention, the switch is turned off in a state where a predetermined potential is applied to the third electrode.

In one aspect of the semiconductor device of the present invention, after the changeover switch is turned off, a predetermined potential is further applied to the second electrode.

In one aspect of the semiconductor device of the present invention, when changing the polarization state of the third insulating film, the changeover switch is turned on and the second electrode and the third electrode are respectively turned on. Apply a predetermined potential.

In one aspect of the semiconductor device of the present invention, one of the predetermined potentials applied to the second electrode and the third electrode is a ground potential, and the other is a positive potential.

In one aspect of the semiconductor device of the present invention, the second insulating film contains a high dielectric material.

In one aspect of the semiconductor device of the present invention, the second insulating film has a higher relative permittivity than the first insulating film.

The semiconductor arithmetic device of the present invention is configured by arranging a plurality of semiconductor devices in a matrix.
The semiconductor device includes a source / drain and the source / drain.
An electrically floating first electrode provided via a drain and a first insulating film, and a second insulating material provided on one portion of the first electrode and containing no ferroelectric material A film, a second electrode provided to face the part of the first electrode with the second insulating film interposed therebetween, and a strong electrode provided on another portion of the first electrode. A third insulating film having at least one film containing a dielectric material,
A third electrode provided so as to face the other portion of the first electrode via the third insulating film, and a third signal connected to the third electrode and a predetermined signal; A changeover switch for turning on / off the connection with the line.

In one embodiment of the semiconductor arithmetic device of the present invention, the switch is turned off in a state where a predetermined potential is applied to the third electrode.

In one embodiment of the semiconductor arithmetic device of the present invention, after the changeover switch is turned off, a predetermined potential is further applied to the second electrode.

In one aspect of the semiconductor arithmetic device of the present invention, when changing the polarization state in the third insulating film,
The switch is turned on, and the second switch is turned on.
A predetermined potential is applied to each of the third electrode and the third electrode.

In one aspect of the semiconductor arithmetic device of the present invention, one of the predetermined potentials applied to the second electrode and the third electrode is a ground potential, and the other is a positive potential.

In one aspect of the semiconductor processing device of the present invention, the second insulating film contains a high dielectric material.

In one aspect of the semiconductor arithmetic device of the present invention, the second insulating film has a higher relative dielectric constant than the first insulating film.

In one aspect of the semiconductor arithmetic device of the present invention, the signal line is common to each row.

In one aspect of the semiconductor arithmetic device of the present invention, the signal line is common to each column.

In one embodiment of the semiconductor arithmetic device of the present invention, a plurality of vectors are held as a data group, and a difference value for each element between the vectors is calculated in correspondence with the input vector.

In one aspect of the semiconductor arithmetic device of the present invention, a pair of the semiconductor devices are connected in parallel, and the absolute value of the difference between the respective vectors for each element is calculated.

In one aspect of the semiconductor arithmetic device of the present invention, a vector satisfying a predetermined condition is selected from the data group based on the difference value.

In one embodiment of the semiconductor arithmetic device of the present invention, among the plurality of semiconductor devices arranged in a matrix,
Each column corresponds to each vector constituting the data group, and each row corresponds to each element of the vector.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments to which the present invention is applied will be described below in detail with reference to the drawings.

(First Embodiment) In this embodiment, the MF
A MISFET type semiconductor device is disclosed. Figure 1
1A and 1B are schematic diagrams illustrating a main configuration of an MFMISFET of the present embodiment, wherein FIG. 1A is a schematic cross-sectional view of a main part of the MFMISFET, and FIG. 1B is a circuit diagram of the MFMISFET.

This MFMISFET is an impurity of a conductivity type opposite to that of the substrate 1 by ion implantation or the like into the element region of the silicon semiconductor substrate 1 (phosphorus, arsenic, etc., which are n-type impurities if the substrate 1 is p-type) Source / drain 2 into which p-type impurity such as boron is introduced if the substrate is n-type
And a laminated structure having functions of a capacitor and a voltage application electrode is arranged on the substrate 1.

The laminated structure is formed by patterning a channel formed by a source / drain 2 of a substrate 1 through a gate insulating film 3 and forming an electrically floating island-like floating gate electrode 4. A first charge storage film 5 made of a dielectric material not containing a ferroelectric material on one part of the floating gate electrode 4, and a first charge storage film 5 on the part of the floating gate electrode 4 via the first charge storage film 5. A first control gate electrode 6 which is patterned and capacitively coupled to the floating gate electrode 4, a second charge storage film 7 made of a ferroelectric material and formed on another portion of the floating gate electrode 4,
A pattern is formed on the other portion of the floating gate electrode 4 via a second charge storage film 7, and includes a second control gate electrode 8 capacitively coupled to the floating gate electrode 4. Thus, the floating gate electrode 4 (one portion), the first charge storage film 5,
And from the first control gate electrode 6 to the capacitor 1
1 is a floating gate electrode 4 (another part);
Charge storage film 7 and second control gate electrode 8
Respectively constitute the capacitors 12.

Here, when writing (erasing) information, the electric capacity of the capacitor 11 is compared with that of the capacitor 12 in consideration of effectively applying a voltage to the second charge storage film 7 which is a ferroelectric substance. Need to be somewhat larger. Specifically, the relative dielectric constant of the ferroelectric is 500 to 1000.
The first charge storage film 5 of the capacitor 11
Is formed of SiO ₂ or the like, the area of the capacitor becomes large. Therefore, it is preferable to form the first charge storage film 5 from a high dielectric material having a higher dielectric constant than an insulating material such as SiO ₂ .

Further, in the MFMISFET, a changeover switch 10 for turning on / off the connection between the second control gate electrode 8 and the signal line 9 is arranged on the second control gate electrode 8. By turning off the changeover switch 10 in a state where a predetermined potential is applied to the second control gate electrode 8, (the input terminal 8a of) the control gate electrode 8 becomes an electrically floating state. Control gate electrode 6
The polarization state of the second charge storage film 7 does not change without being affected by the voltage applied to (the input terminal 6a).

To change the polarization state of the second charge storage film 7, the changeover switch 10 is turned on and the input terminal 6a
The V ₁ to be applied to V ₂ to the input terminal 8a. Considering that writing and erasing are performed, the polarization state of the second charge storage film 7 can be both “increase” and “decrease”.
One may correspond to writing and the other to erasing. Specifically, this can be realized by setting _one of V ₁ and V ₂ to a positive potential and the other to a ground potential. As described above, in the present embodiment, writing / erasing can be performed extremely easily without generating a negative voltage for writing / erasing as in the conventional MFMISFET or using a special technique such as SOI.

Here, in the example shown in the figure, the charge storage film 7 is a single layer, but, for example, as shown in FIG. 2, a single ferroelectric film 21 and a normal ferroelectric film 22 are sandwiched therebetween. , 23 may be stacked to form the second charge storage film 7.

In view of various circumstances, a portion of the floating gate electrode 4, the first charge storage film 5, and the first control gate electrode 6 are connected to the capacitor 11.
Alternatively, it is also preferable to provide a plurality of capacitors 12 including other portions of the floating gate electrode 4, the charge storage film 7, and the second control gate electrode 8.

The MFMISFET of this embodiment is mainly used as a difference calculation element. Hereinafter, the operation function as the difference calculation element will be described. In brief, the polarization state of the second charge storage film 7 is changed by turning on the changeover switch 10 and applying a predetermined voltage. At that time, the polarization state is changed so that the floating gate potential becomes a certain value when the predetermined switch V is applied to the input terminal 6a of the first control gate electrode 6 with the changeover switch 10 turned off. Subsequently, by applying an input V _X is a predetermined analog signal switching switch 10 is turned off, the floating gate potential of the MFMISFET is proportional to the value (precisely (V-V _X) is a constant to the value (The value obtained by adding the potential), and the difference calculation is realized. At this time, the second control gate electrode 8
(Input terminal 8a) of the polarization state of the second charge storage film 7 without being affected by the application of the analog signal V _X for electrically in a floating state is unchanged.

When V and V _X are applied, a constant bias may be applied together with them. This bias is canceled during the difference calculation, and does not affect the output.

Specifically, the MFMISFE of this embodiment
T is configured as a difference operation element as described below. This example
Now, the amount of charge stored in the floating gate electrode 4
For adjustment, the so-called V_refAdopt the method. This V_refmethod
Is the storage voltage V corresponding to the value to be stored _memThe input end
When the voltage is applied to the element 6a and read, the floating gate
Potential φ_FGThere is an appropriate potential V_refSo that the second
This is a method of adjusting the polarization state of the charge storage film 7.

As shown in FIG. 3, the MFMISFET forms a source follower having a source or a drain connected to a load circuit 24 and one end of the load circuit 24 grounded for reading stored information. However, in the illustrated example, n
This shows a type MOS transistor configuration.

[0043] written to the storage voltage V _mem this MFMI
In SFET, upon application of a new input voltage V _X to the input terminal 6a, the floating gate potential phi _FG as a proportional constant gamma, the _{φ FG = γ () + V} ref. Therefore, a difference between the storage voltage and the input voltage appears as a floating gate potential. This floating gate potential can be read out as a drain-source current if, for example, an environment is set such that the MOS transistor operates in a saturation region.

By the way, in this MFMISFET, V_X-V_memIf <0, reading is disabled, so avoid this
Considering this, a configuration as shown in FIG. 4 is adopted. Immediately
At the time of writing, as shown in FIG.
(V_DD-V _mem) And φ_FG= V_ref The polarization state of the second charge storage film 7 is changed so that
You.

On the other hand, at the time of reading, as shown in FIG.
As shown in FIG._DD-V _X) Is applied.

In this case, (V _DD −
When applying (V _mem ) and (V _DD -V _X ), a constant bias may be applied together with them. This bias is canceled during the difference calculation, and does not affect the output.

Further, in this embodiment, as shown in FIG. 5, two MFMISFETs are combined to constitute a circuit for calculating the absolute value of the difference. This difference absolute value calculation circuit has two M
FMISFETs are connected in parallel, and a load circuit 24 is connected to the source or drain for reading stored information as described above.
To form a source follower with one end of the load circuit 24 grounded.

To execute the absolute difference calculation, first,
The other MFMISFET 31 has V_{me m}To the other MFM
(V_DD-V_mem) Is stored. Soshi
Therefore, the MFMISFET 31 has V_XTo MFMISFE
(V_DD-V_X) To output
Voltage V_outIs the proportionality constant of γ, V_TIs the threshold voltage
And V_out= Γ | V_X-V_mem| + V_ref-V_T And the difference absolute value | V_X-V_mem|
Can be

Although the embodiment using the MFMISFET of the present invention as a difference calculation element has been described above, the MFMISFET can be used as a normal storage element. Even in this case, it is not necessary to fix the read potential to a predetermined appropriate potential where the polarization vector does not change unlike the related art.

According to the present invention, there is no restriction on the read potential of the conventional MFMISFET, and the same operation as the EEPROM can be performed during the read operation. Therefore, it is very effective to use it for adjusting the threshold value of the MOS transistor. For example, it is possible to significantly improve the performance of an operational amplifier by using it for trimming an operational amplifier that requires symmetry.

Further, as shown in FIG. 6, when the present invention is applied to form a neuron MOS inverter, as shown in FIG.
The OR circuit can be separated. This neuron M
Since the input of the ferroelectric film is floating, the OS inverter has an advantage that the gain of the floating gate is improved as compared with the conventional case. In any case, writing can be performed with lower power consumption than EEPROM, and furthermore, writing can be performed at high speed.

Therefore, it can be expected to be applied to an extremely wide range of application fields, for example, a logic circuit system having high flexibility that can arbitrarily switch logic functions in real time can be easily configured.

As described above, according to this embodiment, in addition to having a sufficient function as a storage element, it is possible to execute an accurate difference (absolute) operation without causing a change in polarization vector. MFMISFET driven with low power consumption is realized.

(Second Embodiment) In the present embodiment, the first
A semiconductor arithmetic device in which a plurality of MFMISFETs disclosed in the embodiments are arranged in a matrix is disclosed. This semiconductor arithmetic device calculates a difference value for each element between the vectors in accordance with the input vector, and based on the difference value,
It has a function of selecting a vector satisfying a predetermined condition, in this case, a vector having the smallest sum of the absolute differences (Manhattan distance) from the data group.

FIG. 8 is an equivalent circuit diagram showing a main configuration of the semiconductor arithmetic device of the present embodiment. In this semiconductor arithmetic device, one in which the capacitor 33 is connected to the pair of MFMISFETs 31 and 32 shown in FIG. 5 is used as one constituent unit, and the constituent units are arranged in a matrix with a common input terminal for each row. And the evaluation circuit 3
4 are connected.

Here, a different template is used for each column.
vector

[0057]

(Equation 1)

Is stored. Here, focusing on the first column, a pair of MFMs in the i-th row and the first column
If T _i is stored in ISFETs 31 and 32, the input is V _i , and the output voltage is a _outi ,

[0059]

(Equation 2)

By inputting these output voltages to a predetermined adder,

[0061]

(Equation 3)

Is obtained. Here, {V _i } forms an input vector.

As described above, each pair of MMFMISFEs
T is a circuit that outputs the absolute value of the difference between each element of the input vector and the template vector, and each column is a circuit that outputs the Manhattan distance between the input vector and the template vector.

FIG. 9 shows a specific example of the adder. The adder and the lower electrode and the common, it is opposed to each of the upper electrode with respect to the lower electrode, thus the capacitor C _1, C ₂ each formed by parallel connection, ..., and C _n, and these And a capacitor C ₀ connected in series. If a MOS transistor structure is used in which the lower electrode is a floating gate electrode, the function is similar to a mathematical model of a neuron, that is, a so-called neuron MO.
It becomes an S transistor.

Here, the potential V _{tot of the} lower electrode is determined by assuming that the electric charge Q has been stored in advance.

[0066]

(Equation 4)

Is obtained. In this case, load elements for constituting the source follower are capacitors C ₁ , C ₂ ,.
_n, and C ₁ = C ₂ =... = C _n = C (electrical capacity of the capacitor 33). Here, C ₁ , C ₂ ,..., C _n may be set to different values, and the Manhattan distance weighted for each element may be calculated.

The outputs V _out1 , V _out2 ,
...

[0069]

(Equation 5)

These outputs are input to an evaluation circuit 34, which is a so-called Wiener take all (WTA) circuit, and a vector satisfying a predetermined condition, here, a vector having the smallest Manhattan distance is selected from the data group. You.

As described above, according to the present embodiment, in addition to having a sufficient function as a storage element, it is possible to execute accurate difference (absolute value) calculation without causing a change in polarization vector. The MFMISFET disclosed in the first embodiment, which is driven with low power consumption, constitutes a difference absolute value calculation device, and can execute analog / digital fusion processing at a device level, thereby achieving a huge and vague in the real world. It is possible to respond to requests as much as possible.

(Third Embodiment) In the present embodiment, the first
A semiconductor memory device in which a plurality of MFMISFETs disclosed in the embodiments are arranged in a matrix is disclosed.

FIG. 10 is an equivalent circuit diagram showing a main configuration of the semiconductor memory device of the present embodiment. This semiconductor memory device is configured by arranging a plurality of MFMISFETs shown in FIG. 1 in a matrix, has a common source line and drain line in the row direction, and has a sense amplifier 41 connected to each row. Each MFMISFET has a sense amplifier 41
A switch 42 composed of a MOS transistor for selecting a connection to is connected. The switches 42 are connected by a common signal line (word line) in the column direction. Further, the source line and the drain line in the column direction may be shared, and the sense amplifier 41 may be connected to each column.

As described above, by preparing the sense amplifier 41 for each row, writing / reading can be performed in a row-parallel manner, and the second charge accumulation can be performed depending on whether a voltage is applied to either the program line or the analog line. Since the direction of the electric field applied to the film 7 can be changed, the erasing operation is not necessarily required.

A method for writing information using the semiconductor memory device of this embodiment will be described with reference to a read flow shown in FIG. Here, one row and one column and two rows and one column in FIG.
V0, V are applied to the MFMISFETs (M0, M1)
An example in which 1 is written will be described.

First, the word (word) 0 is set to “1”, the switch 42 is turned on, M0 and M1 are respectively connected to the sense amplifier 41, and then the write / read (read / write) 0 is set to “0”. The switch 42 is turned off. At this time, the other Write / Read are also set to “0”.

The following steps are performed in parallel for each row.
Be executed. For one row, Analog
0 to V0, and for 2 rows, Analog1 to V1.
And the floating gate potential φ_FGIs the reference
Pressure V _refIf not equal, Write for one line
/ Read0 is set to “1” and the changeover switch 10 is turned on.
Write / Read0 is set to "1" for 2 rows
To turn on the changeover switch 10 so that Table A
The force is applied, and the inputs in Table B are applied to the two rows. here
The step of setting each Write / Read to “1” is as follows.
Synchronized.

Subsequently, Write / Read0 is set to "0".
And the changeover switch 10 is turned off.
write / Read0 is set to “0” and the changeover switch 10
Is turned off, V0 is applied to Analog0 in the first row, and V1 is applied to Analog1 in the second row.

When the floating gate potential φ _FG is equal to the reference voltage V _ref , Program
m (program) 0 and Analog 0 are set to the ground potential, and for two rows, Program 1 and Analog
1 is set to the ground potential, and the writing of M0 and M1 ends.

After all the memory cells have been written through the above steps, the write operation is completed.

Here, even when the changeover switch 10 is on, if both the analog line and the program line are set to the ground potential, no new writing occurs.

Next, a method for reading information using the semiconductor memory device of this embodiment will be described. First, all Wri
The te / Read line is set to “0”, and the Word line corresponding to the memory cell to be read is set to “1”.
Connect to sense amplifier 41.

Subsequently, a ramp voltage is applied to the analog line, and a value when the output of the sense amplifier 41 is inverted is obtained by sample hold. This value is the written value.

Specifically, at the time of reading using the lamp voltage, as shown in FIG. 12, as the lamp voltage is applied, the floating gate potential φ _FG rises accordingly, and lamp voltage becomes V _mem having stored when phi _FG becomes the reference voltage V _ref.

Here, the binary voltage is used without using the lamp voltage.
If a signal is added to the analog line in the manner of the search, reading can be performed with the bit accuracy of the number of times the signal is added. Specifically, for example, when considering with 3-bit precision, as shown in FIG. 13, the determination is first made with "100" (= 1 / 2V _DD ). At this time, since φ _FG <V _ref , “11
The following judgment is made at 0 "(= 3/4 V _DD ). This time, φ _FG >
Since it is V _ref , “101” (= 5/8 V _DD ) is a value read with 3-bit accuracy.

In the semiconductor memory device of FIG. 10, if the erase operation is performed prior to writing, the Program line can be set to the ground potential at the time of writing.

Further, as shown in FIG. 14, the sense amplifier 41 is provided with a transistor 43 paired with a switch 42 for selecting a word line, so that a source line of a memory cell is connected to a ground potential. It can be. As a result, as shown in FIG.
A configuration is possible in which the gram line and the source line are common to each row. Further, as shown in FIG.
source line may be common.

A method of erasing information in the semiconductor memory device having the structure shown in FIG. 15 or FIG. 16 will be described. First,
All the Analog and Word lines are set to the ground potential, and Write / Rea corresponding to the memory cell to be erased is set.
The d line is set to “1”, and the changeover switch 10 is turned on.
Here, if a plurality of Write / Read lines are set to “1”, information of a plurality of memory cells sharing a Source line is erased.

Then, V _erase (> 0) is applied to the source line corresponding to the memory cell to be erased. At this time, the other source lines are kept at the ground potential. Here, if V _erase (> 0) is applied to a plurality of Source lines, information of a plurality of memory cells sharing a Write / Read line is erased.

As described above, the Write / Read line,
Depending on the selection of the Source line, information of a plurality of memory cells can be erased two-dimensionally. Further, it is also possible to collectively erase information of all memory cells in the row direction and the column direction.

As described above, according to the present embodiment, by configuring a semiconductor memory device using an MFMISFET, it is possible to perform a simple (reliable) write (erase) / read operation with low power consumption. Become.

In the semiconductor memory device of the present embodiment, for example, the semiconductor memory device shown in FIG. 16, as shown in FIG. 17, a pair of adjacent MFMISFETs (here, a pair of MFMISFETs in the same column in adjacent rows) are used. On the other hand, by connecting the capacitor 51 and the switch 52 as shown in the figure, a circuit equivalent to the absolute difference calculating device of FIG. 1 in the first embodiment can be easily realized.

[0093]

According to the present invention, in addition to having a sufficient function as a storage element, it is possible to execute an accurate difference (absolute) operation without causing a change in a polarization vector, thereby achieving low power consumption. And an MFMISFET-type semiconductor device driven by a plurality of semiconductor devices, and a semiconductor arithmetic device that executes analog / digital convergence processing at a device level.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a main configuration of an MFMISFET according to a first embodiment.

FIG. 2 is a schematic sectional view showing another configuration example of the charge storage film made of a ferroelectric material in FIG.

FIG. 3 is an equivalent circuit diagram showing an example in which a source follower is configured using the MFMISFET of FIG. 1;

FIG. 4 is an equivalent circuit diagram showing another example of voltage application to the MFMISFET of FIG.

FIG. 5 is an equivalent circuit diagram showing an arithmetic circuit for calculating a difference absolute value formed by combining two MFMISFETs of FIG. 1;

FIG. 6 is an equivalent circuit diagram showing a configuration of a neuron MOS inverter according to the present invention.

FIG. 7 is a diagram for explaining that a NAND circuit and a NOR circuit can be selectively realized by a neuron MOS inverter to which the present invention is applied;

FIG. 8 is an equivalent circuit diagram illustrating a main configuration of a semiconductor processing device according to a second embodiment.

FIG. 9 is an equivalent circuit diagram showing a specific example of an adder that is a component of the semiconductor arithmetic device according to the second embodiment.

FIG. 10 is an equivalent circuit diagram showing a main configuration of a semiconductor memory device according to a third embodiment.

FIG. 11 is a flowchart showing a method of writing information using the semiconductor memory device according to the third embodiment.

FIG. 12 is a characteristic diagram showing the time dependency of a reference voltage V _ref when reading is performed using a ramp voltage.

FIG. 13 is a characteristic diagram showing the time dependency of a reference voltage _Vref when reading is performed in the manner of a binary search.

FIG. 14 is an equivalent circuit diagram showing another configuration example of the sense amplifier.

FIG. 15 is a partial equivalent circuit diagram showing an example in which a Program line and a Source line are common to each row.

FIG. 16 is an equivalent circuit diagram showing an example in which two rows of Source lines are shared.

FIG. 17 is an equivalent circuit diagram showing a state in which the equivalent circuit of FIG. 16 is modified to form a circuit equivalent to the absolute difference calculating device of FIG. 1 in the first embodiment;

[Explanation of symbols]

 Reference Signs List 1 silicon semiconductor substrate 2 source / drain 3 gate insulating film 4 floating gate electrode 5 first charge storage film 6 first control gate electrode 6a, 8a input terminal 7 second charge storage film 8 second control gate electrode 10 Changeover switch 11, 12, 33, 51 Capacitor 21 Ferroelectric film 22, 23 Paraferroelectric film 24 Load circuit 31, 32 MFMISFET 34 Evaluation circuit 41 Sense amplifier 42, 52 Switch 43 Transistor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) G11C 16/02 H01L 27/10 444A H01L 27/105 F-term (Reference) 5B025 AA02 AA07 AC02 AE06 5F083 EP03 EP22 FR07 GA05 5F101 BA02 BA12 BA62 BB02 BD20 BD33

Claims (20)

[Claims] A source / drain; a first electrode in an electrically floating state provided through the source / drain and a first insulating film; and a first electrode provided on one portion of the first electrode. A second insulating film containing no ferroelectric material, a second electrode provided so as to face the part of the first electrode via the second insulating film, A third insulating film having at least one layer containing a ferroelectric material provided on another portion of the first electrode; and the other portion of the first electrode via the third insulating film. And a changeover switch connected to the third electrode for turning on / off a connection between the third electrode and a predetermined signal line. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein the switch is turned off in a state where a predetermined potential is applied to the third electrode. 3. The semiconductor device according to claim 2, wherein a predetermined potential is further applied to the second electrode after the changeover switch is turned off. 4. When changing the polarization state of the third insulating film, the changeover switch is turned on, and a predetermined potential is applied to each of the second electrode and the third electrode. The semiconductor device according to claim 1, wherein 5. The semiconductor device according to claim 4, wherein one of the predetermined potentials applied to the second electrode and the third electrode is a ground potential, and the other is a positive potential. 6. The semiconductor device according to claim 1, wherein said second insulating film contains a high dielectric material. 7. The semiconductor device according to claim 1, wherein the second insulating film has a higher relative dielectric constant than the first insulating film.
7. The semiconductor device according to any one of claims 6 to 6. 8. A semiconductor arithmetic device configured by arranging a plurality of semiconductor devices in a matrix, wherein the semiconductor device is provided via a source / drain, the source / drain, and a first insulating film. A first electrode in an electrically floating state, a second insulating film not including a ferroelectric material provided on one portion of the first electrode, and a second insulating film interposed therebetween. A second electrode provided so as to face the part of the first electrode, and at least one layer of a film containing a ferroelectric material provided on another portion of the first electrode. A third insulating film having: a third electrode provided to face the other portion of the first electrode via the third insulating film; and a third electrode connected to the third electrode, A switch for turning on / off the connection between the third electrode and a predetermined signal line Wherein a and a switch. 9. The semiconductor arithmetic device according to claim 8, wherein the changeover switch is turned off in a state where a predetermined potential is applied to the third electrode. 10. The semiconductor arithmetic device according to claim 9, wherein a predetermined potential is further applied to the second electrode after the changeover switch is turned off. 11. The method according to claim 11, wherein when changing the polarization state of the third insulating film, the changeover switch is turned on, and a predetermined potential is applied to each of the second electrode and the third electrode. Claims 8 to 10
The semiconductor arithmetic device according to claim 1. 12. The semiconductor arithmetic device according to claim 11, wherein one of the predetermined potentials applied to the second electrode and the third electrode is a ground potential, and the other is a positive potential. 13. The semiconductor arithmetic device according to claim 8, wherein said second insulating film contains a high dielectric material. 14. The semiconductor arithmetic device according to claim 8, wherein said second insulating film has a higher relative dielectric constant than said first insulating film. 15. The semiconductor arithmetic device according to claim 8, wherein said signal line is common to each row. 16. The semiconductor arithmetic device according to claim 8, wherein said signal line is common to each column. 17. The semiconductor arithmetic device according to claim 16, wherein a plurality of vectors are held as a data group, and a difference value for each element between the vectors is calculated corresponding to the input vector. . 18. A semiconductor device comprising: a pair of semiconductor devices connected in parallel;
18. The semiconductor arithmetic device according to claim 17, wherein a difference absolute value for each element between the vectors is calculated. 19. The semiconductor arithmetic device according to claim 17, wherein a vector satisfying a predetermined condition is selected from the data group based on the difference value. 20. A plurality of semiconductor devices arranged in a matrix, wherein each column corresponds to each vector constituting the data group, and each row corresponds to each element of the vector. Item 20. The semiconductor arithmetic device according to any one of items 17 to 19.