JP3114155B2 - Analog memory element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog memory device which stores an amount of charge as an analog amount and which can easily increase and decrease the amount of charge little by little.

[0002]

2. Description of the Related Art There have been many cases where it is necessary to store an analog signal amount on an LSI. For example, storage of voice and image signals, storage of weighting factors of neural circuits, and the like are typical examples. However, conventionally, there has been no semiconductor device that can be practically used for storing an accurate analog amount. Therefore, when analog storage is required, there is no choice but to digitize it and store each bit in a digital memory. As a result, the number of memory devices and the occupied area increase.

Therefore, development of a memory device capable of directly storing an analog signal amount has been desired. The most likely conventional device is a so-called floating gate MOS transistor that performs analog storage with the amount of charge stored in a gate that is electrically isolated from the surroundings. However, this floating gate MOS transistor is not suitable for accurate analog storage as it is. That is,
In the conventional floating gate MOS transistor, when injecting charge from the tunnel junction into the floating gate, a large amount of charge is injected in a short time and the state becomes equilibrium. Therefore, it is impossible to accurately store an arbitrary analog amount. It was difficult. This problem will be briefly described below with reference to the drawings.

FIG. 5 shows a structure of a conventional floating gate MOS transistor. In the figure, 1 is a floating gate, 2 is a control gate, and 3 is a tunnel oxide film.

FIG. 6 shows an equivalent circuit. In this device, when a voltage for charge injection is applied to the control gate 2, a high electric field is applied to the electron barrier of the tunnel oxide film 3, and as a result, a tunnel current flows between the drain and the floating gate through the tunnel oxide film 3, and the floating gate 1 Is injected into the substrate. As the charge is injected, the potential of the floating gate changes, the voltage applied to the tunnel junction drops, and the tunnel current stops flowing, reaching an equilibrium state. When a pulse voltage for charge injection is applied between the control gate and the drain, a time change of the floating gate potential according to the amount of charge injected into the floating gate is shown by a curve B in FIG. In the case of the conventional structure, there is nothing to block the current flowing from the tunnel junction to the floating gate, so a large amount of charge immediately flows into the entire floating gate, and the charge reaches the saturation state in a very short time. Would. Therefore, it has been difficult to accurately adjust the amount of charge to be injected little by little.

[0006]

SUMMARY OF THE INVENTION The present invention has been proposed in order to improve the above-mentioned drawbacks, and it is difficult to finely and efficiently adjust the amount of charge stored in the floating gate. An object of the present invention is to provide an analog memory device having a floating gate structure that solves the above problem.

[0007]

In order to achieve the above object, the present invention provides a floating gate, a tunnel junction for taking charge in and out of the floating gate, and a drain current value which varies according to the amount of charge in the floating gate. In a memory device having a MOS transistor section, a floating gate has a first portion through which a charge is transferred through a tunnel junction and a second portion which controls a MOS transistor section via a semiconductor layer.
And a charge injection control electrode for adjusting an electric resistance by applying an electric field to the semiconductor layer, and being provided in proximity to the semiconductor layer, and sandwiching the first portion of the floating gate. An object of the present invention is to provide an analog memory element characterized in that a tunnel current control electrode and a charge injection electrode are provided.

[0008]

According to the present invention, a semiconductor layer is interposed between a first portion and a second portion of a floating gate, and the resistance of the semiconductor layer is changed, so that the amount of charge to be injected can be accurately adjusted little by little. , The accuracy of writing and erasing the analog amount can be improved.

[0009]

Next, an embodiment of the present invention will be described. The embodiment is merely an example, and it goes without saying that various changes or improvements can be made without departing from the spirit of the present invention.

FIG. 1 shows an analog memory device according to the present invention. The figure shows a MOSFET, and a p-type semiconductor layer 14 is shown.
, A source 12, a drain 13, and a charge injection electrode 4
Is formed, and a first portion 6 of the floating gate and a second portion 11 are provided in an oxide film above the semiconductor layer, and a semiconductor layer 9 is provided between the first portion and the second portion. Is provided. A tunnel oxide film 5 is formed between the charge injection electrode 4 and the first portion 6 of the floating gate. Further, a tunnel current control electrode 7 is provided above the first portion 6 of the floating gate, and a charge injection control gate 8 is formed near (above or below) the semiconductor layer 9. 1
0 indicates a gate.

A feature of the present invention is that the floating gate serves as a first portion 6 through which electric charges enter and exit through a tunnel junction.
And a second portion 11 for controlling the MOS transistor portion. These portions are connected via a semiconductor layer 9 and charge injection for adjusting an electric resistance by applying an electric field to the semiconductor layer. It has a structure in which a control gate 8 is formed. On the other hand, in the conventional structure, the two parts of the floating gate are electrically short-circuited. In the structure of the present invention, the charge transfer between the two parts of the floating gate is controlled. The difference is that the total amount of charge injected into the floating gate can be controlled in small increments.

FIG. 2 shows an equivalent circuit of the device of the present invention, and its operation will be described below. In this structure, the semiconductor layer 9 operates as a field effect transistor (FET) having the charge injection control gate 8 as a gate. That is, the electric resistance of the semiconductor layer 9 changes according to the voltage of the charge injection control gate 8. OFF when the electric resistance is high, O when the electric resistance is low
N, and the voltages of the corresponding charge injection control gates 8 are referred to as an OFF voltage and an ON voltage, respectively. First,
An OFF voltage of the charge injection control gate 8 is set, and a voltage is applied between the tunnel current control electrode 7 and the charge injection electrode 4 to flow a current through the tunnel junction. In the first portion 6 of the floating gate on the tunnel junction, the charge immediately accumulates to saturation. Next, the voltages of the tunnel current control electrode 7 and the charge injection electrode 4 are restored to prevent the tunnel current from flowing, and then the charge injection control gate 8 is set to the ON voltage to set the first portion of the floating gate. Charge accumulated in MOS 6
The FET is diffused to the second portion 11 of the floating gate.
If the capacitance of the first part 6 of the floating gate is made sufficiently smaller than the capacitance of the second part 11 of the floating gate, the amount of injected charge is small when viewed from the whole floating gate, and the floating gate Of the second portion 11 is also slight. Therefore, the total amount of charges injected for a certain charge injection pulse voltage is smaller than that of the conventional device. That is, the temporal change of the floating gate potential depending on the amount of injected charge is as shown by the curves (D, E) in FIG. 7, and the potential of the second portion 11 of the floating gate gradually changes as shown in (E).

As described above, according to the device of the present invention, the amount of charge to be injected can be accurately adjusted little by little. Therefore, the accuracy of writing / erasing an analog amount is improved. In addition, since the amount of small change in charge can be considered to be approximately constant with respect to a constant control voltage pulse, the hysteresis characteristic of charge injection control in writing and erasing is eased, and control of charge is simplified. Become.

FIG. 1 shows a specific example of the element structure of the first embodiment of the present invention. The semiconductor layer 9 is provided between the first portion 6 of the floating gate through which charges are transferred through the tunnel junction and the second portion 11 of the floating gate that controls the MOS transistor portion. The floating gate may be formed of polycrystalline silicon. Semiconductor layer 9
Is required to be larger than the operating resistance value of the tunnel junction, and the value is generally 1 GΩ or more, depending on the shape and dimensions of the element. Further, a charge injection control gate 8 is provided near the semiconductor layer 9. Since the resistance of the semiconductor layer 9 changes according to the potential of the charge injection control gate 8, the charge transfer between the first portion 6 of the floating gate and the second portion 11 of the floating gate can be controlled. For reference, FIG. 3 shows ON / OFF characteristics of a thin film transistor having a structure partially equivalent to the present invention. When the gate voltage changes by 4 V near 0 V, the current value changes by five digits. The resistance change also changes by five digits. The actual resistance value can be adjusted by the shape of the semiconductor layer 9 and the amount of impurities.

FIG. 4 shows a device structure according to a second embodiment of the present invention. This configuration is different from the first embodiment in that a charge injection control gate 15 is provided on the semiconductor substrate side in addition to the charge injection control gate 8 'for controlling the resistance of the semiconductor layer 9'. An electric field can be applied to the semiconductor layer 9 'more efficiently than in the first embodiment. Note that the charge injection control gate 8 'may be omitted.

[0016]

As described above, according to the present invention,
In a memory element including a floating gate, a tunnel junction for taking charge in and out of the floating gate, and a MOS transistor part in which a drain current value changes in accordance with a charge amount of the floating gate, the floating gate sandwiches a semiconductor layer; A first portion for taking in and out a charge through a tunnel junction and a second portion for controlling a MOS transistor portion are coupled to each other, and an electric field is applied to the semiconductor layer in the vicinity of the semiconductor layer to adjust its electric resistance. A charge injection control electrode is provided, and a tunnel current control electrode and a charge injection electrode are provided with the first portion of the floating gate interposed therebetween. By simply applying the above control voltage pulse, the amount of charge of the floating electrode can be easily and efficiently adjusted very finely and accurately.
Therefore, if the analog memory element of the present invention is used in a synapse circuit of a neural network, learning of a synapse load can be easily and efficiently performed by simple pulse control, and a neurochip having a learning ability can be manufactured.

[Brief description of the drawings]

FIG. 1 shows a device structure diagram of a first embodiment of the present invention.

FIG. 2 shows an equivalent circuit of the present invention.

FIG. 3 shows ON / OFF characteristics of a thin film transistor.

FIG. 4 shows a device structure diagram of a second embodiment of the present invention.

FIG. 5 is a structural view of a conventional floating gate type MOSFET.

FIG. 6 shows an equivalent circuit of a conventional structure.

FIG. 7 shows a schematic diagram of a temporal change of a floating gate potential.

[Explanation of symbols]

 Reference Signs List 1 floating gate 2 control gate 3 tunnel oxide film 4 charge injection electrode 5 tunnel oxide film 6 first portion of floating gate 7 tunnel current control electrode 8 charge injection control gate 9 semiconductor layer 10 gate 11 second portion of floating gate 12 Source 13 Drain 14 Semiconductor layer 15 Charge injection control gate

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-25182 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29 / 788 H01L 29/792

Claims (1)

(57) [Claims] 1. A memory device comprising: a floating gate; a tunnel junction for transferring charge into and out of the floating gate; and a MOS transistor having a drain current value that changes in accordance with the amount of charge in the floating gate. A first portion for transferring charges through a tunnel junction and a second portion for controlling a MOS transistor portion are coupled to each other with the layer interposed therebetween, and an electric field is applied to the semiconductor layer in proximity to the semiconductor layer, An analog memory device, comprising: a charge injection control electrode for adjusting the electric resistance; and a tunnel current control electrode and a charge injection electrode sandwiching a first portion of the floating gate. .