WO1995006905A1

WO1995006905A1 - Analog, uv light-programmable voltage reference in cmos technology

Info

Publication number: WO1995006905A1
Application number: PCT/NO1994/000144
Authority: WO
Inventors: Tor Sverre Lande; Aanen Abusland
Original assignee: Tor Sverre Lande; Aanen Abusland
Priority date: 1993-08-31
Filing date: 1994-08-31
Publication date: 1995-03-09
Also published as: NO933103L; AU7666794A; NO933103D0

Abstract

An analog UV-light programmable voltage reference implemented in CMOS technology is programmed by exposing UV-structures to ultraviolet light. The voltage reference comprises two UV-structures provided between respectively each supply line and a floating node connected to the gate electrode of a field-effect transistor for detection of the voltage of the floating node. The voltage of the floating node is stabilized on a value determined by the voltages of the UV-structures, the capacitance of the floating node being given by the sum of the capacitance of the UV-structures, the capacitance of the gate electrode and possible parasitic capacitances. The analog voltage reference is used for implementing respectively an analog voltage adder, analog amplifiers with either increased linear input range or accurately determined amplification, as well as a UV-light programmable analog memory. A method of programming the analog memory is disclosed.

Description

Analog, UV light-programmable voltage reference in CMOS technology

The invention concerns an analog, UV light-programmable voltage reference, wherein the voltage reference is implemented in CMOS technology, and wherein the programming includes exposing UV structures to ultraviolet light. The invention further concerns various analog components which utilize the voltage reference according to the invention, viz. an analog voltage adder according to the introduction of claim 6, an analog amplifier with extended linear input range according to the introduction of claim 7, a second analog amplifier with extended linear input range according to the introduction of claim 9, an analog amplifier with accurately determined amplification according to the introduction of claim 11 , and a UV light- programmable analog memory according to the introduction of claim 12. Finally the invention also concerns a method for programming an analog memory using ultraviolet light.

In analog neural network implementations on a semi-conductor chip, e.g. a neural network, a major part of the chip will have to be dedicated to distributing the differential signal. A locally generated voltage reference will be capable of reducing the need for global wiring of differential signals. When implementing analog neural networks it will also be necessary to store weights, which requires an analog memory which may either be a short-term or a long-term memory. Moreover, in large analog networks, accumulated voltage deviations will be a problem. One possible solution to this problem will be local voltage adjustment and storage of adjusted voltages.

The implementation of a long-term analog memory in CMOS technology involves the storage of the charge associated with a voltage in a capacitor with minimal leakage. For this purpose the fact can be exploited that the silicone dioxide which insulates the various layers of a semi-conductor chip from each other will become conductive, albeit with a relatively high resistance, when exposed to ultraviolet (UV) light and be a very good insulator when not exposed to UV light. An induced conductor of this kind is called a UV conductor. A charge can then be placed on the gate electrode of a field- effect transistor when an overlap between a layer with a controlled voltage and the floating gate is exposed to UV light. A structure of this nature is called a UV structure. When the UV light is turned off, the floating gate will retain the charge.

A UV structure according to the prior art for programming a floating gate is illustrated in figure 1. The UV structure is in the form of a capacitor which is exposed to ultraviolet light. A programming circuit injects current into the floating gate through the UV conductor, which is connected between the floating gate and the control node across a gap with capacitive coupling across the gap. The programming circuit may be any suitable circuit and a single transistor, a transconductance amplifier or a NOR gate have been employed. The UV conductor across the gap is non-linear, depending on the voltage across the nodes. The conductance decreases with decreasing voltage, and at low voltages will approach that of non-illuminated silicon dioxide. Non-linearity implies that the voltage of the floating gate can never quite match that of the control node.

The object of the present invention is to employ UV structures of the above-mentioned type in order to generate and store reference voltages using standard CMOS technology for implementing large analog networks on a semi-conductor chip. A second object is to be able to generate and store voltage references locally, thus substantially reducing the amount of global wiring in large analog networks. A further object is to be able to store such reference voltages represented by stored charges anywhere in the network and to be able to manipulate these charges by capacitive coupling. This makes it possible to implement various applications for use in large, analog networks, such as adders, amplifiers and memories.

The above-mentioned and other objects are achieved according to the invention in that the voltage reference comprises a first and a second UV structure between each supply rail and a floating node connected with the gate electrode of a field-effect transistor for detection of the floating node's voltage, and that the floating node's voltage is stabilized at a value determined by the ratio between the voltages in the first and the second UV structures when they are exposed to ultraviolet light, the capacitance of the floating node being given by the sum of the capacitances of the UV structures, the gate electrode's capacitance and any parasitic capacitances.

An analog voltage adder according to the present invention is characterized by the features presented in the characterizing part of the independent claim 6. A first analog amplifier according to the present invention is characterized by the features presented in the characterizing part of the independent claim 7, and a second analog amplifier according to the present invention is characterized by the features presented in the characterizing part of the independent claim 9. A third analog amplifier according to the present invention is characterized by the features presented in the characterizing part of the independent claim 11.

The present invention further comprises a UV light-programmable analog memory which is characterized by the floating node of the voltage reference being connected with the output of a programming circuit via a control capacitor, by a voltage follower being connected in parallel over the terminals of the control capacitor, the reference input of the voltage follower being connected with the floating node and its output with the control capacitor via a control node, the control node thus attaining the same voltage as the floating node when the voltage follower is operated. A method for programming this analog memory is characterized by the features presented in the characterizing part of the independent claim 15.

The invention will now be described in more detail with reference to examples of application and the drawing, in which

figure 1 illustrates a UV structure according to the prior art and employed for programming a floating gate,

figure 2a is an analog, UV light-programmable voltage reference according to the present invention,

figure 2b is an equivalent coupling for the voltage reference in figure 2a when it is exposed to UV light,

figure 2c is a detailed and schematic representation of a UV structure as used in the voltage reference in figure 2a,

figures 3a, b, c are UV structures as used in the present invention, implemented in CMOS technology and illustrated in a plan view and a section along line A-A' respectively,

figure 4 is an analog adder according to the invention,

figure 5a is a first analog amplifier according to the invention,

figure 5b is a variant of the amplifier in figure 5a,

figure 6 is a second analog amplifier according to the invention,

figure 7 is a UV light-programmable analog memory according to the invention, and figure 8 is a variant of the analog memory in figure 7 implemented as a differential memory.

A programmable voltage reference according to the present invention is illustrated in figure 2a. It comprises 2 UV structures 1a, 1b, located in series between the supply voltages and via a so-called floating node 2 connected with the gate electrode of a field-effect transistor 3. The field effect transistor 3 will normally constitute a part of some kind of circuit combination, e.g. a multiplier or a transconductance amplifier. The floating node 2 corresponds to the floating gate in the prior art and denotes in general a node without conductance to other nodes in the network, i.e. a node which has no resistive or conductive connection to an external potential. The floating node is connected to a capacitance, one part of which constitutes the gate electrode of the field effect transistor 3, while the UV structures constitute a second capacitance. In addition there will also be parasitic capacitances to supply voltages and other nodes, and these can be summed into one parasitic capacitor to ground. Thus it should be understood that it is only for reasons of clarity that the floating node 2 in figure 2a and the subsequent figures is shown as the connection point between the UV structures. When the UV structures 1a, 1b in figure 2a are exposed to ultraviolet light, a resistive voltage divider is formed and the floating node 2 is charged to a point of equilibrium between the supply voltages. The value of this point of equilibrium is determined by the relative sizes of the two UV conductors in the structures 1a, 1b.

The equivalent coupling for the voltage reference when it is exposed to UV light is shown in figure 2b, and from this coupling it is easy to see that the floating node's voltage can be described by the equation

where V is the floating node's voltage. Since the resistance has a non-linear dependence on the floating node's voltage, formula I is a first-order non-linear differential equation.

When the UV light is removed from the UV structures, the floating node 2 will retain the charge. The voltage associated with the charge is detected by a field effect transistor 3. The UV structure used in the voltage reference in figure 2a is shown in more detail in figure 2c. The UV structure comprises a UV light-induced conductor connected via a capacitor. Normally the entire structure is protected by a metal shield, which is then provided with a window which permits the UV conductor to be exposed to ultraviolet light. In all the figures the UV structure is generally symbolized by a capacitor in a circle.

The following section discusses how UV structures as employed in the present invention are implemented in CMOS technology. The UV conductors are formed on the edges of the chip layers, and the programming time is therefore determined by that piece of the edge of the control node which is exposed over the floating node, i.e. the UV conductor's resistance and the area of the floating node, viz. the floating node's capacitance and the UV light's intensity. In order to maximize the first and minimize the second, the floating node should be long and narrow. Furthermore light will be able to be reflected between the layers and therefore it is necessary to have an overlap between them in order to protect the floating node from exposure to underlying nodes, e.g. substrate and well. It can be seen that by means of the UV structures described in the following, each of the UV structures 1a, 1b illustrated in fig. 2a in reality are integrated into a total structure with 2 UV conductors connected via the floating node.

A first embodiment of the UV structures as employed in the present invention is illustrated in figure 3a, in plan view (I) and section (II) along line A-A' respectively. The floating node was made of single layer polysilicon and exposed sections of control nodes were made of double-layer polysilicon and placed with an overlap of, for example, 4μ over the floating node. The exposed edge of the control node is, for example, 64μ long. The entire circuit was covered by a metal layer which was provided with an opening, an exposure window located above the circuit. In this case the floating node was detected by a broadband operational transconductance amplifier (OTA, not shown), connected as a voltage follower. The voltage follower was connected with the floating node by a line of single-layer polysilicon passed over the substrate. In this version, the total capacitance of the floating node was found to be 380 fF.

A second version of the UV structures as employed in the present invention is illustrated in figure 3b, in plan view (I) and section (II) along line A-A¹. Here a floating node is made of double-layer polysilicon, and the exposed section of the power supply node or control node is made of single-layer polysilicon. The advantage of this is that the floating node is moved away from the substrate, which reduces both parasitic UV conductance and parasitic capacitance to ground. Instead, most of the parasitic capacitance will go to the control nodes, which constitute a capacitive divider. The floating node will therefore initially be located closer to its equilibrium voltage compared to the version in figure 3a and consequently give a shorter programming time. In order to give an impression of the dimensions, an exposure window was used with a width of 17μ. The floating node was detected by a single OTA, connected as a voltage follower. In this version an attempt was made to reduce the capacitance of the floating node to a minimum, viz. 76 fF.

A third version of the UV structures as employed in the present invention is illustrated in figure 3c, in plan view (I) and section (II) along line A-A'. Here a floating node was made of single-layer polysilicon, and the exposed section of the power supply nodes 1 or the control nodes 2 was made as a diffusion of the p-type to V_dd and diffusion of the n-type to ground. In principle the floating node thereby constituted the interconnected gates of two transistors, the p-transistor with both s-electrode and d- electrode connected to V_dd and the n-transistor with both s-electrode and d-electrode connected to ground. In this case the exposure window had a width of, for example, 16μ. In the same way as in the other versions the floating node was detected by an OTA and the total capacitance of the floating node was 104 fF. This version can be expected to give less variation in the stored voltage than the two other versions, since the UV structures are designed as transistor circuits and this is the part of a VLSI process which is easiest to control.

The accuracy of the voltage reference according to the present invention is in theory only limited by thermal noise. This is dependent on the capacitance of the floating node and is given by the formula

where V_N is the sine value of the noise in microvolts. After the programming of a voltage reference of this kind, conditions at the other terminals of the detector, e.g. the transistor, may affect the voltage of the floating node due to parasitic capacitances. In the illustrated versions of the voltage reference, a floating node is obtained with low total capacitance, which is desirable for reducing the programming time, but even though the parasitic capacitances are low, they need not be negligible in a given version. However, this will be the case for any design which employs a floating node technique.

Various applications of voltage reference according to the invention will now be described.

Example 1: Voltage addition

The problem with addition of voltages in analog networks is actually a problem associated with the generation of reference voltages. By using the voltage references according to the present invention a desired local reference can be generated at a very reasonable cost and the stored charge or voltage can be manipulated by capacitive coupling as described above. As illustrated in figure 4, two or more capacitors C_1f C₂ ... can be used as inputs to a UV structure 1a, 1b where a charge is stored. The capacitors can manipulate the stored charge independently of one another, i.e. the voltage of the floating node 2 will be a sum of the input voltages, scaled by the ratio of the input capacity and the total capacitance of the floating node.

Figure 4 shows an adder according to the invention based on a UV structure 1a, 1b with two input capacitors C,, C₂ of different sizes. The voltage of the floating node 2 was detected by a voltage follower 3 as illustrated in figure 4. Due to capacitive division a signal compression is obtained in this adder, i.e. the variation in the output voltage will constitute a fraction of the variation in the input voltage, a fact which can be advantageous in the case of circuits with a low, linear input range. Alternatively the input voltages could be outside the supply voltages and an output voltage would still be obtained which was within the operating range of the succeeding circuitry.

Example 2: Amplification with increased linear input range

The capacitive division inherent in a UV structure may be used to reduce the dynamic range of a signal. If this reduction is detected by the inputs of an amplifier, this will be the same as increasing the amplifier's linear input range by a factor proportional to the capacitive division, in figure 5a a voltage reference according to the present invention is illustrated with three coupling capacitors C₁ , C₂, C₃. The capacitor C₃ is double the size of C₂, which in turn is double the size of capacitor C The floating node 2 is connected to the input of an operational amplifier 6, in this case a transconductance amplifier. Instead of designing the amplifier as illustrated in figure 5a as a linear amplifier, it can also be designed as a differential amplifier and in this case there are employed as inputs two voltage references according to the present invention, each with its floating node. As shown in figure 5b, the amplifier is designed with three input capacitors C^ C₂, C₃; C₄, C₅, C₆ respectively, as input to each of the floating nodes 1a and 1b. The amplifier's linear input range is again increased by a factor proportional to the capacitive division, which is equivalent to reducing the amplifier's voltage gain by the same factor.

Example 3: Accurately determined amplification

If the analog differential amplifier illustrated in figure 5b is used in a feedback configuration, the capacitive division can be used to achieve the exact amplification desired, as shown in figure 6, where voltage references with the UV structures 1a, 1c and the UV structures 1b, 1d respectively are connected over respective floating nodes 2a, 2b to each of the inputs on the operational amplifier 6. A coupling capacitor C, is connected with the floating node 2a and a second coupling capacitor C₂ is provided in a feedback loop from the output on the operational amplifier 6 to the floating node 2b in the second voltage reference 1b, 1d. In this case the circuit's amplification constitutes the scaling factor between the coupling capacitors C,, C₂ when the combined capacitance of each of the floating nodes 2a, 2b has the same value.

Example 4: UV-programmable analog memory

When programming of a voltage reference according to the invention is performed, there will be a finite charge on the floating node and this charge can be manipulated by capacitive coupling, which can be used to produce an analog memory as illustrated in figure 7. Here the voltage reference with the two UV structures 1a, 1b is connected via the floating node 2 to the gate electrode on a field-effect transistor 3. A programming circuit 8 is connected with the floating node via a control node 4 and a coupling capacitor C₁ . The programming circuit comprises a p-channel field-effect transistor and an n-channel field-effect transistor respectively. The voltage over the coupling capacitor can be removed or compressed by voltage follower 5, described as a collapsing follower, whose reference input is connected to the floating node 2 and output to the control node 4.

Before the programming begins, the programming circuit 8 pulls the control node to either V_dd or ground. The coupling capacitor C₁₍ which in this case can also be described as a control capacitor, pulls charge from the rest of the floating node 2. The voltage swing of the floating node 2 is determined by capacitive division. When the voltage reference is exposed to ultraviolet light, the floating node will be charged or discharged towards its equilibrium point. After the programming there will be a voltage difference over the coupling capacitor C, , determined by the initial difference between the charge on the control node 4 and the floating node 2, together with the exposure time. A negative voltage on the control node during the programming, relative to the floating node's voltage, results in a programmed, positive voltage and vice versa. When the voltage over the coupling capacitor C₁ is compressed or collapsed, its charge will be distributed over the rest of the floating node, including the gate electrode on the detector, in this case the field-effect transistor 3. It should be noted that when the voltage follower 5 is operating, it will force the control node 4 to the same voltage as the floating node 2. This also solves the problem of the programming circuit 8 affecting the floating node 2 after the programming. The programming circuit must, of course, be switched off after exposure to UV light. The deviation in the voltage follower is scaled by capacitive division. In this case the preferred design of the UV structures was as illustrated in figure 3a, while as a UV light source a standard EPROM eraser with a centre wavelength of 254 nm was used.

When programming the analog memory according to the invention a stepwise programming set-up was employed. The control node 4 was placed either at V_dd or ground and the floating node 2 was charged with only a fraction of its dynamic range, controlled by the duration of the exposure to UV light. The programming circuit 8 was then switched off together with the UV light and the voltage follower 5 switched on. This required a programming time of only a fraction of the floating node's time constant. The programming algorithm in the method according to the invention consequently comprises steps for turning off the voltage follower's bias voltage, turning on the programming circuit, applying a predetermined programming pattern, turning on the ultraviolet light, waiting for a predetermined time interval, turning off said ultraviolet light, turning off said programming circuits and turning on the bias voltage of said voltage follower. The algorithm for programming can, of course, be placed in a loop for repeated programming.

programming step is described by the equation

1/ -IΛ/ -π(/7)~ fnjn- ) ■/ ^vfn(rή-^κvcπ ^~_f ^vfrK -1) (III) where V,,, is the voltage of the floating node, V,,, is the voltage of the control node and k the capacitive division of the control node signal. It should be noted that the differential link is not only exponential, but "non-lineariy exponential", which makes this equation difficult or even impossible to solve. If, however, the floating node's voltage swing is limited, even the exponential dependence can be ignored and the programming regarded as linear.

As the floating node moves away from the equilibrium point, the non-linearity will manifest itself and the programming steps will become smaller. This ensures that the analog memory according to the invention does not diverge due to deviation during repeated programming up and down.

As can be seen in figure 7 the analog memory has a single-terminated form. In some cases, e.g. where a differential pair is used as an input step to a synaptic connection circuit for the implementation of a neural network of the Hopfield type, it will be advantageous to use a differentially designed analog memory in order, amongst other things, to avoid asymmetries in the output current of the synaptic circuit. A differential design will also be able to reduce problems connected with direct voltage level and noise.

The voltage follower in the single-terminated analog memory in figure 7 made the memory self-referring. In a differential embodiment as illustrated in figure 8, self- reference is not necessary, since two control nodes 4a and 4b are used which are locked to the same voltage when programming is not taking place. The control nodes 4a, 4b are therefore connected respectively via the field-effect transistors 9a, 9b to ground, the control nodes 4a, 4b thus affecting the respective, connected, floating nodes 2a, 2b in common mode. The field-effect transistors 9a, 9b are controlled by a signal clamp_enable (cl_e). It can be seen in figure 8 that the control nodes 4a, 4b are again connected to the respective floating nodes via control capacitors or coupling capacitors C₁ and C₂ respectively, while the voltage references comprise the UV structures 1a, 1c and 1b, 1d respectively. The programming circuit which is connected to the control nodes 4a, 4b is not shown. The preferred UV structures in this case were those illustrated in fig. 3b. It should be noted that the differential analog memory designed as shown in fig. 8, has lower temperature sensitivity than the embodiment according to fig. 7.

With the voltage reference according to the present invention and the illustrated applications of this voltage reference it becomes possible to implement analog networks such as large-scale integrated circuits in such a manner that analog weights can be stored and calculated locally on the semi-conductor chip. Above all, the voltage reference and the applications thereof are envisaged employed in large analog, neural networks, which, when implemented on semi-conductor chips, means that a major part of the chip has to be dedicated to signal routing, usually because the representation of a differential signal requires two wires. If one part of the differential signal constitutes a voltage reference, according to the invention it can be generated locally, thus eliminating the need for a global reference with associated wiring requirements. It is particularly advantageous that the voltage reference according to the invention can be generated by means of standard CMOS technology. As mentioned above, the principle of this technology is illustrated by the embodiments in figures 3a-3c, and it can be seen that each and every one of these embodiments implements a voltage reference with two UV conductors connected via a floating node. A person skilled in the art will understand that, when used in the application examples, the CMOS implementation of the voltage reference can be selected from what is suitable to the purpose of the application, e.g. the voltage reference's dimensions, the floating node's capacitance or the programming time.

Claims

1. An analog, UV-light programmable voltage reference, wherein the voltage reference is implemented in CMOS technology and wherein the programming includes exposing UV-structures to ultraviolet light, characterized by the voltage reference comprising a first and a second UV-structure respectively provided between each supply line and a floating node connected to the gate electrode of a field-effect transistor for detection of the voltage of said floating node, said floating node's voltage being stabilized at a value determined by the relation between the voltages of the first and the second UV- structure when these are exposed to ultraviolet light, the capacitance of said floating node being given by the sum of the capacitances of the UV-structures, the capacitance of the gate electrode and possible parasitic capacitances.

2. A voltage reference according to claim 1 , characterized by that the UV-structure comprises a dielectric connected across the terminals of a coupling capacitor, said dielectric becoming conducting upon exposure to ultraviolet light.

3. A voltage reference according to claim 2, characterized by the dielectric being silicon dioxide.

4. A voltage reference according to claim 1 , characterized by the parasitic capacitance being represented by a capacitor connected between the floating node and earth.

5. A voltage reference according to claim 1 , characterized by the field-effect transistor, whose gate electrode is connected with the floating node, forming a component of circuitry like an analog multiplier or an operational amplifier.

6. An analog voltage adder, comprising an analog voltage reference according to claim 1, characterized by at least two capacitors being provided as inputs to the voltage reference and the floating node being connected with the positive input of a voltage follower for detection of the voltage of said floating node, said voltage of said floating node being the sum of the capacitor voltages, scaled by the quotient between the combined capacitance of the capacitors and the capacitance of the floating node.

7. An analog amplifier with extended linear input range, comprising an analog voltage reference according to claim 1 , characterized by providing one ore more coupling capacitors as input to the voltage reference and by the floating node being connected with the positive input of an operational amplifier for detection of the voltage of the floating node, the capacitive voltage division in the voltage reference constituting a factor proportional with the increase of the linear input range of the operational amplifier.

8. An analog amplifier with extended linear input range, comprising a first and a second analog voltage reference according to claim 1 , characterized by one or more coupling capacitors respectively being provided as input to the first and second voltage reference respectively, and each of the floating nodes being connected with respectively the first and second input of an operational amplifier for detection of the voltages of the floating nodes.

9. An analog amplifier according to claim 7 or claim 8, characterized by the operational amplifier being a linear amplifier.

10. An analog amplifier according to claim 7 or 8, characterized by the operational amplifier being a differential amplifier.

11. An analog amplifier with accurately determined amplification, comprising a first and a second analog voltage reference according to claim 1 , characterized by a coupling capacitor being provided as input to the first and second voltage reference respectively, each of the floating nodes being connected with a respective input of an operational amplifier and one of the coupling capacitor being provided in a feedback loop between the output of said operational amplifier and an input of the same, such that the amplification said operational amplifier being equal to the scaling factor between the coupling capacitor which forms the input of the voltage references, given that the combined capacitance of each of said floating nodes has the same value.

12. A UV-light programmable analog memory comprising an analog voltage reference according to claim 1 , characterized by the floating node of the voltage reference being connected with the output of a programming circuit via a control capacitor, a voltage follower being connected in parallell over the terminals of said control capacitor, the reference input of said voltage follower being connected with the said floating node and its output with said control capacitor over a control node, such said control node attaining the same voltage as the floating node when the voltage follower is driven.

13. An analog memory according to claim 12, characterized by the programming circuit being an operational amplifier.

14. An analog memory according to claim 12, characterized by the programming circuit being logic circuitry.

15. A method of programming an analog memory according to claim 12, using ultraviolet light, characterized by the method comprising steps for turning off the bias voltage of the voltage follower, turning on the programming circuit, applying a predetermined programming pattern, turning on the ultraviolet light, waiting for a predetermined time interval, turning off said ultraviolet light, turning off said programming circuits and turning on the bias voltage of said voltage follower.

16. A method of programming according to claim 15, characterized by the programming taking place stepwise in either negative or positive programming steps.

17. A method of programming according to claim 16, characterized by using a standard EPROM eraser with a center wavelength of 254 nm as UV-light source.

18. A method of programming according to claim 17, characterized by the control node being connected to the supply voltage for the voltage reference or to earth, and charging the floating node with only a fraction of its dynamic capacitance range, the charging being controlled by the length of the time interval of the exposure to ultraviolet light.