WO1990011615A1 - Transistor a semiconducteurs d'oxyde metallique a grille de tranchee - Google Patents

Transistor a semiconducteurs d'oxyde metallique a grille de tranchee Download PDF

Info

Publication number
WO1990011615A1
WO1990011615A1 PCT/US1990/000237 US9000237W WO9011615A1 WO 1990011615 A1 WO1990011615 A1 WO 1990011615A1 US 9000237 W US9000237 W US 9000237W WO 9011615 A1 WO9011615 A1 WO 9011615A1
Authority
WO
WIPO (PCT)
Prior art keywords
trench
recited
transistor
insulating layer
source
Prior art date
Application number
PCT/US1990/000237
Other languages
English (en)
Inventor
Allen L. Solomon
Original Assignee
Grumman Aerospace Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Grumman Aerospace Corporation filed Critical Grumman Aerospace Corporation
Publication of WO1990011615A1 publication Critical patent/WO1990011615A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Definitions

  • the present invention finds application in connection with thin silicon plates or wafers formed to support a multiplicity of monolithically integrated data processor circuits. More particularly, the invention is directed to the production of circuits formed on silicon wafers for interfacing devices such as infrared detector elements to a processing network that amplifies, stores and interprets detected infrared frequency signals.
  • the infrared spectrum covers a range of wavelengths longer than the visible wavelengths, but shorter than microwave wavelengths. Visible wavelengths are generally regarded as between 0.4 and 0.75 micrometers. The infrared wavelengths extend from 0.75 micrometers to 1 millimeter. The function of infrared detectors is to respond to the energy of a wavelength within some particular portion of the infrared region.
  • Heated objects generate radiant energy having characteristic wavelengths within the infrared spectrum.
  • Many current infrared image detection systems incorporate arrays with large numbers of discrete, highly sensitive detector elements, the electrical outputs of which are connected to processing circuitry. By analyzing the pattern and sequence of detector element excitation, the processing circuitry can identify and track sources of infrared radiation. Though the theoretical performance of such contemporary systems is satisfactory for many applications, it is difficult to construct structures that adequately interface large numbers of detector elements with associated circuitry in a practical and reliable manner.
  • Contemporary arrays of detectors may be sized to include 256 detector elements on a side, or a total of 65, 536 detectors, the size of each square detector being approximately 0.009 centimeters on a side, with 0.00116 centimeters spacing between detectors . Such a subarray would therefore be 2.601 centimeters on a side . Interconnection of such a subarray to processing circuitry would require connecting each of the 65, 536 detectors to processing circuitry within a square, a l ittle more than one inch on a side. Each subarray may, in turn , be joined to other subarrays to form an array that connects to 25 , 000 , 000 detectors or more. As would be expected considerable difficulties are presented in electricl ly connecting the detector elements to associated circuitry, and laying out the circuitry in a minimal area . The problems of forming processing circuitry in such a dense environment require minimization of the surface area used for the circuitry.
  • the outputs of the detector elements typical ly undergo a series of processing steps in order to permit derivation of the informational content of the detector output sign al .
  • the more fundamental processing steps such as preamplification, tuned band pass filtering , clutter and background rejection, multiplexing and fixed noise pattern suppression, are preferably done at a location adjacent the detector array focal plane .
  • on-focal plane, or up-front signal processing reductions in size , power and cost of the main processor may be achieved.
  • on-focal plane signal processing helps alleviate performance, reliability and economic problems associated with the construction of millions of closely spaced conductors connecting each detector element to the signal processing network.
  • 1/f noise can be the principal noise component at low frequencies of operation, it is highly desirable that circuits operating within such frequencies be constructed in such a manner as to decrease 1/f noise to an acceptably low level.
  • the preamplifier transistor is a field effect device
  • Reduction of 1/f noise in the preamplifier, where the preamplifier transistor is a field effect device, is conventionally obtained by increasing the area of the channel region under the gate. This large area over the semiconductor substrate surface results in a decrease in circuit component density or decreased circuit component miniaturization.
  • the channel region of a metal-oxide-semiconductor (MOS) field effect transistor is formed in a trench in the semiconductor. The transistor then occupies far less semiconductor substrate surface and so enables a high component density circuit to be obtained.
  • MOS metal-oxide-semiconductor
  • a process for forming a trench gate metal oxide semiconductor transistor, and the resulting structure are disclosed.
  • the transistor gate region is formed in a trench in the semiconductor substrate. Regions adjacent the upper surface of the trench are doped to form source and drain regions.
  • a layer of insulator is applied to the surface of the trench.
  • a conductive layer is applied on the surface of the trench upon the insulating layer to complete the formation of an insulated gate.
  • the source and drain regions are therefore separated by the trench and the gate region is separated from the source and drain regions by the insulating layer lining the trench surface.
  • the trench can be formed by reactive ion etching and the insulating layers formed by thermally oxidizing the silicon substrate exposed by the trench.
  • Gate and source regions are formed by diffusing dopants into the substrate adjacent upper surfaces of the trench.
  • the conductive layer can be formed by vapor deposition of a doped polycrystalline silicon layer on the surface of the trench above the insulating layer.
  • the substrate is formed of p-doped silicon, and the gate and drain regions are formed of degenerately n-doped regions.
  • the conductive layer, which forms the transistor gate may be formed of a metal, or of degenerately doped polysilicon.
  • the insulating layer may be formed to be comprised of silicon dioxide.
  • the trench is formed up to approximately 10 to 20 microns deep, 2 to 3 microns wide and up to 10 to 20 microns wide.
  • the trench may be completely filled with the conductive material, an insulator material, or left open and simply lined with the layer of conductive material.
  • Figure 1 is a cross-sectional view of a contemporary MOS transistor structure
  • Figure 2 is a cross-sectional view of a transistor formed in accordance with the present invention.
  • FIG. 3 is a top perspective view of the transistor illustrated at Figure 2.
  • a similar trench gate embodiment can include a p-MOS transistor, an n or p junction field effect transistor (JFET) as well as the n-MOS transistor described here.
  • JFET junction field effect transistor
  • integrated circuit processor channels may be used in on-focal-plane signal processors.
  • Each detector element in the detector array may be connected to a preamplifier, such as a CMOS preamplifier, in an analog processor circuit.
  • CMOS preamplifier Low preamplifier noise is essential to prevent degradation of detector sensitivity. Since the preamplifiers are operated at low frequency, a principal source of noise is flicker or 1/f noise. The l/f noise is inversely proportional to the area of the channel or gate regions of an MOS transistor, as expressed in the following equation:
  • K a constant
  • C characteristic capacitance of the oxide layer
  • w the width of the gate
  • L the length of the gate. See: R. Gregorian and G.C. Temes, Analog MOS Integrated Circuits For Signal Processing, pp. 98, 99, John Wiley & Sons, N.Y., N.Y. (1986)
  • a large area gate region in a MOS transistor will produce a low 1/f noise component.
  • such a structure requires a large amount of semiconductor surface area. This makes it difficult to obtain a high density of such integrated circuit functions.
  • the present invention is directed to a structure and process for enhancing the area of the gate region without enhancing the semiconductor surface area.
  • the MOS transistor gate region may be regarded as a capacitor, which is formed by a metal oxide sem conductor cross-section.
  • Large area capacitors that preserve semiconductor surface are obtained in bulk silicon by using the walls of trenches, grooves or holes, which are cut in silicon, for example, by plasma or reactive ion etching.
  • gate region area may be enhanced by using the depth of the trench to enlarge the electrode channel area without the need to use a large amount of the semiconductor surface.
  • the present invention recognizes the capacitive characteristics of the MOS transistor gate region and applies particular trench forming techniques to the construction of the MOS transistor. In such a manner the MOS transistor gate channel area or gate channel region, is enhanced, mitigating 1/f noise, without the need to use large amounts of the semiconductor surface.
  • FIG. 1 illustrates an n-MOS transistor constructed in accordance with conventional techniques.
  • MOS transistor 11 is formed of an n-doped source region 21 and an n-doped drain region 23 formed in p-doped silicon 20.
  • the source and drain regions are bridged by an insulating layer, e.g. insulating layer 25, which may be formed of material such as silicon dioxide ( Si0 2 ) or silicon nitride.
  • a conductive gate 27 is disposed on the upper surface of the insulator 25.
  • the gate 27 is typically formed of metal or doped polysilicon.
  • the characteristic 1/f noise is related to the width and length of the gate area intermediate to the source and drain.
  • the length of the gate area labeled L
  • the width of the gate area is orthogonal to the plane of the drawing.
  • 1/f noise is reduced, though the maximum speed at which the circuit will efficiently operate is reduced.
  • the present invention is directed to a construction and technique wherein the gate area is enhanced without the need to appropriate greater surface area of the semiconductor wafer.
  • Figure 2 illustrates one embodiment of the present invention.
  • MOS transistor 13 comprises an n-doped source region 21, and an n-doped drain region 23, both formed in p-doped silicon 20.
  • a trench 31 is formed in the silicon substrate.
  • the trench may be formed by any of a variety of techniques, such a ⁇ reactive ion etching.
  • An insulating layer 33 is disposed on the vertical and bottom surface of the trench 31.
  • the insulating layer 33 is a thin film of silicon dioxide formed by thermal oxidation of the silicon.
  • a conductive film 35 which serves as the gate, is then disposed on the upper surface of insulating layer 33.
  • the gate layer 35 may be formed of conductive material, such a ⁇ metal or of degenerately doped semiconductor material, e.g. polysilicon.
  • the trench can be filled with an insulator material such as Si0 2 or with a conductive material without the need for a conductive film liner.
  • Electrodes 37, 39 may be formed on the upper exposed surfaces of source 21 and drain 23, respectively. Where the insulating layer 33 extends above the surfaces of source 21 and drain 23, the Si0 2 may be etched by any of a number of contemporary techniques to facilitate the formation of the electrodes. An additional electrode (not shown) may be formed to facilitate contact with the gate layer 35.
  • trench 31 is formed to be up to approximately 10 to 20 microns deep and 2 to 3 microns wide.
  • the length of the trench (orthogonal to the plane of Figure 1) is up to the range of 10 to 20 microns.
  • the particular dimensions may be selected in accordance with the desired noise characteristics and speed of the transistor, and the available surface area.
  • Figure 3 illustrates the arrangement of source, gate, and drain electrodes on the semiconductor substrate surface. A filled trench is depicted.
  • the gate would be connected to a dedicated detector element and the drain to a storage capacitor which may be selectively interrogated by the further processing circuitry (not shown).
  • the source may be connected to a low level bias circuit, or alternatively may be sustained at a substantially zero level, as may be desired.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un procédé de formation d'un transistor à semiconducteurs d'oxyde métallique à grille de tranchée, et la structure ainsi obtenue. Ledit transistor est réalisé par formation d'une tranchée (31) dans le substrat (20) à semiconducteurs, lequel est utilisé pour construire la région de grille. Les régions adjacentes à la surface supérieure de la tranchée, sont dopées afin de former des régions de source et de drain (21, 23). On applique une couche d'isolant (33) le long de la surface de ladite tranchée, et on applique une couche conductrice (35), formant ladite grille, sur la surface de ladite tranchée, au-dessus de ladite couche d'isolation. Les régions de source et de drain (21, 23) sont par conséquent séparées par ladite tranchée (31), et ladite région de grille (35) est séparée desdites régions de source et de drain (21, 23) par ladite couche isolante (33) recouvrant la surface de la tranchée.
PCT/US1990/000237 1989-03-21 1990-01-09 Transistor a semiconducteurs d'oxyde metallique a grille de tranchee WO1990011615A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US32663489A 1989-03-21 1989-03-21
US326,634 1989-03-21

Publications (1)

Publication Number Publication Date
WO1990011615A1 true WO1990011615A1 (fr) 1990-10-04

Family

ID=23273054

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1990/000237 WO1990011615A1 (fr) 1989-03-21 1990-01-09 Transistor a semiconducteurs d'oxyde metallique a grille de tranchee

Country Status (2)

Country Link
CA (1) CA2007908A1 (fr)
WO (1) WO1990011615A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250450A (en) * 1991-04-08 1993-10-05 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2724165A1 (de) * 1976-05-29 1977-12-01 Tokyo Shibaura Electric Co Oberflaechen-feldeffekttransistorvorrichtung
JPS53149771A (en) * 1977-06-01 1978-12-27 Matsushita Electric Ind Co Ltd Mis-type semiconductor device and its manufacture
US4316203A (en) * 1978-05-29 1982-02-16 Fujitsu Limited Insulated gate field effect transistor
US4453305A (en) * 1981-07-31 1984-06-12 The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland Method for producing a MISFET
US4455740A (en) * 1979-12-07 1984-06-26 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a self-aligned U-MOS semiconductor device
US4462040A (en) * 1979-05-07 1984-07-24 International Business Machines Corporation Single electrode U-MOSFET random access memory
JPS59181045A (ja) * 1983-03-31 1984-10-15 Toshiba Corp 半導体装置
US4571513A (en) * 1982-06-21 1986-02-18 Eaton Corporation Lateral bidirectional dual notch shielded FET
US4767722A (en) * 1986-03-24 1988-08-30 Siliconix Incorporated Method for making planar vertical channel DMOS structures

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2724165A1 (de) * 1976-05-29 1977-12-01 Tokyo Shibaura Electric Co Oberflaechen-feldeffekttransistorvorrichtung
JPS53149771A (en) * 1977-06-01 1978-12-27 Matsushita Electric Ind Co Ltd Mis-type semiconductor device and its manufacture
US4316203A (en) * 1978-05-29 1982-02-16 Fujitsu Limited Insulated gate field effect transistor
US4462040A (en) * 1979-05-07 1984-07-24 International Business Machines Corporation Single electrode U-MOSFET random access memory
US4455740A (en) * 1979-12-07 1984-06-26 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a self-aligned U-MOS semiconductor device
US4453305A (en) * 1981-07-31 1984-06-12 The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland Method for producing a MISFET
US4571513A (en) * 1982-06-21 1986-02-18 Eaton Corporation Lateral bidirectional dual notch shielded FET
JPS59181045A (ja) * 1983-03-31 1984-10-15 Toshiba Corp 半導体装置
US4767722A (en) * 1986-03-24 1988-08-30 Siliconix Incorporated Method for making planar vertical channel DMOS structures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250450A (en) * 1991-04-08 1993-10-05 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance

Also Published As

Publication number Publication date
CA2007908A1 (fr) 1990-09-21

Similar Documents

Publication Publication Date Title
US5108938A (en) Method of making a trench gate complimentary metal oxide semiconductor transistor
US6392282B1 (en) BiCMOS-integrated photodetecting semiconductor device having an avalanche photodiode
EP1553633A2 (fr) Détecteur infrarouge et son procédé de fabrication
US7692258B2 (en) Photosensitive device
US7928511B2 (en) Semiconductor device and method for manufacturing semiconductor device
US5726485A (en) Capacitor for a semiconductor device
US20110024608A1 (en) Avalanche impact ionization amplification devices
US5010025A (en) Method of making trench JFET integrated circuit elements
US7368760B2 (en) Low parasitic capacitance Schottky diode
US5053350A (en) Method of making trench MOSFET capacitor cell for analog signal processing
KR20190108470A (ko) 수광 장치, 및 수광 장치의 제조 방법
US5122851A (en) Trench JFET integrated circuit elements
US5712498A (en) Charge modulation device
US5716880A (en) Method for forming vertical polysilicon diode compatible with CMOS/BICMOS formation
US4499654A (en) Method for fabricating semiconductor photodetector
US6285052B1 (en) Integrated capacitor
US5278430A (en) Complementary semiconductor device using diamond thin film and the method of manufacturing this device
US6489658B2 (en) MOS-transistor for a photo cell
WO1990011615A1 (fr) Transistor a semiconducteurs d'oxyde metallique a grille de tranchee
CA2009067C (fr) Transistor metal-oxyde-semiconducteur complementaire a grille en tranchee
US4803363A (en) Infrared detector with integral feedback capacitance
US4859851A (en) Thermal-radiation imaging devices and systems, and the manufacture of such imaging devices
JP4083553B2 (ja) 光半導体装置
JP2017157755A (ja) 光検出器及び光検出器の製造方法
WO1990011619A1 (fr) Mosfet a une seule tranchee-cellule de condensateur pour le traitement de signaux analogiques

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB IT LU NL SE