WO1990005995A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO1990005995A1
WO1990005995A1 PCT/JP1989/001180 JP8901180W WO9005995A1 WO 1990005995 A1 WO1990005995 A1 WO 1990005995A1 JP 8901180 W JP8901180 W JP 8901180W WO 9005995 A1 WO9005995 A1 WO 9005995A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
conductor
resistance element
diffusion region
resistance
Prior art date
Application number
PCT/JP1989/001180
Other languages
French (fr)
Japanese (ja)
Inventor
Yasunari Furuya
Kazuko Moriya
Original Assignee
Seiko Epson Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP1290499A external-priority patent/JP2864576B2/en
Application filed by Seiko Epson Corporation filed Critical Seiko Epson Corporation
Priority to GB9015141A priority Critical patent/GB2232530B/en
Publication of WO1990005995A1 publication Critical patent/WO1990005995A1/en
Priority to KR1019900701560A priority patent/KR900702572A/en

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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802—Resistors only
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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Definitions

  • the present invention relates to a high-precision resistive element structure in a semiconductor device.
  • FIG. 1 a structural diagram in which a resistance element, particularly a high resistance element, is formed on a semiconductor substrate by using polycrystalline silicon is shown in FIG.
  • Polycrystalline silicon 2 is formed by sandwiching an insulating film 9 as an oxide film on a semiconductor substrate 3 and connected to aluminum electrode wires 4 and 6 via contacts 5 and 7.
  • the upper part of the polycrystalline silicon 2 had a strong insulating film 1 °, and the upper part thereof had only an oxide protection film without a signal line or any signal line made of aluminum wiring.
  • FIG. 2 shows a structural diagram in which a resistance element conventionally formed of a low-concentration diffusion layer or a diffusion layer formed by ion implantation is formed on a semiconductor substrate.
  • Diffusion resistor 12 formed on the surface of semiconductor substrate 13 is connected to aluminum electrode wires 14 and 16 via contacts 15 and 17.
  • Above the diffusion resistor there is an insulating film which is an oxide film.
  • the upper portion of the insulating film has another signal wiring made of polycrystalline silicon / aluminum, or has no signal wiring and has only an oxide protective film.
  • FIG. 1 shows a structural diagram in which a resistance element conventionally formed of a low-concentration diffusion layer or a diffusion layer formed by ion implantation.
  • a depletion layer is formed on the surface of the resistive element due to the electric charge accumulated at the interface between the diffusion surface of the resistive element and the oxide film and the electric field from the signal wiring passing over the resistive element. .
  • This depletion layer works to increase the resistance value of the resistance element. If the thickness force of the depletion layer becomes a level that cannot be ignored with respect to the diffusion depth of the resistance element, the value of the resistance element will fluctuate greatly. With a diffusion depth of 1 mm or less formed by ion implantation, a sheet resistance of 9 ⁇ or more In children, this phenomenon is remarkable, with resistance values ranging from a few percent to several. %.
  • the configuration of the semiconductor device of the present invention is such that a conductor having a lower resistance than the resistance element is formed at least above the diffusion resistance formed by low diffusion or ion implantation or the resistance element formed of polysilicon.
  • the feature is to keep the low resistance conductor at a constant potential with respect to the power supply
  • the cause of the variation in resistance value Therefore, since the electromagnetic field from the impurity ions and adjacent signal lines is cut off, the low diffusion resistance and the polycrystalline silicon resistance can be kept stable.
  • FIG. 1 is a structural view of a conventional polycrystalline silicon resistance element.
  • FIG. 2 is a structural diagram of a conventional diffusion resistance element.
  • FIG. 3 is a structural view of a resistive element made of polycrystalline silicon according to the present invention.
  • FIG. 4 is a structural view of the diffusion resistance element of the present invention.
  • FIG. 5 is a structural diagram of the polycrystalline silicon resistor of the present invention formed on LOCOS.
  • FIG. 6 is a structural diagram of a polycrystalline silicon resistor according to the present invention when a stopper is provided below L 0 C 0 S.
  • FIG. 7 (a) is a plan view of the polycrystalline silicon resistor of the present invention in which the periphery is surrounded by the same material as the resistance element, and FIG. 7 (b) is a cross-sectional view thereof.
  • Fig. 8 shows the polycrystalline silicon resistor of the present invention in which the upper and lower layers of the resistive element are covered with conductors.
  • Fig. 9 (a) shows the polycrystalline silicon resistor of the present invention in which the potential of the conductor covering the resistive element is set to VDD.
  • Fig. 9 (b) is a diagram showing an example of a circuit when the potential of a conductor is used as the output of a transistor.
  • FIG. 1 ⁇ is an application circuit diagram of the resistive element according to the present invention when the output voltage is divided by the resistor in the middle stage.
  • FIG. 11 is an application circuit diagram of the resistance element according to the present invention when the output voltage is divided by a plurality of resistance elements.
  • FIG. 12 is a cross-sectional view of a polycrystalline silicon resistor of the present invention using two-layer metal wiring.
  • FIG. 13 (a) is a cross-sectional view of a diffusion resistor according to the present invention in which the periphery is covered with the same material as the resistor, and
  • FIG. 13 (b) is a cross-sectional view thereof.
  • FIG. 14 is a cross-sectional view of the diffused resistance element of the present invention in which the upper and lower layers of the resistance are covered with shield conductors.
  • FIG. 15 (a) is a plan view of the diffusion resistance element of the present invention in which the periphery is surrounded by a stopper
  • FIG. 15 (b) is a cross-sectional view thereof.
  • FIG. 16 is an equivalent circuit diagram of a field base using the resistive element of the present invention covered with a shield conductor as a delay line of a high-frequency circuit.
  • FIG. 3 shows the basic configuration of the present invention.
  • FIG. 3 is a structural diagram of a resistance element made of polycrystalline silicon.
  • Reference numeral 2 denotes a resistance element using polycrystalline silicon, and both ends thereof are led out to electrodes 4 and 6 via contacts 5 and 7, respectively.
  • the material of the electrodes 4 and 6 is aluminum.
  • a low-resistance conductor 1 is formed so as to cover more than half of the polycrystalline silicon by sandwiching the acid ibE on the upper part of the polycrystalline silicon 2 and a constant potential (low power supply potential VSS 8 or high power supply potential VDD). , Or its intermediate potential).
  • the oxide film in the present invention intends an insulating film.
  • the resistance element having such a structure has the following advantages. First, it is possible to prevent noise from a signal line disposed above the low resistance conductor 1 and the outside world from jumping into the resistance element. In other words, the electric and magnetic noise transmitted from the stray capacitance, stray inductance, etc. existing around the resistance element is removed by the electrostatic shielding effect of low resistance conduction. Therefore, the resistance element is used as a stable and high-precision element without a change in current-to-current characteristic (that is, resistance value) due to noise even during operation of the semiconductor device.
  • the low-resistance conductor can block light radiated from outside to the resistance element. Since a high-resistance polycrystalline silicon resistor is a semiconductor, it changes its electron energy by light energy such as visible light, infrared light, and ultraviolet light, and consequently changes its characteristic force as a resistive element. So, with a physical protection material called a low resistance conductor By covering, the above-mentioned problems are eliminated and a stable resistance element is obtained.
  • the advantage of preventing the resistance element characteristics from fluctuating due to the influence of the outside world has been provided.However, on the contrary, the noise point generated by the resistance element itself, the electric field and the magnetic field do not reach the surroundings, and the point j is there. Particularly in a circuit that operates at high speed, the charge flowing through the resistor element also fluctuates rapidly, increasing thermal noise, and unnecessary radiation emitted from this resistor element cannot be ignored. It is.
  • the material of the resistor may be P-type polycrystalline silicon, N-type polycrystalline silicon, L which is not implanted, or high-resistance polycrystalline silicon which is reduced in the amount of ion implantation (referred to as a high-resistor), or
  • the present invention has the same effect not only for silicon but also for other semiconductors and semiconductor-metal compounds.
  • Aluminum, tungsten, and molybdenum are commonly used as materials for the low-resistance conductor, but polycrystalline silicon is also effective.
  • FIG. 5 is a diagram in which a polycrystalline silicon resistor of the present invention is formed on a selective oxide film (hereinafter referred to as L0C0S) formed on the surface of a semiconductor substrate.
  • L0 COS 53 is formed on a substrate 55, and a polycrystalline silicon resistor 50 is formed thereon via an oxide film 52.
  • the oxide film 56 is sandwiched between the aluminum conductor 51 and the resistor 5 () is covered, and the aluminum conductor 51 is connected to the power supply VSS 54.
  • FIG. 6 is a diagram of an application example in which a high-concentration diffusion region is provided immediately below LOCOS. A high diffusion region (stopper) is provided under LOCOS to increase the breakdown voltage of the transistor. Since FIG.
  • FIG. 6 shows the P channel region, a dark N + stopper 65 is provided, and a VDD potential is applied from the substrate 66.
  • a polycrystalline silicon resistor 60 is formed on the LOCOS 64, and the upper portion thereof is covered with an aluminum conductor 61, and its potential is set to VDD67. With this configuration, the resistor 60 is vertically dissociated by the aluminum conductor 61 kept at VDD and the N + stopper 65. Therefore, there is a double effect that the characteristics as a resistive element are stabilized and the withstand voltage of the transistor is increased.
  • the N-channel region below 0:03? — The same effect can be obtained by providing a P + stopper on the well and applying VSS to this P + strobe, aluminum and the aluminum conductor.
  • FIG. 7 (a) is a plan view of an example in which the sides of the resistor are shielded with the same material as the resistor
  • FIG. 7 (b) is a cross-sectional view taken along line AB.
  • polycrystalline silicon 77 is arranged around the polycrystalline silicon resistance element 70, an aluminum conductor 75 connected to VSS is formed to cover them all, and the anode conductor 75 and the polycrystalline silicon 77 are contacted as far as possible. , 78 are provided.
  • reference numerals 73 and 74 denote aluminum electrode wires in the same layer as the aluminum conductor 75 connected to the polycrystalline silicon 70 via the contacts 71 and 72.
  • FIG. 8 is a structural diagram in which a shield layer is formed below a resistive element.
  • An oxide film 86 is sandwiched on the semiconductor substrate 83 to form a conductor 82, and the potential is set to VSS 85.
  • This conductor 82 is usually used for the first polycrystalline silicon force.
  • the oxide film is sandwiched, and the resistance element 80 is formed by the second polycrystalline silicon.
  • the film is sandwiched and covers the top of the aluminum conductor 81 force-resistive element 80 which is energized to VSS 84.
  • the first polycrystalline silicon has a higher resistance than aluminum, it goes without saying that the greater the number of contacts for connecting the first polycrystalline silicon to the VSS power supply, the greater the effect becomes.
  • the potential of each part of the polycrystalline silicon conductor is made as uniform as possible by arranging at least two power supply contacts at both ends of the polycrystalline silicon opposed to each other with the resistance element interposed therebetween. By doing so, the effect on the resistance element is further improved.
  • FIG. 9 (a) is a structural diagram of the resistive element in which the potential of the low-resistance conductor is set to VDD 90 in the structure of FIG. From the point of view of the shielding effect, it does not change with VSS or VDD.
  • FIG. 9 (b) is a side view of the case where the potential applied to the low-resistance conductor is extracted from the output voltage of the transistor and is set to an intermediate potential between VDD and VSS.
  • MO S transistor 91, 92, 93, each transistor driving ability mosquito? ⁇ , ⁇ ⁇ 2, S N1, ⁇ ⁇ 2, signal 96 when each of the transistor threshold V TP1, V T P2, VTNI , and V TN 2 The potential of
  • FIG. 10 is an application circuit diagram of a resistance element with a middle tap. A circuit that divides a resistor into two and takes out from the intermediate point through an output operational amplifier 1 • 7. The present invention is applied to a resistor element that is accurately divided into two.
  • a polycrystalline silicon resistor 101 connected to VDD100 and VSS 105 via contacts 102 and 1 ⁇ 4 has a
  • Output V. 108 outputs VDD / 2 exactly.
  • FIG. 11 is an application circuit diagram of a field stand using two resistive elements for the same purpose as in FIG.
  • the signal 116 connecting the two is input to the ⁇ amplifier 117, and the potential of the signal 116 is output as it is 3 ⁇ 4EV 0 11
  • the structure of the resistors 115 and 116 must be exactly the same, and In order to prevent the effects of noise and electromagnetic fields, cover the resistors 115 and 116 with the upper aluminum conductors 113 and 112, and give the same potential 111. By doing so, a stable voltage is output to Vo.
  • VDDZ3 and VDDZ4 can be easily obtained by connecting three or four in series.
  • the structure according to the present invention using the polycrystalline polysilicon resistor can be applied to a semiconductor device having two layers or three layers, of course, the force ⁇ exemplified in the case of one layer of aluminum wiring.
  • FIG. 12 is a structural diagram of two or more aluminum layers.
  • a polycrystalline silicon resistor 120 sandwiching an oxide film 122 on the substrate 121, and operates as a resistance element through the electrodes 124 and 125.
  • the electrodes 124 and 125 are the first aluminum wiring layers.
  • a second aluminum wiring layer 127 is provided across the oxide films 123 and 126, covers the entire upper portion of the polycrystalline silicon resistor 120, and is supplied with a VSS potential.
  • the distance between the resistive element 120 and the shield material 127 is farther than in the case of aluminum single-layer wiring, so the shielding effect is somewhat reduced. Since it is not necessary to do so, the design becomes easier.
  • the stabilization of the resistance and the technology of the L and L are achieved by the shield effect beam of the present invention. Can be applied.
  • FIG. 4 is a basic structural diagram when the present invention is applied to a diffusion resistor.
  • an upper portion of at least half of the plane of the diffusion resistance is covered with an aluminum conductor 11 with an oxide film interposed therebetween, and a VSS potential 18 is applied.
  • the aluminum conductor 11 becomes a shielding material, and shields electromagnetic noise, light, ions, and dirt from the outside with electric force and physically, so that the diffusion resistance is stabilized and the accuracy is improved.
  • Diffusion resistance material is formed in the N-substrate ⁇ —Pell resistance, ⁇ —Pell formed in the substrate ⁇ —Low diffusion resistance such as resistance, or formed by ion implantation ⁇ + resistance, ⁇ + High as resistance?
  • the present invention can be applied to diffusion resistance and the like.
  • a metal-semiconductor compound, a superconducting substance, and the like can be applied in addition to aluminum and polycrystalline silicon.
  • FIG. 13 is a structural diagram when the periphery of the diffusion resistor is covered with the same diffusion material.
  • FIG. 13 (a) is a plan view
  • FIG. 13 (b) is a cross-sectional view taken along line AB.
  • Diffusion resistance 130 force ⁇ formed in the shallow part of semiconductor substrate 139
  • the same diffusion material 137 is formed around (in the horizontal direction)
  • aluminum conductor 135 covering the upper part of diffusion resistance 130 with an oxide film is The material 137 is contacted with the material 137 via the contacts 136 and 138, and the potential is applied to the power supply VSS.
  • the effect of shielding the electromagnetic field noise of the source / drain ⁇ or diffusion resistance of the surrounding transistors can be determined by the pad structure.
  • 133 and 134 are aluminum electrode wires of the same layer as 135 connected to the diffusion resistor 130 via the contacts 131 and 132.
  • FIG. 14 is a structural diagram in the case where a shield conductor is formed in a lower layer portion of a diffusion resistor.
  • P-base. Plate 143 has N + buried layer 142.
  • 144 and 145 are high impurity; N-type epitaxial layers, and potential is applied to VDD by contact 146.
  • Reference numeral 140 denotes a P + diffusion resistance, which sandwiches an oxide film 147 and has an upper portion covered with an aluminum conductor 141, and the potential of the aluminum conductor 141 is also V DD. Since the diffused resistance element with this structure is shielded from the top, bottom, left and right, the stability and accuracy as resistance are extremely high.
  • FIGS. 13 and 14 have a shielding effect in the lateral and downward directions of the resistance element, so that the transistor near the current path generated when the semiconductor integrated device is irradiated with light or a-line. This has a great effect of preventing the influence of the substrate current due to the switching.
  • FIG. 15 (a) is a plan view of the case where the periphery of the diffusion resistor is surrounded by a stopper
  • FIG. 15 (b) is a cross-sectional view taken along the line AB.
  • a P + stopper 157 is formed around an N-type diffused resistor 150 formed on the surface of the P-well 159 formed on the N-substrate, and a VSS potential is applied from the aluminum conductor 155 by the contacts 156 and 158.
  • This structure not only shields and prevents electromagnetic noise from surroundings, but also has a latch-up prevention effect.
  • a P-type diffusion resistor is formed on the N-substrate, and the surrounding area is surrounded by an N + stopper, and VDD is applied to the N + stopper and the aluminum conductor of the diffusion fan Lh, thereby again providing an electromagnetic field. It has the effect of noise shielding and latch-up prevention.
  • 153 and 154 are aluminum electrode wires in the same layer as the aluminum conductor, and are connected to the resistor 150 via the contacts 151 and 152.
  • the electrostatic shielding effect by covering the periphery of the diffused resistor with a conductor given a constant potential is similar to the case of a polycrystalline silicon resistor.
  • the potential may be the intermediary potential.
  • the surrounding area is covered with a conductor connected to a constant potential to reduce the resistance. This has the effect of increasing the stability of the device.
  • the present invention can be applied in the same manner as described above.
  • FIG. 16 is an equivalent circuit showing that the shield resistance of the present invention can be used as a delay line of a high-frequency circuit.
  • Capacitors 164 to 167 are always able to obtain a stable capacitance fox since they are surrounded by a conductor of constant potential around the resistor 160 to 163, and are also shielded Therefore, the stability of the resistance value is also good.
  • the signal is input from the resistance terminal on the V i side, and output from the resistance terminal on the V 0UT side.
  • the invention has a very wide range of applications.
  • the technique of covering the resistive element of the present invention with a shield conductor can be applied to covering the periphery of a capacitor, a transistor, and the like with a shield conductor, and can increase the capacitance and the stability of the transistor.
  • the present invention has an extremely wide range of applications because the stability and accuracy of a resistor are improved with a simple configuration in which the peripheral structure pattern of the resistor is slightly added using existing manufacturing processes.
  • Improving the stability and accuracy of a resistive element means that the absolute value of the resistive element, or the relative resistance ratio when multiple resistive elements are used, is less affected by the surrounding electromagnetic field noise. It is.
  • the surface (generally, an oxide film) potential of the resistance element is prevented from floating, it is less susceptible to ions and the like, and the aging of the resistance value can be prevented.
  • the electromagnetic field noise generated from the resistance element itself can be reduced.
  • high-precision high-resistance element power can be realized by low-concentration diffusion, the required area is reduced, and as a result, semiconductor integrated devices can be highly integrated.

Abstract

A semiconductor device in which a conductor is formed on at least a resistance element that is formed by diffusing impurities into a polycrystalline silicon or semiconductor substrate, said conductor having a resistance smaller than that of said resistance element and being maintained at a predetermined potential. Such a constitution of the invention makes it possible to prevent the entrance of impurity ions or noise from the neighboring signal lines or from external units, that cause a change in the resistance of the resistance element, since there is formed a conductor having a predetermined potential. Therefore, the resistance of the resistance element can be stably maintained.

Description

明 細  Details
技術分野 Technical field
本発明は半導体装置に於ける高精度な抵抗素子の構造に関する。  The present invention relates to a high-precision resistive element structure in a semiconductor device.
背景技術  Background art
従来、 多結晶シリコンで抵抗素子、 特に高抵抗素子を半導体基扳上に形成 した構造図を第 1図に示す。 半導体基板 3の上に酸化膜である絶縁膜 9をは さみ多結晶シリコン 2力く形成され、 コンタクト 5、 7を介してアルミニウム 電極線 4、 6と接続されている。 そして多結晶シリコン 2の上部には絶縁膜 1◦力くあり、 その上部はアルミニゥム配線による ί言号線又は何も信号線がな く酸化保護膜があるのみであつた。  Conventionally, a structural diagram in which a resistance element, particularly a high resistance element, is formed on a semiconductor substrate by using polycrystalline silicon is shown in FIG. Polycrystalline silicon 2 is formed by sandwiching an insulating film 9 as an oxide film on a semiconductor substrate 3 and connected to aluminum electrode wires 4 and 6 via contacts 5 and 7. The upper part of the polycrystalline silicon 2 had a strong insulating film 1 °, and the upper part thereof had only an oxide protection film without a signal line or any signal line made of aluminum wiring.
さらに、 従来低濃度の拡散層又はイオン打ち込みによる拡散層で形成され る抵抗素子を半導体基板上に形成した構造図を第 2図に示す。 半導体基板 1 3の表面部に形成された拡散抵抗 1 2はコンタクト 1 5、 1 7を介してアル ミニゥム電極線 1 4、 1 6と接続されている。 そして拡散抵抗の上部には酸 化膜である絶緣膜がありく その上部は多結晶シリコンゃアルミニゥムによる 他の信号配線が、 又は何も信号配線がなく酸化保護膜があるのみであった。 しかし、 第 2図に示す従来の構造では、 抵抗素子の拡散面と酸化膜の界面 に蓄積した電荷や抵抗素子上を通過する信号配線からの電界のために抵抗素 子表面に空乏層を生ずる。 この空乏層は抵抗素子の抵抗値を上昇させる方向 に働く。 この空乏層の厚み力《抵抗素子の拡散の深さに対して無視できない水 準になると、 抵抗素子の値を大きく変動させることになる。 イオン打ち込み で形成される 1〃以下の拡散深さでシート抵抗ら〜 9 Κ Ω 以上の抵抗素 子では、 この現象が顕著で、抵抗値が数％から数 1。％変動することがあつ た。 Further, FIG. 2 shows a structural diagram in which a resistance element conventionally formed of a low-concentration diffusion layer or a diffusion layer formed by ion implantation is formed on a semiconductor substrate. Diffusion resistor 12 formed on the surface of semiconductor substrate 13 is connected to aluminum electrode wires 14 and 16 via contacts 15 and 17. Above the diffusion resistor, there is an insulating film which is an oxide film. The upper portion of the insulating film has another signal wiring made of polycrystalline silicon / aluminum, or has no signal wiring and has only an oxide protective film. However, in the conventional structure shown in FIG. 2, a depletion layer is formed on the surface of the resistive element due to the electric charge accumulated at the interface between the diffusion surface of the resistive element and the oxide film and the electric field from the signal wiring passing over the resistive element. . This depletion layer works to increase the resistance value of the resistance element. If the thickness force of the depletion layer becomes a level that cannot be ignored with respect to the diffusion depth of the resistance element, the value of the resistance element will fluctuate greatly. With a diffusion depth of 1 mm or less formed by ion implantation, a sheet resistance of 9 Ω or more In children, this phenomenon is remarkable, with resistance values ranging from a few percent to several. %.
また同様に、第 1図に示すような構造に高抵抗多結晶シリコンを棚した 場台、酸 i Mで保護されているだけのため、 不純物イオン力多結晶シリコン 上に侵入した場合、 その電界により、 多結晶シリコンの抵抗値が大きく変動 することがあった。  Similarly, when the high resistance polycrystalline silicon is shelved in the structure shown in Fig. 1, it is only protected by the acid iM. As a result, the resistance of polycrystalline silicon sometimes fluctuated greatly.
又半導体素子は特 光に対してエネルギー準位が変化する為、半導体装 置に可視光、 赤外線、紫外線等が照射されると、抵抗値が変化してしまうと いう問題点を有していた。  In addition, since the energy level of a semiconductor device changes with respect to light, there is a problem that the resistance value changes when the semiconductor device is irradiated with visible light, infrared light, ultraviolet light, or the like. .
発明の開示  Disclosure of the invention
本発明の半導体装置の構成は、 低 拡散あるいは、 イオン打込みで形成 される拡散抵抗もしくは多結晶シリコンで形成される抵抗素子の少なくとも 上方に抵抗素子よりも低抵抗の導体を形成し、 こ^)低抵抗導体を電源に対し て、一定電位に保つことを特徵とする  The configuration of the semiconductor device of the present invention is such that a conductor having a lower resistance than the resistance element is formed at least above the diffusion resistance formed by low diffusion or ion implantation or the resistance element formed of polysilicon. The feature is to keep the low resistance conductor at a constant potential with respect to the power supply
本発明の上記構成によれば、 低1¾拡散あるいはイオン打込みで構成され る抵抗、又は高抵抗多結晶シリコンの少なくとも に一定電位に接続され た導体を形成することにより、 抵抗値の変動の原因となる、 不純物イオンや 近接信号線からの電磁界を遮断するので、 低 ^ ^拡散の抵抗、 多結晶シリコ ンカ抵抗値を安定に保つことができるのである。  According to the above configuration of the present invention, by forming a conductor connected to a constant potential at least in a resistor configured by low 1¾ diffusion or ion implantation, or high-resistance polycrystalline silicon, the cause of the variation in resistance value Therefore, since the electromagnetic field from the impurity ions and adjacent signal lines is cut off, the low diffusion resistance and the polycrystalline silicon resistance can be kept stable.
又、光が照射されることによる抵抗値の麵を防止することができる。  In addition, it is possible to prevent the resistance value from being increased due to light irradiation.
図面の簡単な説明—  BRIEF DESCRIPTION OF THE DRAWINGS—
第 1図は従来の多锆晶シリコンによる抵抗素子の構造図。  FIG. 1 is a structural view of a conventional polycrystalline silicon resistance element.
第 2図は従来の拡散抵抗素子の構造図。  FIG. 2 is a structural diagram of a conventional diffusion resistance element.
第 3図は本発明の多結晶'シリコンによる抵抗素子の構造図。  FIG. 3 is a structural view of a resistive element made of polycrystalline silicon according to the present invention.
第 4図は本発明の拡散抵抗素子の構造図。 ； 第 5図は LOCOS上に形成した本発明の多結晶シリコン抵抗の構造図。 第 6図は L 0 C 0 S下にストツバ一を設けた時の本発明の多結晶シリコン 抵抗の構造図。 FIG. 4 is a structural view of the diffusion resistance element of the present invention. ; FIG. 5 is a structural diagram of the polycrystalline silicon resistor of the present invention formed on LOCOS. FIG. 6 is a structural diagram of a polycrystalline silicon resistor according to the present invention when a stopper is provided below L 0 C 0 S.
第 7図 （a) は、 周辺を抵抗素子と同じ材料で囲んだ本発明の多結晶シリ コン抵抗の平面図、 第 7図 （b) はその断面図。  FIG. 7 (a) is a plan view of the polycrystalline silicon resistor of the present invention in which the periphery is surrounded by the same material as the resistance element, and FIG. 7 (b) is a cross-sectional view thereof.
第 8図は抵抗素子の上下層を導体で覆った本発明の多結晶シリコン抵抗の 第 9図 （a) は抵抗素子を覆う導体の電位を VDDにした、 本発明の多結 晶シリコン抵抗の構造図、 第 9図 （b) は導体の電位をトランジスタの出力 とした時の一回路例を示す図。  Fig. 8 shows the polycrystalline silicon resistor of the present invention in which the upper and lower layers of the resistive element are covered with conductors. Fig. 9 (a) shows the polycrystalline silicon resistor of the present invention in which the potential of the conductor covering the resistive element is set to VDD. Fig. 9 (b) is a diagram showing an example of a circuit when the potential of a conductor is used as the output of a transistor.
第 1◦図は中間夕ップで出力電圧を抵抗分割する時の本発明による抵抗素 子の応用回路図。  FIG. 1 ◦ is an application circuit diagram of the resistive element according to the present invention when the output voltage is divided by the resistor in the middle stage.
第 11図は、 複数の抵抗素子で出力電圧を抵抗分割する時の本発明による 抵抗素子の応用回路図。  FIG. 11 is an application circuit diagram of the resistance element according to the present invention when the output voltage is divided by a plurality of resistance elements.
第 12図は二層金属配線による本発明の多結晶シリコン抵抗の断面図。 第 13図 （a) 周辺を抵抗と同じ材料で覆った本発明による拡散抵抗の苹 面図、 第 13図 （b) はその断面図。  FIG. 12 is a cross-sectional view of a polycrystalline silicon resistor of the present invention using two-layer metal wiring. FIG. 13 (a) is a cross-sectional view of a diffusion resistor according to the present invention in which the periphery is covered with the same material as the resistor, and FIG. 13 (b) is a cross-sectional view thereof.
第 14図は抵抗の上下層をシールド導体で覆つた本発明の拡散抵抗素子の 断面図。  FIG. 14 is a cross-sectional view of the diffused resistance element of the present invention in which the upper and lower layers of the resistance are covered with shield conductors.
第 15図 （a) は周辺をストッパーで囲った本発明の拡散抵抗素子の平面 図、 第 15図 （b) はその断面図。  FIG. 15 (a) is a plan view of the diffusion resistance element of the present invention in which the periphery is surrounded by a stopper, and FIG. 15 (b) is a cross-sectional view thereof.
第 16図はシールド導体で覆われた本発明の抵抗素子を高周波回路のディ レイラインとして使用した場台の等価回路図。  FIG. 16 is an equivalent circuit diagram of a field base using the resistive element of the present invention covered with a shield conductor as a delay line of a high-frequency circuit.
発明を実施するため最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
本発明の実施例を図面に基づいて説明する。 第 3図は本発明の基本構成と なる多結晶シリコンによる抵抗素子の構造図である。 2は多結晶シリコンを 用いた抵抗素子で、 その両端はコンタクト 5、 7を経由して電極 4、 6へ引 き出されている。 電極 4、 6の材料はアルミニウムである。 そして多結晶シ リコン 2の上部に酸 ibEをはさみ、 多锆晶シリコンの苹 積の半分以上を 覆うように低抵抗導体 1を形成し、一定電位 （低電源電位 V S S 8、又は高 電源電位 V D D、 その中間電位でもよい） を与えておく。 尚、 本発明に於け る酸化膜とは絶縁膜を意図する。 An embodiment of the present invention will be described with reference to the drawings. Fig. 3 shows the basic configuration of the present invention. FIG. 3 is a structural diagram of a resistance element made of polycrystalline silicon. Reference numeral 2 denotes a resistance element using polycrystalline silicon, and both ends thereof are led out to electrodes 4 and 6 via contacts 5 and 7, respectively. The material of the electrodes 4 and 6 is aluminum. Then, a low-resistance conductor 1 is formed so as to cover more than half of the polycrystalline silicon by sandwiching the acid ibE on the upper part of the polycrystalline silicon 2 and a constant potential (low power supply potential VSS 8 or high power supply potential VDD). , Or its intermediate potential). Incidentally, the oxide film in the present invention intends an insulating film.
この様な構造の抵抗素子は次の様な利点がある。 まず低抵抗導体 1の上部 に配置される信号線、及び外界からのノイズが抵抗素子へ飛び込むのを防止 すること力できる。 つまり抵抗素子の周隨こ存在する浮遊容量、 浮遊ィンダ クタンス等から伝わる電気 *磁気ノイズは、 低抵抗導休の静電しゃへい効果 により取り除かれる。 よって抵抗素子は、半導体装置の動作中でもノイズに より電流一 «ΕΕ特性（即ち抵抗値) 力変化することなく、安定した精度の高 い素子として使われる。  The resistance element having such a structure has the following advantages. First, it is possible to prevent noise from a signal line disposed above the low resistance conductor 1 and the outside world from jumping into the resistance element. In other words, the electric and magnetic noise transmitted from the stray capacitance, stray inductance, etc. existing around the resistance element is removed by the electrostatic shielding effect of low resistance conduction. Therefore, the resistance element is used as a stable and high-precision element without a change in current-to-current characteristic (that is, resistance value) due to noise even during operation of the semiconductor device.
次に、 ii 程中及び完成後に抵抗素子へ外部から入り込む +イオン、 一 イオンの進入を防止すること力《できる。 つまり低抵抗導体の電位より +側に 蒂電して 、るィォンは反発させ抵抗素子から遠ざけ、一側に帯電して 、るィ オンは低抵抗導体へ引きよせる。 す'ると、 半導体装置の電源をいれている間 は、 抵抗素子近傍のイオン分布は一定となり、外部イオンによる電界影響を 防ぐこと力できる。  Next, it is possible to prevent the + ions and one ion from entering the resistance element from the outside during the process ii and after completion. In other words, when the electric potential of the low resistance conductor is higher than the potential of the low resistance conductor, Rion repels and moves away from the resistance element, and is charged to one side, and the Rion is drawn to the low resistance conductor. Then, while the power supply of the semiconductor device is turned on, the ion distribution near the resistance element becomes constant, and the effect of the electric field by external ions can be prevented.
よつて辭変化により抵抗値が変動することを防止することが可能となる。 さらに低抵抗導体は、外部から抵抗素子へ照 される光を遮断することが 可能である。 高抵抗多結晶シリコン抵抗-は半導体である為、可視光、赤外線、 紫外線等の光エネルギーにより、 電子エネルギー力く遷移し、結果的に抵抗素 子としての特性力 <変化してしまう。 そこで低抵抗導体という物理的保護材で 覆うことにより上記の様な問題点はなくなり安定した抵抗素子となる。 Therefore, it is possible to prevent the resistance value from fluctuating due to a change in the dictionary. Furthermore, the low-resistance conductor can block light radiated from outside to the resistance element. Since a high-resistance polycrystalline silicon resistor is a semiconductor, it changes its electron energy by light energy such as visible light, infrared light, and ultraviolet light, and consequently changes its characteristic force as a resistive element. So, with a physical protection material called a low resistance conductor By covering, the above-mentioned problems are eliminated and a stable resistance element is obtained.
以上、 外界からの影響で抵抗素子特性が変動することを防止する利点をあ げてきたが、 反対に抵抗素子自体から発生するノイズ、 電界 ·磁界を周囲へ およぼさないという禾 lj点もある。 とくに高速で動作する回路の場合、 抵抗素 子を流れる電荷も急激に変動する為、 熱雑音を大きくなり、 この抵抗素子か ら放出される不要幅射は無視できなくなり、 この様な場合、 有効である。 抵抗の材料としては、 P型多結晶シリコン、 N型多結晶シリコンの他にィ ォン打ち込みしな L、か、 ィォン打ち込み量を少なくした高抵抗の多結晶シリ コン （ハイレジと呼ぶ） 、又はシリコンに限らず他の半導体、 及び半導体— 金属化合物においても、 本発明は同じ効果を持つ。  As mentioned above, the advantage of preventing the resistance element characteristics from fluctuating due to the influence of the outside world has been provided.However, on the contrary, the noise point generated by the resistance element itself, the electric field and the magnetic field do not reach the surroundings, and the point j is there. Particularly in a circuit that operates at high speed, the charge flowing through the resistor element also fluctuates rapidly, increasing thermal noise, and unnecessary radiation emitted from this resistor element cannot be ignored. It is. The material of the resistor may be P-type polycrystalline silicon, N-type polycrystalline silicon, L which is not implanted, or high-resistance polycrystalline silicon which is reduced in the amount of ion implantation (referred to as a high-resistor), or The present invention has the same effect not only for silicon but also for other semiconductors and semiconductor-metal compounds.
低抵抗導体の材質としては、 アルミニウム、 タングステン、 モリブデンは どの金属が一般的であるが、 多結晶シリコンでも効果はある。 さらに力リウ ムひ素系の化合物♦超電導材料でも可能である。  Aluminum, tungsten, and molybdenum are commonly used as materials for the low-resistance conductor, but polycrystalline silicon is also effective. In addition, it is possible to use a compound of rhodium arsenic-based superconducting material.
本発明は構造が簡単である為、 応用範囲力;'極めて広い。 その中から抵抗素 子の構造に関する応用例に焦点を絞り、 実施例をあげてゆく。  Since the present invention has a simple structure, its application range is extremely wide. We will focus on application examples related to the structure of resistive elements, and give examples.
第 5図は半導体基板表面に形成された選択的酸化膜 （以下 L 0 C 0 Sと呼 ぶ） 上に本発明の多結晶シリコン抵抗を形成した図である。 基板 5 5上に L 0 C O S 5 3を形成し、 その上に酸化膜 5 2を介して多結晶シリコン抵抗 5 0を形成する。 さらに酸化膜 5 6をはさみアルミニウムの導体 5 1で抵抗 5 (〕を覆い、 アルミニウム導体 5 1には電源 V S S 54を接続しておく。 L O C O Sの上部に抵抗素子を形成することの利点は、 L 0 C 0 S膜が厚い為、 多結晶シリコンの真下に寄生トランジスタ力できにくい、 基板との距離が遠 くなる為、 抵抗素子と基板の間の浮遊容量が少なくなる。 抵抗直下のビンホ 一ルによりリークカ<防止しやすい等があげられる。 第 5図は低抵抗導体で覆 うことにより、 抵抗素子としての安定性、 高精度性、 信頼性がさらに高まる。 第 6図は L O C O Sの直下に高濃度拡散領域を設けた応用例の図である。 トランジスタの耐圧を上げる為に LOCOSの下に高 拡散領域 （ストッ パー） を設ける。 第 6図は Pチヤネノレ領域なので、 濃い N+ ストッパー 65 を設け、基板 66より VDD電位を与える。 LOCOS 64の上に多結晶シ リコン抵抗 60を形成し、 その上部をアルミニウム導体 61で覆い、 その電 位を VDD67とする。 この構成にすると抵抗 60は VDDに保たれるアル ミニゥム導体 61と N+ストッパー 65によって上下力、らシーゾレドされる。 よつて抵抗素子としての特性も安定し力、つトランジスタの耐圧も上か'るとい う二重の効果がある。 Nチャネル領域では、 0じ03下の？— ゥエルに P+ ストッパ一を設け、 この P+ ス卜ヅノ、'一及びアルミニウム導体に VS S を与えれば全く同じ効果が得られる。 FIG. 5 is a diagram in which a polycrystalline silicon resistor of the present invention is formed on a selective oxide film (hereinafter referred to as L0C0S) formed on the surface of a semiconductor substrate. L 0 COS 53 is formed on a substrate 55, and a polycrystalline silicon resistor 50 is formed thereon via an oxide film 52. Furthermore, the oxide film 56 is sandwiched between the aluminum conductor 51 and the resistor 5 () is covered, and the aluminum conductor 51 is connected to the power supply VSS 54. The advantage of forming a resistance element above the LOCOS is that L Since the 0 C 0 S film is thick, it is difficult for a parasitic transistor to be generated directly below the polycrystalline silicon, and the distance from the substrate is long, so that the stray capacitance between the resistive element and the substrate is reduced. It is easy to prevent leaks, etc. In Fig. 5, by covering with a low resistance conductor, the stability, high accuracy and reliability of the resistance element are further improved. FIG. 6 is a diagram of an application example in which a high-concentration diffusion region is provided immediately below LOCOS. A high diffusion region (stopper) is provided under LOCOS to increase the breakdown voltage of the transistor. Since FIG. 6 shows the P channel region, a dark N + stopper 65 is provided, and a VDD potential is applied from the substrate 66. A polycrystalline silicon resistor 60 is formed on the LOCOS 64, and the upper portion thereof is covered with an aluminum conductor 61, and its potential is set to VDD67. With this configuration, the resistor 60 is vertically dissociated by the aluminum conductor 61 kept at VDD and the N + stopper 65. Therefore, there is a double effect that the characteristics as a resistive element are stabilized and the withstand voltage of the transistor is increased. In the N-channel region, below 0:03? — The same effect can be obtained by providing a P + stopper on the well and applying VSS to this P + strobe, aluminum and the aluminum conductor.
第 7図 （a) は、抵抗と同じ材料で抵 ¾¾¾辺をシ一ルドした錢例の平面 図で、第 7図 （ b ) は A— B線の断面図である。本発明のシールド効杲をよ り高めるには、 抵抗素子と同じ高さ （層） にもシールド材を形成することが 望ましい。 そこで、多結晶シリコン抵抗素子 70の周囲に多結晶シリコン 7 7を配置し、 それらを全て覆う V S Sに接続されたアルミニウム導体 75を 形成し、 ァノレミニゥム導体 75と多結晶シリコン 77はできる限りコンタク 卜 76、 78を設ける。 こうすることにより多結晶シリコン 70の抵抗値は 下がり、低抵抗導体に対してシ一ルド効果を発揮する。 図中 73、 74は、 コンタクト 71、 72を介して多結晶シリコン 70に接続されるアルミニゥ ム導体 75を同層のアルミニウム電極線である。  FIG. 7 (a) is a plan view of an example in which the sides of the resistor are shielded with the same material as the resistor, and FIG. 7 (b) is a cross-sectional view taken along line AB. In order to further enhance the shielding effect of the present invention, it is desirable to form a shielding material at the same height (layer) as the resistance element. Therefore, polycrystalline silicon 77 is arranged around the polycrystalline silicon resistance element 70, an aluminum conductor 75 connected to VSS is formed to cover them all, and the anode conductor 75 and the polycrystalline silicon 77 are contacted as far as possible. , 78 are provided. By doing so, the resistance value of the polycrystalline silicon 70 decreases, and a shield effect is exerted on the low-resistance conductor. In the figure, reference numerals 73 and 74 denote aluminum electrode wires in the same layer as the aluminum conductor 75 connected to the polycrystalline silicon 70 via the contacts 71 and 72.
第 8図は抵抗素子の下層にシールド層を形成した構造図である。 半導体基 板 83の上に酸化膜 86をはさみ、 導体 82を形成し、電位を V S S 85と する。 この導体 82は通常第 1多結晶シリコン力;'用いられる。 そして酸化膜 をはさみ、 第 2多結晶シリコンによる抵抗素子 80力形成され、 さらに酸化 膜をはさみ、 V S S 84へ電位をとられたアルミニウム導体 81力抵抗素子 80の上部を覆う。 この構造にすれば、 抵抗素子 80をその上下層からシー ルドする為、 安定した抵抗素子が得られるという効果は高い。 ここで第 1多 結晶シリコンはアルミニゥムより高抵抗であるため第 1多結晶シリコンと V S S電源を接続する為のコンタクトを多くとる程、前記効果が大きくなるこ とはいうま.でもない。 特に導体力 <多結晶シリコンの場合、 抵抗素子を挾んで 対向する多結晶シリコンの両端部の 2個所に少なくとも電源コンタクトを配 置する等して、 多結晶シリコン導体の各部分の電位をできるだけ均一にする ようにすれば、 抵抗素子に対する効果はより一層向上する。 FIG. 8 is a structural diagram in which a shield layer is formed below a resistive element. An oxide film 86 is sandwiched on the semiconductor substrate 83 to form a conductor 82, and the potential is set to VSS 85. This conductor 82 is usually used for the first polycrystalline silicon force. Then, the oxide film is sandwiched, and the resistance element 80 is formed by the second polycrystalline silicon. The film is sandwiched and covers the top of the aluminum conductor 81 force-resistive element 80 which is energized to VSS 84. With this structure, since the resistance element 80 is shielded from the upper and lower layers, the effect of obtaining a stable resistance element is high. Here, since the first polycrystalline silicon has a higher resistance than aluminum, it goes without saying that the greater the number of contacts for connecting the first polycrystalline silicon to the VSS power supply, the greater the effect becomes. In particular, in the case of conductor force <polycrystalline silicon, the potential of each part of the polycrystalline silicon conductor is made as uniform as possible by arranging at least two power supply contacts at both ends of the polycrystalline silicon opposed to each other with the resistance element interposed therebetween. By doing so, the effect on the resistance element is further improved.
第 9図 （a) は第 1図の構造に於いて、 低抵抗導体の電位を VDD 90に とつた抵抗素子の構造図である。 シールド効果^、う点からすると V S Sで も VDDでも変わりない。  FIG. 9 (a) is a structural diagram of the resistive element in which the potential of the low-resistance conductor is set to VDD 90 in the structure of FIG. From the point of view of the shielding effect, it does not change with VSS or VDD.
第 9図 （b) は同じく低抵抗導体への印加電位をトランジスタの出力電圧 から取り出して VDD、 VS Sの中間電位とする場合の一側図である。 MO S トランジスタ 91、 92、 93、 のトランジスタ駆動能カを各々 ?^、 β ρ2、 SN1、 βΝ2、 トランジスタしきい値を各々 VTP1 、 VTP2、 VTNI 、 VTN2 とすると信号 96の電位は
Figure imgf000009_0001
FIG. 9 (b) is a side view of the case where the potential applied to the low-resistance conductor is extracted from the output voltage of the transistor and is set to an intermediate potential between VDD and VSS. MO S transistor 91, 92, 93, each transistor driving ability mosquito? ^, Β ρ 2, S N1, β Ν2, signal 96 when each of the transistor threshold V TP1, V T P2, VTNI , and V TN 2 The potential of
Figure imgf000009_0001
但し、 V TNI 一 ΤΝ2 ノ  However, V TNI
VDD— ~ TP2 ~ TPI  VDD-- ~ TP2 ~ TPI
となる。 よって出力電圧は、 VDDを基準とすると、Becomes Therefore, the output voltage is
Figure imgf000009_0002
Figure imgf000009_0002
シールド効果を上げるためには、 中間電位の出力インピーダンスを低くす る必要があるので、第 9図 （b) では、 V2電位のボルテージフォロアとし て差動対を利用し、 出力 97を得ている。 To increase the shielding effect, lower the output impedance at the intermediate potential. Since it is necessary that, in FIG. 9 (b), as a voltage follower of V 2 potential using a differential pair, to obtain an output 97.
さらにシールドされる抵抗素子の温度特性に合わせて、 シールド導体の電 位を変化させてやれば、 シールド抵抗素子を変動させる原因の一つである空 乏層の効果を補償することができる。 例えば第 9図 （b) において、 トラン ジス夕 94のゲ一ト入力を直接ボルテージフォロアの +端子に入力すれば、 p型のシールドされる抵抗素子の空乏層効果を補償することができる。 第 10図は中間夕ップ付抵抗素子の応用回路図である。抵抗を 2分割して、 その中間点からの出カオペアンプ 1◦ 7を通して取り出す回路で、 正確に 2 分割された抵抗素子へ本発明を適用している。  Further, if the potential of the shield conductor is changed in accordance with the temperature characteristics of the shielded resistance element, the effect of the depletion layer, which is one of the causes of the fluctuation of the shield resistance element, can be compensated. For example, in FIG. 9 (b), if the gate input of the transistor 94 is directly input to the + terminal of the voltage follower, the depletion layer effect of the p-type shielded resistance element can be compensated. FIG. 10 is an application circuit diagram of a resistance element with a middle tap. A circuit that divides a resistor into two and takes out from the intermediate point through an output operational amplifier 1 • 7. The present invention is applied to a resistor element that is accurately divided into two.
VDD100と VSS 105にコンタクト 102、 1〇 4を介して接続さ れた多锆晶シリコン抵抗 101には、 その構造上の中間点にコン夕クト 10 A polycrystalline silicon resistor 101 connected to VDD100 and VSS 105 via contacts 102 and 1〇4 has a
3カ'設けられ、 コンタク卜から取り出す信号 106の電位は VDDZ2にな るようにしてある。 この多結晶シリコン抵抗 101の上部を V S Sへ接続さ lたアルミニウム導体 109で覆うことにより、 抵抗値が周囲のノイズゃ電 3 'is provided, and the potential of the signal 106 extracted from the contact is set to VDDZ2. By covering the upper portion of the polycrystalline silicon resistor 101 with an aluminum conductor 109 connected to V SS, the resistance value is reduced by the surrounding noise noise.
5界からシールドされ、部分的に抵抗値が変動してしまうのを防止する。 よ つて出力 V。 108には正確に VDD/2が出力される。 It is shielded from the fifth field and prevents the resistance value from partially changing. Output V. 108 outputs VDD / 2 exactly.
第 11図は第 10図と目的は同じで、 2本の抵抗素子を用いる場台の応用 回路図である。 V D D 110と V S S 111の間に直列接続された 2本の多 結晶シリコン抵抗 114と 115があり、 その 2本をつなぐ信号 116はォ ぺアンプ 117へ入力され、 信号 116の電位がそのまま出力 ¾EV0 11FIG. 11 is an application circuit diagram of a field stand using two resistive elements for the same purpose as in FIG. There are two polycrystalline silicon resistors 114 and 115 connected in series between VDD 110 and VSS 111. The signal 116 connecting the two is input to the ォ amplifier 117, and the potential of the signal 116 is output as it is ¾EV 0 11
8となって出力される。 Outputs as 8.
VDD  VDD
Vo = ― ~~  Vo = ― ~~
2  Two
とする為には、 抵抗 115と 116の構造を全く同じにしておき、 かつ周匪 からのノイズ、 電磁界による影響を防ぐ為、 抵抗 1 1 5と 1 1 6の上層アル ミニゥム導体 1 1 3と 1 1 2で覆い、 同一の電位 1 1 1を与えておく。 こう することにより V o には安定した電圧が出力される。 In order to achieve this, the structure of the resistors 115 and 116 must be exactly the same, and In order to prevent the effects of noise and electromagnetic fields, cover the resistors 115 and 116 with the upper aluminum conductors 113 and 112, and give the same potential 111. By doing so, a stable voltage is output to Vo.
この構成による抵抗分割は極めて応用範囲力広く、 3本、 4本を直列接続 しておけば、 V D DZ 3、 V D DZ4も簡単に得られる。  The resistance division by this configuration is extremely wide-ranging, and VDDZ3 and VDDZ4 can be easily obtained by connecting three or four in series.
又、 スタンダードセル方式による半導体集積装置内のレイァゥト時、 予め 抵抗素子とそれを覆うアルミニゥム等の導体を 1つのセルとして登録してお けば、 簡単に自動配置、 配線処理が可能である。  Also, at the time of layout in a semiconductor integrated device using the standard cell method, if a resistive element and a conductor such as aluminum covering the resistive element are registered in advance as one cell, automatic arrangement and wiring processing can be easily performed.
以上、 多結晶ポリシリコン抵抗を用いた本発明の構造では、 アルミニウム 配線 1層の場合を例にあげて来た力 <、 もちろん 2層、 3層配線の半導体装置 でも応用できる。  As described above, the structure according to the present invention using the polycrystalline polysilicon resistor can be applied to a semiconductor device having two layers or three layers, of course, the force <exemplified in the case of one layer of aluminum wiring.
第 1 2図はアルミ 2層以上の構造図である。 基板 1 2 1の上に酸化膜 1 2 2をはさみ多結晶シリコン抵抗 1 2 0があり、 電極 1 24、 1 2 5を通して 抵抗素子として動作する。 電極 1 2 4、 1 2 5は第 1アルミニウム配線層で ある。 さらに酸化膜 1 2 3、 1 2 6をはさんで、 第 2アルミニウム配線層 1 2 7があり、 多結晶シリコン抵抗 1 2 0の上部全体を覆っており、 かつ V S S電位を与えられている。 この場合、 抵抗素子 1 2 0とシールド材 1 2 7の 距離が、 アルミニウム 1層配線の時より離れる為、 多少シールドの効果は減 る力 \ 抵抗素子のコンタクトをさけてシールド材のパターン設計をしなくて 済むので、 その分、 設計は容易となる。  FIG. 12 is a structural diagram of two or more aluminum layers. There is a polycrystalline silicon resistor 120 sandwiching an oxide film 122 on the substrate 121, and operates as a resistance element through the electrodes 124 and 125. The electrodes 124 and 125 are the first aluminum wiring layers. Further, a second aluminum wiring layer 127 is provided across the oxide films 123 and 126, covers the entire upper portion of the polycrystalline silicon resistor 120, and is supplied with a VSS potential. In this case, the distance between the resistive element 120 and the shield material 127 is farther than in the case of aluminum single-layer wiring, so the shielding effect is somewhat reduced. Since it is not necessary to do so, the design becomes easier.
これまでの実施例は多結晶シリコンを抵抗素材として使う場合であった力 半導体基板に埋め込まれた拡散抵抗の場合でも、 本発明のシールド効梁によ り抵抗の安定化と L、う技術は応用できる。  In the case of the diffusion resistance embedded in the semiconductor substrate, the stabilization of the resistance and the technology of the L and L are achieved by the shield effect beam of the present invention. Can be applied.
第 4図は本発明を拡散抵抗へ応用した時の基本構造図である。 拡散抵抗 1 2の両端にコンタクト 1 5、 1 7を設け、 アルミニウム配線 1 4、 1 6を電 極とする。 そして拡散抵抗の平面 ®¾の半分以上の上部を酸化膜をはさんで アルミニウム導体 11で覆い、 VS S電位 18を与えておく。 この構造によ りアルミニウム導体 11はシールド材となり、外界からの電磁波ノイズや光、 イオン、 よごれを電気的力、つ物理的に遮蔽するので、 拡散抵抗の安定化、 高 精度化の効果がある。 FIG. 4 is a basic structural diagram when the present invention is applied to a diffusion resistor. Provide contacts 15 and 17 at both ends of the diffused resistor 12 and connect the aluminum wires 14 and 16 Pole. Then, an upper portion of at least half of the plane of the diffusion resistance is covered with an aluminum conductor 11 with an oxide film interposed therebetween, and a VSS potential 18 is applied. With this structure, the aluminum conductor 11 becomes a shielding material, and shields electromagnetic noise, light, ions, and dirt from the outside with electric force and physically, so that the diffusion resistance is stabilized and the accuracy is improved. .
拡散氐抗の材質としては N-基板中に形成する Ρ— ゥエル抵抗、 Ρ—基板 中に形成する Ν— ゥエル ί氐抗などの低 拡散抵抗や、 イオン打ち込みで形 成する Ρ+抵抗、 Ν+抵抗などの高？驗拡散抵抗などに本発明は適用できる。 又低抵抗導体の材質としては、 アルミニウムや多結晶シリコンの他、金属 —半導体化合物、超電導物質などが適用できる。 Diffusion resistance material is formed in the N-substrate Ρ—Pell resistance, Ρ—Pell formed in the substrate 低 —Low diffusion resistance such as resistance, or formed by ion implantation Ρ + resistance, Ν + High as resistance? The present invention can be applied to diffusion resistance and the like. As the material of the low-resistance conductor, a metal-semiconductor compound, a superconducting substance, and the like can be applied in addition to aluminum and polycrystalline silicon.
拡散抵抗とシールド材料の組み合わせも多くのものか可能で、 その中から 抵抗の構造に焦点を絞り実施例をあげてゆく。  Many combinations of diffusion resistors and shield materials are possible, and the examples will focus on the structure of the resistors.
第 13図は拡散抵抗の周囲を同じ拡散材料で覆つた場合の構造図である。 第 13図 （a) は平面図、 第 13図 （b) は A— B線の断面図である。 拡散 抵抗 130力《半導体基板 139の浅い部分に形成されており、 その周囲 （横 方向） に同じ拡散材料 137を形成し、 拡散抵抗 130の上部を酸化膜をは さんで覆うアルミニウム導体 135は拡散材料 137とコンタク 136、 1 38を介して接銃され、 さらに電源 V S Sへ電位を与えられる。 こめ構造に より周囲のトランジスタのソース · ドレイン♦又は拡散抵抗力、らの電磁界ノ ィズを遮蔽す 効果か まる。 図中 133、 134は拡散抵抗 130へコン タクト 131、 132を介して接铳される 135と同じ層のアルミニウム電 極線である。  FIG. 13 is a structural diagram when the periphery of the diffusion resistor is covered with the same diffusion material. FIG. 13 (a) is a plan view, and FIG. 13 (b) is a cross-sectional view taken along line AB. Diffusion resistance 130 force << formed in the shallow part of semiconductor substrate 139, the same diffusion material 137 is formed around (in the horizontal direction), and aluminum conductor 135 covering the upper part of diffusion resistance 130 with an oxide film is The material 137 is contacted with the material 137 via the contacts 136 and 138, and the potential is applied to the power supply VSS. The effect of shielding the electromagnetic field noise of the source / drain ♦ or diffusion resistance of the surrounding transistors can be determined by the pad structure. In the figure, 133 and 134 are aluminum electrode wires of the same layer as 135 connected to the diffusion resistor 130 via the contacts 131 and 132.
第 14図は拡散抵抗の下層部にシールド導体を形成した場合の構造図であ る。 P—基.板 143に N+埋め込み層 142力あり、 144、 145は高不 純物; の N型ェピタキシャル層で、 コンタクト 146により V D Dへ電位 をとられている。 140は P+拡散抵抗で、 酸化膜 147をはさみ、 その上 部をアルミニウム導体 141で覆われており、 アルミ導体 141の電位も V DDとなっている。 この構造の拡散抵抗素子は、上下♦左右からシールドさ れる為、 抵抗としての安定性、 精度が極めて高い。 FIG. 14 is a structural diagram in the case where a shield conductor is formed in a lower layer portion of a diffusion resistor. P-base. Plate 143 has N + buried layer 142. 144 and 145 are high impurity; N-type epitaxial layers, and potential is applied to VDD by contact 146. Has been taken. Reference numeral 140 denotes a P + diffusion resistance, which sandwiches an oxide film 147 and has an upper portion covered with an aluminum conductor 141, and the potential of the aluminum conductor 141 is also V DD. Since the diffused resistance element with this structure is shielded from the top, bottom, left and right, the stability and accuracy as resistance are extremely high.
この様に第 13図、 第 14図の実施例では抵抗素子の横方向及び下方向に 対するシールド効果がある為、 半導体集積装置に光や a線が照射された時に 発生する電流路近くのトランジスタのスィツチングによる基板電流の影響を 防ぐという大きな効果も有している。  As described above, the embodiments of FIGS. 13 and 14 have a shielding effect in the lateral and downward directions of the resistance element, so that the transistor near the current path generated when the semiconductor integrated device is irradiated with light or a-line. This has a great effect of preventing the influence of the substrate current due to the switching.
第 15図 （a) は拡散抵抗の周囲をストッパーで囲んだ場合の平面図で、 第 15図 （b) はその A— B線の断面図である。 N—基板で形成した P— ゥ エル 159表面に作られた N型拡散抵抗 150の周囲に P+ ストッパー 15 7を形成し、 コンタクト 156、 158によりアルミニウム導体 155から VS S電位を与える。 この構造によれば、 周囲からの電磁ノイズをシールド して防止する他、 ラッチアップ防止効果もある。  FIG. 15 (a) is a plan view of the case where the periphery of the diffusion resistor is surrounded by a stopper, and FIG. 15 (b) is a cross-sectional view taken along the line AB. A P + stopper 157 is formed around an N-type diffused resistor 150 formed on the surface of the P-well 159 formed on the N-substrate, and a VSS potential is applied from the aluminum conductor 155 by the contacts 156 and 158. This structure not only shields and prevents electromagnetic noise from surroundings, but also has a latch-up prevention effect.
この反転型半導体の場合、 N—基板の上に P型拡散抵抗を形成し、 その周 囲を N+ ストッパーで囲い、 N+ ストッパー及び拡散抵枋 Lhのアルミニウム 導体には V D Dを与えることにより、 やはり電磁ノイズシールド及びラッチ アップ防止という効果がある。 尚、 -図中、 153、 154はアルミニウム導 体と同層のアルミニウム電極線であり、 コンタクト 151、 152を介して 抵抗 150に接続される。  In the case of this inversion type semiconductor, a P-type diffusion resistor is formed on the N-substrate, and the surrounding area is surrounded by an N + stopper, and VDD is applied to the N + stopper and the aluminum conductor of the diffusion fan Lh, thereby again providing an electromagnetic field. It has the effect of noise shielding and latch-up prevention. In the figure, 153 and 154 are aluminum electrode wires in the same layer as the aluminum conductor, and are connected to the resistor 150 via the contacts 151 and 152.
これまで述べて来た拡散抵抗の周囲を一定電位を与えられた導体で覆うと いうことによる静電遮蔽効果は、 多結晶シリコン抵抗の場合と同様前記一定 電位の電源として、 VS S、 VDD、 又はその中問電位でもかまわない。 また、 拡散抵抗に中間タップを設け、 1本の拡散抵抗素子を分圧して使用 する場合も、 その周囲を一定電位に接続された導体で覆うことにより、 抵抗 素子の安定性が高まるという効果がある。 The electrostatic shielding effect by covering the periphery of the diffused resistor with a conductor given a constant potential, which has been described so far, is similar to the case of a polycrystalline silicon resistor. Or, the potential may be the intermediary potential. Also, when an intermediate tap is provided in the diffused resistor and one diffused resistive element is used by dividing the voltage, the surrounding area is covered with a conductor connected to a constant potential to reduce the resistance. This has the effect of increasing the stability of the device.
さらに複数の拡散抵抗素子を用いる場合も前述と同様、本発明力適用でき る。  Further, even when a plurality of diffusion resistance elements are used, the present invention can be applied in the same manner as described above.
第 1 6図は、 本発明のシールド ί氐抗が高周波回路のディレイラインとして 使えることを示す等価回路である。 抵抗 1 6 0〜1 6 3の周瞧ま一定電位の 導体で囲んであるので、 コンデンサ 1 64〜 1 6 7は常に安定な容量暄を得 ること力くでき、 またシ一ルドされているので、 抵抗値の安定性も良い。 信号 は V i側の抵抗端子から入力し、 出力に V0UT側の抵抗端子から取り出す。 FIG. 16 is an equivalent circuit showing that the shield resistance of the present invention can be used as a delay line of a high-frequency circuit. Capacitors 164 to 167 are always able to obtain a stable capacitance fox since they are surrounded by a conductor of constant potential around the resistor 160 to 163, and are also shielded Therefore, the stability of the resistance value is also good. The signal is input from the resistance terminal on the V i side, and output from the resistance terminal on the V 0UT side.
述べてきた様に、本発明はその応用範囲が極めて広い。  As mentioned, the invention has a very wide range of applications.
回路技術の中で最も基本的な受動素子である抵抗素子の精度を上げるとい うことは、 あらゆる電子回路の中で使われる。 特に抵抗の絶対値の精度が必 要な発振回路、 A/D変換回路、 センサー回路、及び複数の抵抗素子の相対 的な値 （抵抗比） の精度が必要な DZA変換回路、電圧検出回路、発振停止 検出回路、 さらに高 ί氐抗としてできる限りリーク電流を抑止が必要なスタチ ック RAM、 E P R OM、 F 2 P R O Mなどの電子デバイスを半導体集積装 g±に形成する場合、本発明は極めて利用しやすいものである。 Increasing the accuracy of resistive elements, the most basic passive element in circuit technology, is used in all electronic circuits. In particular, oscillation circuits, A / D conversion circuits, and sensor circuits that require the accuracy of the absolute value of the resistor, DZA conversion circuits and voltage detection circuits that require the accuracy of the relative value (resistance ratio) of multiple resistance elements, oscillation stop detection circuit, a higher ί氐抗leakage current requires suppression of statin click RAM as possible as, EPR OM, when forming an electronic device, such as F 2 PROM in the semiconductor integrated instrumentation g ±, the present invention is extremely It is easy to use.
さらに本発明の抵抗素子をシールド導体で覆うという技術は、 容量、 トラ ンジスタ、 等の周囲をシールド導体で覆うということにも応用可能で、容量、 - トランジスタの安定性を上げること力できる。  Furthermore, the technique of covering the resistive element of the present invention with a shield conductor can be applied to covering the periphery of a capacitor, a transistor, and the like with a shield conductor, and can increase the capacitance and the stability of the transistor.
本発明は、 既存の製造工程を用いて、 抵抗素子の周辺構造パターンを少し 付加するだけという簡単な構成で、抵抗素子としての安定性、精度が向上す る為、 その応用範囲が極めて広い。  INDUSTRIAL APPLICABILITY The present invention has an extremely wide range of applications because the stability and accuracy of a resistor are improved with a simple configuration in which the peripheral structure pattern of the resistor is slightly added using existing manufacturing processes.
抵抗素子の安定性、 精度が向上するとは、 抵抗素子としての絶対値、 ある いは複数の抵抗素子を用いた時の相対抵抗比に関して、 周囲の電磁界ノィズ の,影響を受けにくくなるということである。 また抵抗素子の表面 （一般には酸化膜） 電位がフローティングにならない 様にする為、 イオン等の影響を受けにくくなり、 抵抗値の経年変動を防止で さる。 Improving the stability and accuracy of a resistive element means that the absolute value of the resistive element, or the relative resistance ratio when multiple resistive elements are used, is less affected by the surrounding electromagnetic field noise. It is. In addition, since the surface (generally, an oxide film) potential of the resistance element is prevented from floating, it is less susceptible to ions and the like, and the aging of the resistance value can be prevented.
さらに光により抵抗素子特性が変動することが防止できる。  Further, it is possible to prevent the resistance element characteristics from fluctuating due to light.
そして抵抗素子自体から発生する電磁界ノィズを軽減することができる。 また低濃度拡散により精度の良い高抵抗素子力《実現できる為、 必要面積が 少なくなり、 結果的に半導体集積装置を高集積化できる。  Then, the electromagnetic field noise generated from the resistance element itself can be reduced. In addition, since high-precision high-resistance element power can be realized by low-concentration diffusion, the required area is reduced, and as a result, semiconductor integrated devices can be highly integrated.

Claims

I 5 請 求 の 範 囲 I 5 Scope of Claim
1. 多結晶シリコンまたは半導体基板への不純物拡散で形成される抵抗素子 の少なくとも上方に導体を形成し、該導体に一定電位を印加することを特徵 とする半導体装置。  1. A semiconductor device characterized by forming a conductor at least above a resistive element formed by impurity diffusion into polycrystalline silicon or a semiconductor substrate, and applying a constant potential to the conductor.
2. 前記抵抗素子と前記導体の間には絶縁膜が介在することを特徴とする請 求項 1記載の半導体装置。 - 2. The semiconductor device according to claim 1, wherein an insulating film is interposed between the resistance element and the conductor. -
3. 前言 体は前記抵抗素子の平 ®ϋ積の半分以上を覆うように形成される ことを特徵とする請求項 2記載の半導体装置。 3. The semiconductor device according to claim 2, wherein the precursor is formed so as to cover at least half of the area of the resistance element.
4. 前記抵抗素子の 2つの端子の間の該抵抗素子の上方に、前記導体が形成 4. The conductor is formed above the resistor between the two terminals of the resistor.
10 されることを特徵とする請求項 2記載の半導体装置。 10. The semiconductor device according to claim 2, wherein the semiconductor device is manufactured.
5. 多結晶シリコンよりなる前記抵抗素子は半導体基^ 1：に絶縁膜を介して 形成されることを特徴とする請-求項 3または 4記載の半導体装置。  5. The semiconductor device according to claim 3, wherein the resistance element made of polycrystalline silicon is formed on the semiconductor substrate 11 via an insulating film.
6. 多結晶シリコンよりなる前記抵抗素子は半導体基板に形成された選択的 酸 t)Eの上部に形成されることを特徵とする請求項 3または 4記載の半導体  6. The semiconductor according to claim 3, wherein the resistance element made of polycrystalline silicon is formed on the selective acid t) E formed on the semiconductor substrate.
7. 前記一定電位は、 電源電位であることを特徵とする請求項 5または 6記 7. The device according to claim 5, wherein the constant potential is a power supply potential.
8. 前記一定電位は、 電源の中間電位であることを特徵とする請求項 5また は 6記載の半導体装置。 8. The semiconductor device according to claim 5, wherein the constant potential is an intermediate potential of a power supply.
20 9. 前記選択的酸化膜下の基板に、該基板と同一導醒で基板よりも高不純 物 の拡散領域を設けたことを 4¾とする請求項 6記載の半導体装置。 20. The semiconductor device according to claim 6, wherein the substrate below the selective oxide film is provided with a diffusion region of a higher impurity than the substrate with the same conduction as the substrate.
1 0. 前記基板に電源電位を印加することを傲款とする請求項 9記載の半導 10. The semiconductor device according to claim 9, wherein applying a power supply potential to the substrate is an arbitration.
1 1. 前記導体と前記基板に同一の電源電位を印加することを特徵とする請 25 求項 1 0記載の半導体装置。 11. The semiconductor device according to claim 10, wherein the same power supply potential is applied to the conductor and the substrate.
1 2. 前記抵抗素子の横方向にも前記一定電位の供給された前記導体を絶縁 膜を介在して配置することを特徴とする請求項 3または 4記載の半導体装置。12. The semiconductor device according to claim 3, wherein the conductor supplied with the constant potential is also arranged in a lateral direction of the resistance element with an insulating film interposed.
1 3. 前記橫方向に配置された導体は、 前記抵抗素子と同一層の多結晶層シ リコンよりなり、 前記上方に形成された導体とコンタクトにより接続される1 3. The conductor arranged in the 橫 direction is made of a polycrystalline silicon in the same layer as the resistance element, and is connected to the conductor formed above by a contact.
5 ことを特徴とする請求項 1 1記載の半導体装置。 5. The semiconductor device according to claim 11, wherein:
1 4. 前記横方向に配置された導体は、 前記抵抗素子を挾んで対向すること を特徴とする請求項 1 1または 1 2記載の半導体装置。  13. The semiconductor device according to claim 11, wherein the conductors arranged in the lateral direction face each other across the resistance element.
1 5. 前記抵抗素子の下方に絶縁膜を介して前記一定電位が印加された第 2 の導体を配置することを特徴とする請求項 3または 4記載の半導体装置。0 \ 6. 前記抵抗素子の上方全体を覆うように前記導体が形成されることを特 徴とする請求項 4記載の半導体装置。  5. The semiconductor device according to claim 3, wherein a second conductor to which the constant potential is applied is disposed below the resistance element via an insulating film. 5. The semiconductor device according to claim 4, wherein the conductor is formed so as to cover the entire upper part of the resistance element.
1 7. 半導体基板への不純物拡散で形成される間前記抵抗素子は第 1の拡散 領域よりなり、 該第 1の拡散領域に近隣する前記半導体基板に第 2の拡散領 1 7. The resistive element comprises a first diffusion region while being formed by impurity diffusion into the semiconductor substrate, and a second diffusion region is formed in the semiconductor substrate adjacent to the first diffusion region.
' 域を設け、 該第 2の拡散領域に前記一定電位を供給することを特徴とする請 5 求項 3または 4記載の半導体装置。 5. The semiconductor device according to claim 3, wherein a region is provided, and the constant potential is supplied to the second diffusion region.
1 8. 前記第 2の拡散領域は、 前記第 1の拡散領域を挾んで対向して配置さ れることを特徴とする請求項 1 6記載の半導体装置。  18. The semiconductor device according to claim 16, wherein the second diffusion region is disposed so as to face the first diffusion region.
1 . 前記第 2の拡散領域は前記導体とコンタクトにより接続されることを 特徴とする請求項 1 6または 1 7記載の半導体装置。 18. The semiconductor device according to claim 16, wherein the second diffusion region is connected to the conductor by a contact.
0 2 0. 前記第 1の拡散領域の下方の前記半導体基板に前記第 2の拡散領域と 同一導電型であり、 前記半導体基板とは逆導電型の埋め込み層を設け、 該埋 め込み層は前記半導体基板中で前記第 2の拡散領域を接触するように形成さ れることを特徴とする請求項 1 7または 1 8記載の半導体装置。 0 2 0. A buried layer of the same conductivity type as that of the second diffusion region and of a conductivity type opposite to that of the semiconductor substrate is provided in the semiconductor substrate below the first diffusion region, and the buried layer is 19. The semiconductor device according to claim 17, wherein the semiconductor device is formed so as to contact the second diffusion region in the semiconductor substrate.
2 1 . 前記第 1の拡散領域と前記第 2の拡散領域を同一導電型とすることを5 特徴とする請求項 1 7または 1 8記載の半導体装置。 21. The semiconductor device according to claim 17, wherein the first diffusion region and the second diffusion region have the same conductivity type.
2 2. t 1の拡散領域と前記第 2の拡散領域を逆導電型とすることを特 徴とする請求項 1 8または 1 9記載の半導体装置。 22. The semiconductor device according to claim 18, wherein the diffusion region at t1 and the second diffusion region are of opposite conductivity type.
2 3. 前記抵抗素子は 2つの端子を各々電源に接続してなり、該抵抗素子の 中間点から前記電源 を分割した «Εを取り出すように構成したことを特 徵とする請求項 3または 4記載の半導体装置。 23. The resistance element, wherein two terminals of the resistance element are connected to a power supply, respectively, and the power supply is divided from a middle point of the resistance element to take out the power supply. 13. The semiconductor device according to claim 1.
PCT/JP1989/001180 1988-11-22 1989-11-21 Semiconductor device WO1990005995A1 (en)

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