JPH05129597A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05129597A JPH05129597A JP29124591A JP29124591A JPH05129597A JP H05129597 A JPH05129597 A JP H05129597A JP 29124591 A JP29124591 A JP 29124591A JP 29124591 A JP29124591 A JP 29124591A JP H05129597 A JPH05129597 A JP H05129597A
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor
- semiconductor region
- mos transistor
- current detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000001514 detection method Methods 0.000 claims description 33
- 210000000746 body region Anatomy 0.000 claims description 31
- 230000015556 catabolic process Effects 0.000 claims description 10
- 238000009792 diffusion process Methods 0.000 description 17
- 239000000758 substrate Substances 0.000 description 10
- 238000002955 isolation Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7826—Lateral DMOS transistors, i.e. LDMOS transistors with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に係り、特
に、電力用素子と制御素子とが同一チップ上で共存した
集積回路半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an integrated circuit semiconductor device in which a power element and a control element coexist on the same chip.
【０００２】[0002]
【従来の技術】従来、電力用素子として横型２重拡散Ｍ
ＯＳトランジスタ（以下ＬＤＭＯＳと呼ぶ）を用いた集
積回路半導体装置（ＩＣ）に関しては、高不純物濃度の
ボディ領域でドレイン領域を囲んだＬＤＭＯＳを有する
構造の例が、ザエレクトロケミカル ソサイアティ スプ
リング ミーティングのイクステンディド アブストラ
クト ＶＯＬ．８９−１（１９８９年５月）第４７２頁
から第４７３頁（TheElectrochemical Society、 EXTEN
DED ABSTRACTS、 SPRING MEETING、 VOL.89-1May (198
9)、pp 472-473）において論じられている。この従来例
では、ＬＤＭＯＳの破壊耐量低下の要因となるドレイン
と基板との間の寄生バイポーラトランジスタ動作を抑制
するために、前述の高濃度のボディ領域を設けている。2. Description of the Related Art Conventionally, a horizontal double diffusion M is used as a power element.
Regarding an integrated circuit semiconductor device (IC) using an OS transistor (hereinafter referred to as LDMOS), an example of a structure having an LDMOS in which a drain region is surrounded by a body region having a high impurity concentration is an extension of The Electrochemical Society Spring Meeting. Dido Abstract VOL. 89-1 (May 1989), pages 472 to 473 (The Electrochemical Society, EXTEN
DED ABSTRACTS, SPRING MEETING, VOL.89-1May (198
9), pp 472-473). In this conventional example, the above-mentioned high-concentration body region is provided in order to suppress the operation of the parasitic bipolar transistor between the drain and the substrate, which causes a reduction in the breakdown resistance of the LDMOS.
【０００３】[0003]
【発明が解決しようとする課題】前記従来構造では半導
体基板とＬＤＭＯＳのドレイン間に存在する寄生バイポ
ーラトランジスタの電流利得を低減して、その動作を抑
制する手法が述べられている。しかし、ＬＤＭＯＳのス
イッチング動作により発生する雑音を防止する、いわゆ
るシールド構造に関しては言及されてなかった。また、
ＬＤＭＯＳの電流検出を低損失で行うための電流検出端
子付き（センス）ＦＥＴの実現方法に関しても考慮され
てなかった。従って、ＩＣ構造の中で、センスＦＥＴを
有するＬＤＭＯＳ構造を実現する場合の問題点に関して
は検討がなされてなかった。In the above-mentioned conventional structure, there is described a method of reducing the current gain of the parasitic bipolar transistor existing between the semiconductor substrate and the drain of the LDMOS to suppress the operation thereof. However, no reference has been made to a so-called shield structure for preventing noise generated by the switching operation of the LDMOS. Also,
No consideration has been given to a method of realizing a (sense) FET with a current detection terminal for performing current detection of LDMOS with low loss. Therefore, no consideration has been given to the problem in realizing the LDMOS structure having the sense FET in the IC structure.
【０００４】本発明の目的は、センスＦＥＴを有するＬ
ＤＭＯＳシールド構造の半導体装置を提供することにあ
る。An object of the invention is to have an L with a sense FET.
It is to provide a semiconductor device having a DMOS shield structure.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
に、本発明の一実施形態によれば、第１導電型の第１半
導体領域（１）上に第１導電型の第２半導体領域（２）
を設け、半導体主面から前記第２半導体領域（２）に達
するように環状に形成した第１導電型の第３半導体領域
（４）で分離された第２導電型の第４半導体領域（３
ａ）をＭＯＳトランジスタのドレインとし、前記第４半
導体領域（３ａ）内に、前記第１半導体領域（１）並び
に前記第２半導体領域（２）並びに前記第３半導体領域
（４）とは接しない第１導電型の第５半導体領域（７
ｂ、７ｃ）を複数個形成し、前記第５半導体領域（７
ｂ、７ｃ）のうちの少なくとも１つをセンスＦＥＴのミ
ラー用ＭＯＳトランジスタのボディとしたことを特徴と
するものである（第１図参照）。さらに、本発明の好適
な実施形態によれば、前記センスＦＥＴのミラー用ＭＯ
Ｓトランジスタのボディ（７ｂ）直下には前記第２半導
体領域（２）を設けないようにしたことを特徴とするも
のである（図３参照）。In order to achieve the above object, according to one embodiment of the present invention, a second semiconductor region of a first conductivity type is formed on a first semiconductor region (1) of a first conductivity type. (2)
And a fourth semiconductor region (3) of the second conductivity type separated by a third semiconductor region (4) of the first conductivity type formed in an annular shape so as to reach the second semiconductor region (2) from the semiconductor main surface.
a) is a drain of the MOS transistor, and is not in contact with the first semiconductor region (1), the second semiconductor region (2) and the third semiconductor region (4) in the fourth semiconductor region (3a). Fifth semiconductor region of the first conductivity type (7
b, 7c) are formed, and the fifth semiconductor region (7
b) and 7c), at least one of which is used as the body of the mirror MOS transistor of the sense FET (see FIG. 1). Furthermore, according to a preferred embodiment of the present invention, the MO for the sense FET mirror
The second semiconductor region (2) is not provided immediately below the body (7b) of the S transistor (see FIG. 3).
【０００６】さらに、本発明の好適な他の実施形態によ
れば、前記センスＦＥＴのミラー用ＭＯＳトランジスタ
のボディ（７ｂ）直下には第２導電型の第６半導体領域
（１１）を設けたものである（図４、図５参照）。Further, according to another preferred embodiment of the present invention, a sixth conductivity type semiconductor region (11) of the second conductivity type is provided immediately below the body (7b) of the mirror MOS transistor of the sense FET. (See FIGS. 4 and 5).
【０００７】本発明の他の一実施形態によれば、ドレイ
ン領域（３ａ）を囲む高濃度ボディ領域と前記ドレイン
領域（３ａ）内に形成するセンスＦＥＴのソースと接続
されるボディ領域（７ｃ）との耐圧に比べ、高濃度ボデ
ィ領域と前記ドレイン領域（３ａ）内に形成しセンスＦ
ＥＴのミラー端子と接続されるボディ領域（７ｂ）との
耐圧を高くなるように形成した。（図１、図４、図５、
図６参照）According to another embodiment of the present invention, a high-concentration body region surrounding the drain region (3a) and a body region (7c) connected to the source of a sense FET formed in the drain region (3a). And a sense F formed in the high concentration body region and the drain region (3a),
It was formed to have a high breakdown voltage with respect to the body region (7b) connected to the mirror terminal of ET. (FIG. 1, FIG. 4, FIG.
(See Figure 6)
【０００８】[0008]
【作用】本発明によれば、センスＦＥＴを有するＬＤＭ
ＯＳを高濃度ボディ領域で包含することにより、雑音シ
ールド効果が達成される。また、センスＦＥＴとして働
くミラー端子用ＭＯＳトランジスタのボディ領域直下は
前記高濃度ボディ領域を除去すること、そしてミラー端
子用ＭＯＳトランジスタのボディ領域直下の低濃度ドレ
イン領域を高濃度化すること、さらに、ミラー端子用Ｍ
ＯＳトランジスタのボディ領域直下のみ耐圧確保のため
ドレイン領域を残すことにより、シールド構造のＬＤＭ
ＯＳにおいてもセンスＦＥＴのソース端子とミラー端子
の耐圧を向上することが可能であるという効果がある。According to the present invention, an LDM having a sense FET
The noise shielding effect is achieved by including the OS in the high-concentration body region. Further, removing the high-concentration body region just below the body region of the mirror terminal MOS transistor acting as the sense FET, and increasing the concentration of the low-concentration drain region immediately below the body region of the mirror terminal MOS transistor, M for mirror terminal
By leaving the drain region only under the body region of the OS transistor to secure the breakdown voltage, the shielded LDM
Also in the OS, it is possible to improve the withstand voltage of the source terminal and the mirror terminal of the sense FET.
【０００９】[0009]
【実施例】以下、本発明の実施例を図面に依り詳細に説
明する。Embodiments of the present invention will now be described in detail with reference to the drawings.
【００１０】図１は本発明の第１の実施例の半導体装置
の断面図を示してある。本素子はソース接地型のＬＤＭ
ＯＳである。本構造は１Ωｃｍ以上の通常のＰ型半導体
基板１上に高濃度Ｐ型埋込層２を形成し、環状の素子分
離用のＰ型拡散層４をＰ型埋込層２に達するように設
け、両者により分離されるＮ型エピタキシャル領域３ａ
をドレインとし、素子分離領域でなおかつＬＤＭＯＳの
ボディ領域となっているＰ型拡散層４をソースと接続し
てある。本構造では、多結晶シリコン層６がゲートで、
この多結晶シリコン層に対し自己整合的に形成したＰ型
拡散層７ａ、７ｂ、７ｃをボディとし、Ｎ型拡散層９を
ソースとした。本実施例では素子の周辺部以外のボディ
領域には素子分離用のＰ型拡散層４を使用してないため
ボディ領域の横方向拡散による面積増加を防止できる。
また、素子中央部のボディ領域はＮ型エピタキシャル領
域により分離された構造を実現できる。このため、半導
体基板１へのドレインの電位変動の影響をシールドで
き、これにより素子の周辺に放出される雑音が低減でき
るという効果がある。なお、本実施例では基板１がＰ型
のため基板がソース領域とは反対導電型の前述の従来例
の場合と異なり、ソースと基板との間に存在する寄生バ
イポーラトランジスタの電流利得が大きくなるというこ
とがない。FIG. 1 is a sectional view of a semiconductor device according to the first embodiment of the present invention. This element is a source grounded LDM
OS. In this structure, a high concentration P-type buried layer 2 is formed on a normal P-type semiconductor substrate 1 of 1 Ωcm or more, and an annular P-type diffusion layer 4 for element isolation is provided so as to reach the P-type buried layer 2. , N-type epitaxial region 3a separated by both
Is used as a drain, and the P-type diffusion layer 4 which is an element isolation region and is also a body region of the LDMOS is connected to the source. In this structure, the polycrystalline silicon layer 6 is a gate,
The P-type diffusion layers 7a, 7b and 7c formed in self alignment with the polycrystalline silicon layer were used as the body, and the N-type diffusion layer 9 was used as the source. In this embodiment, since the P-type diffusion layer 4 for element isolation is not used in the body region other than the peripheral portion of the element, it is possible to prevent an increase in area due to lateral diffusion of the body region.
Further, the body region in the central portion of the device can be realized with a structure separated by the N type epitaxial region. Therefore, the influence of the potential fluctuation of the drain on the semiconductor substrate 1 can be shielded, and the noise emitted to the periphery of the element can be reduced. In this embodiment, since the substrate 1 is of P type, the current gain of the parasitic bipolar transistor existing between the source and the substrate becomes large unlike the case of the above-mentioned conventional example in which the substrate has a conductivity type opposite to that of the source region. There is no such thing.
【００１１】図２は本発明のＬＤＭＯＳのセンスＦＥＴ
の等価回路である。ソースとドレインが接続された被電
流検出用ＭＯＳトランジスタ（本体部）１００、１０２
と電流検出用ＭＯＳトランジスタ（ミラー部）１０１か
らなり、電流検出用ＭＯＳトランジスタ１０１と被電流
検出用ＭＯＳトランジスタ１００、１０２のゲート幅の
比を例えば１対１０程度以上に設定するとソース電圧が
ほぼ等しい場合、ソース電流の比が両者のゲート幅の比
となる。電流検出用のＭＯＳトランジスタ１０２のソー
ス１０ｂと被電流検出用ＭＯＳトランジスタのソース１
０ａ、１０ｃとの間には通常抵抗を接続し、電流検出用
のＭＯＳトランジスタのソース電流による抵抗両端の電
圧を測定することによりドレイン電流を検出する。この
ため、被電流検出用ＭＯＳトランジスタのソース１０ａ
と１０ｃの耐圧は不要であるが、電流検出用のＭＯＳト
ランジスタのソース１０ｂと被電流検出用ＭＯＳトラン
ジスタのソース１０ａの耐圧は必要である。すなわち、
図１の実施例ではシールド用の低抵抗ボディ領域２、４
と被電流検出用ＭＯＳトランジスタのボディ７ｃの耐圧
は不要であるが、電流検出用のＭＯＳトランジスタのボ
ディ７ｂとの耐圧は高くする必要がある。FIG. 2 shows an LDMOS sense FET of the present invention.
Is an equivalent circuit of. Current-detecting MOS transistors (main body) 100 and 102 in which sources and drains are connected
And a current detection MOS transistor (mirror portion) 101, and the source voltages are substantially equal when the ratio of the gate widths of the current detection MOS transistor 101 and the current detection MOS transistors 100 and 102 is set to about 1:10 or more, for example. In this case, the ratio of the source currents becomes the ratio of the gate widths of both. Source 10b of MOS transistor 102 for current detection and source 1 of MOS transistor for current detection
A resistor is usually connected between 0a and 10c, and the drain current is detected by measuring the voltage across the resistor due to the source current of the MOS transistor for current detection. Therefore, the source 10a of the current detection MOS transistor
And 10c are not required to withstand voltage, but the source 10b of the current detecting MOS transistor and the source 10a of the current receiving MOS transistor are required to have withstand voltage. That is,
In the embodiment of FIG. 1, the low resistance body regions 2 and 4 for shielding are used.
The withstand voltage of the body 7c of the current detection MOS transistor is not necessary, but the withstand voltage of the body 7b of the current detection MOS transistor needs to be high.
【００１２】図３は本発明の第２の実施例の半導体装置
の断面図を示してある。本実施例では、電流検出用ＭＯ
Ｓトランジスタのソースと被電流検出用ＭＯＳトランジ
スタのソースとの耐圧向上のため電流検出用ＭＯＳトラ
ンジスタのボディ下のみ高濃度Ｐ型埋込層２を除いてあ
る。すなわち、１０ｂをミラー用ＭＯＳトランジスタ
（電流検出用ＭＯＳトランジスタ）のソース電極とし、
１０ａと１０ｃを本体のＭＯＳトランジスタ（被電流検
出用ＭＯＳＦＥＴトランジスタ）のソース電極とした図
２で示すようなソース接地型のセンスＦＥＴを実現した
場合に、ソース端子とミラー端子の耐圧を高くすること
が可能となる。本実施例ではミラー用ＭＯＳトランジス
タのボディ領域直下には低抵抗ボディ領域がないが、主
要ドレイン領域を低抵抗ボディ領域で包含してあるため
シールド効果を保つことが可能である。即ち、本実施例
のドレイン領域は高濃度素子分離領域４と高濃度Ｐ型埋
込層２でほぼ取り囲んだＮ型エピタキシャル領域３ａに
形成してあるため、ドレイン電圧が高速に変動したり誘
導性負荷のためグランド電圧以下に下がった場合にも高
濃度のＰ型ボディ領域がグランド電位に対し低インピー
ダンスで固定される。図４は本発明の第３の実施例の半
導体装置の断面図を示してある。本実施例では電流検出
用ＭＯＳトランジスタのソースと被電流検出用ＭＯＳト
ランジスタのソースとのパンチスルー耐圧向上のための
第２の実施例に高濃度Ｎ型埋込層１１を追加した実施例
である。ここでＮ型埋込層１１にリン、Ｐ型埋込層２に
ボロンを用いると埋込層のピーク濃度はＰ型埋込層が高
く、拡散層のわき上がり量はＮ型埋込層の方が大きく設
定できるためドレインのシールドはＰ型拡散層４とＰ型
埋込層２で行いソースと基板とのパンチスルー耐圧はＮ
型埋込層１１で行うことが可能である。FIG. 3 is a sectional view of a semiconductor device according to the second embodiment of the present invention. In this embodiment, the current detection MO
In order to improve the withstand voltage between the source of the S transistor and the source of the current detection MOS transistor, the high concentration P-type buried layer 2 is removed only under the body of the current detection MOS transistor. That is, 10b is used as the source electrode of the mirror MOS transistor (current detection MOS transistor),
When a source-grounded sense FET as shown in FIG. 2 in which 10a and 10c are used as the source electrodes of the body MOS transistors (current-detecting MOSFET transistors) is realized, the withstand voltage of the source terminal and the mirror terminal is increased. Is possible. In this embodiment, there is no low resistance body region directly under the body region of the mirror MOS transistor, but since the main drain region is included in the low resistance body region, the shield effect can be maintained. That is, since the drain region of this embodiment is formed in the N-type epitaxial region 3a which is almost surrounded by the high-concentration element isolation region 4 and the high-concentration P-type buried layer 2, the drain voltage fluctuates at high speed and the inductive property is high. Even when the voltage drops below the ground voltage due to the load, the high-concentration P-type body region is fixed with a low impedance with respect to the ground potential. FIG. 4 shows a sectional view of a semiconductor device according to a third embodiment of the present invention. In this embodiment, a high-concentration N-type buried layer 11 is added to the second embodiment for improving the punch-through breakdown voltage between the source of the current detection MOS transistor and the source of the current detection MOS transistor. .. Here, when phosphorus is used for the N-type buried layer 11 and boron is used for the P-type buried layer 2, the peak concentration of the buried layer is high in the P-type buried layer, and the raised amount of the diffusion layer is higher than that of the N-type buried layer. Since it can be set larger, the drain is shielded by the P-type diffusion layer 4 and the P-type buried layer 2, and the punch-through breakdown voltage between the source and the substrate is N.
It is possible to use the mold burying layer 11.
【００１３】図５は本発明の第５の実施例の半導体装置
の断面図を示してある。本実施例では電流検出用ＭＯＳ
トランジスタのソースと被電流検出用ＭＯＳトランジス
タのソースとのパンチスルー耐圧向上のため第４の実施
例に高濃度Ｎ型埋込層１１を電流検出用ＭＯＳトランジ
スタのソース直下のみに追加した。これによりドレイン
のシールドはＰ型拡散層４とＰ型埋込層２で行いソース
と基板とのパンチスルー耐圧はＮ型埋込層３で行うこと
が可能である。FIG. 5 is a sectional view of a semiconductor device according to the fifth embodiment of the present invention. In this embodiment, a current detection MOS
In order to improve the punch-through breakdown voltage between the source of the transistor and the source of the current detection MOS transistor, the high-concentration N-type buried layer 11 is added to the fourth embodiment only just under the source of the current detection MOS transistor. As a result, the drain can be shielded by the P-type diffusion layer 4 and the P-type buried layer 2, and the punch-through breakdown voltage between the source and the substrate can be performed by the N-type buried layer 3.
【００１４】図６は本発明の第６の実施例の半導体装置
の断面図を示してある。本実施例では被電流検出用ＭＯ
Ｓトランジスタのボディ領域に電流検出用ＭＯＳトラン
ジスタのボディ領域用拡散層７より深くＰ型拡散層１２
を形成している。これにより、被電流検出用ＭＯＳトラ
ンジスタのボディ領域の抵抗を低減し、破壊強度を増加
した。Ｐ型拡散層１２がシールド用の高濃度埋込拡散層
２に達するように形成した場合には大電流素子の中央部
でのシールド領域の電位変動を防止することが可能であ
る。FIG. 6 is a sectional view of a semiconductor device according to the sixth embodiment of the present invention. In this embodiment, the current detection MO
In the body region of the S transistor, the P-type diffusion layer 12 is deeper than the body region diffusion layer 7 of the current detection MOS transistor.
Is formed. As a result, the resistance of the body region of the current detection MOS transistor is reduced and the breakdown strength is increased. When the P-type diffusion layer 12 is formed so as to reach the high-concentration buried diffusion layer 2 for shielding, it is possible to prevent potential fluctuations in the shield region at the center of the large current element.
【００１５】本発明の他の一実施形態によれば、前記第
１導電型の第１半導体領域（１）の比抵抗を０．５Ωｃ
ｍ以下に選定することにより、前記第２半導体領域
（２）を省略できる場合がある。According to another embodiment of the present invention, the specific resistance of the first conductive type first semiconductor region (1) is 0.5 Ωc.
By selecting m or less, it may be possible to omit the second semiconductor region (2).
【００１６】[0016]
【発明の効果】本発明によれば、ドレインを高濃度ボデ
ィ領域で包含する雑音シールド構造のＬＤＭＯＳトラン
ジスタにおいても良好なセンスＦＥＴを実現できるとい
う効果がある。According to the present invention, there is an effect that a good sense FET can be realized even in an LDMOS transistor having a noise shield structure including a drain in a high concentration body region.
【図１】本発明の第１の実施例の半導体装置FIG. 1 is a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の実施例の等価回路FIG. 2 is an equivalent circuit of an embodiment of the present invention.
【図３】本発明の第２の実施例の半導体装置FIG. 3 is a semiconductor device according to a second embodiment of the present invention.
【図４】本発明の第３の実施例の半導体装置FIG. 4 is a semiconductor device according to a third embodiment of the present invention.
【図５】本発明の第４の実施例の半導体装置FIG. 5 is a semiconductor device according to a fourth embodiment of the present invention.
【図６】本発明の第５の実施例の半導体装置FIG. 6 is a semiconductor device of a fifth embodiment of the present invention.
１…Ｐ型半導体基板、２…Ｐ型埋込層、３ａ、３ｂ…Ｎ
型エピタキシャル層、４…素子分離用Ｐ拡散層、５…絶
縁層、６…多結晶シリコン層、７ａ、７ｃ…被電流検出
用ＭＯＳトランジスタのボディ、７ｂ…電流検出用ＭＯ
Ｓトランジスタのボディ、８、１２…Ｐ型拡散層、９…
Ｎ型拡散層、１０ａ、１０ｃ…ソース電極層（被電流検
出用ＭＯＳトランジスタ）、１０ｄ…ドレイン電極層、
１０ｂ…ミラー電極層（電流検出用ＭＯＳトランジス
タ）、１１…Ｎ型埋込層、１００、１０１…被電流検出
用ＭＯＳトランジスタ、１０２…電流検出用ＭＯＳトラ
ンジスタ。1 ... P-type semiconductor substrate, 2 ... P-type buried layer, 3a, 3b ... N
Type epitaxial layer, 4 ... Element isolation P diffusion layer, 5 ... Insulating layer, 6 ... Polycrystalline silicon layer, 7a, 7c ... Current detection target MOS transistor body, 7b ... Current detection MO
S-transistor body, 8, 12 ... P-type diffusion layer, 9 ...
N type diffusion layers, 10a, 10c ... Source electrode layer (current detection MOS transistor), 10d ... Drain electrode layer,
10b ... Mirror electrode layer (current detection MOS transistor), 11 ... N-type buried layer, 100, 101 ... Current detection MOS transistor, 102 ... Current detection MOS transistor.
Claims (4)
型の第２半導体領域を設け、半導体主面から前記第２半
導体領域に達するように環状に形成した第１導電型の第
３半導体領域で分離された第２導電型の第４半導体領域
をＭＯＳトランジスタのドレインとし、前記第４半導体
領域内に、前記第１半導体領域並びに前記第２半導体領
域並びに前記第３半導体領域とは接しない第１導電型の
第５半導体領域を複数個形成し、前記第５半導体領域の
うちの少なくとも１つを電流検出用端子を有するＭＯＳ
トランジスタのボディとしたことを特徴とする半導体装
置。1. A first-conductivity-type second semiconductor region is provided on a first-conductivity-type first semiconductor region, and the first-conductivity-type second semiconductor region is formed in an annular shape so as to reach the second semiconductor region from a semiconductor main surface. The fourth semiconductor region of the second conductivity type separated by the third semiconductor region is used as the drain of the MOS transistor, and the first semiconductor region, the second semiconductor region, and the third semiconductor region are provided in the fourth semiconductor region. A MOS having a plurality of first conductivity type fifth semiconductor regions that are not in contact with each other, and at least one of the fifth semiconductor regions has a current detection terminal.
A semiconductor device having a body of a transistor.
電流検出用端子を有するＭＯＳトランジスタのボディと
なる直下には前記第２半導体領域を設けないようにした
ことを特徴とする請求項１記載の半導体装置。2. The fifth semiconductor region of the first conductivity type,
2. The semiconductor device according to claim 1, wherein the second semiconductor region is not provided immediately below the body of a MOS transistor having a current detection terminal.
電流検出用端子を有するＭＯＳトランジスタのボディと
なる直下には前記第２導電型の第４半導体領域より高濃
度の第２導電型の第６半導体領域を設けたことを特徴と
する請求項１記載の半導体装置。3. A fifth semiconductor region of the first conductivity type,
The sixth semiconductor region of the second conductivity type having a higher concentration than that of the fourth semiconductor region of the second conductivity type is provided immediately below the body of the MOS transistor having the current detection terminal. Semiconductor device.
て、ドレイン領域の主要部を高濃度ボディ領域で分離
し、前記ドレイン領域内に電流検出用端子を有するＭＯ
Ｓトランジスタのソース用ボディ領域とミラー用ボディ
領域を設け、前記高濃度ボディ領域とソース用ボディ領
域の耐圧に比べ、前記高濃度ボディ領域とミラー用ボデ
ィ領域の耐圧の方を高くしたことを特徴とする半導体装
置。4. A lateral double-diffused MOS transistor, wherein a main part of a drain region is separated by a high-concentration body region, and a current detection terminal is provided in the drain region.
The source body region and the mirror body region of the S transistor are provided, and the breakdown voltage of the high concentration body region and the mirror body region is higher than the breakdown voltage of the high concentration body region and the source body region. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29124591A JPH05129597A (en) | 1991-11-07 | 1991-11-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29124591A JPH05129597A (en) | 1991-11-07 | 1991-11-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05129597A true JPH05129597A (en) | 1993-05-25 |
Family
ID=17766365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29124591A Pending JPH05129597A (en) | 1991-11-07 | 1991-11-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05129597A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100380577B1 (en) * | 1995-09-22 | 2003-07-18 | 페어차일드코리아반도체 주식회사 | Sense fet with improved voltage and current detecting ability |
| US6825543B2 (en) | 2000-12-28 | 2004-11-30 | Canon Kabushiki Kaisha | Semiconductor device, method for manufacturing the same, and liquid jet apparatus |
| US6867457B2 (en) | 2002-07-10 | 2005-03-15 | Canon Kabushiki Kaisha | Semiconductor device and liquid jetting device using the same |
| CN102810540A (en) * | 2012-07-31 | 2012-12-05 | 电子科技大学 | LDMOS (laterally diffused metal oxide semiconductor) device with current sampling function |
-
1991
- 1991-11-07 JP JP29124591A patent/JPH05129597A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100380577B1 (en) * | 1995-09-22 | 2003-07-18 | 페어차일드코리아반도체 주식회사 | Sense fet with improved voltage and current detecting ability |
| US6825543B2 (en) | 2000-12-28 | 2004-11-30 | Canon Kabushiki Kaisha | Semiconductor device, method for manufacturing the same, and liquid jet apparatus |
| US7056798B2 (en) | 2000-12-28 | 2006-06-06 | Canon Kabushiki Kaisha | Semiconductor device, method for manufacturing the same, and liquid jet apparatus |
| EP2302677A1 (en) | 2000-12-28 | 2011-03-30 | Canon Kabushiki Kaisha | Method for manufacturing a semiconductor device |
| US6867457B2 (en) | 2002-07-10 | 2005-03-15 | Canon Kabushiki Kaisha | Semiconductor device and liquid jetting device using the same |
| CN102810540A (en) * | 2012-07-31 | 2012-12-05 | 电子科技大学 | LDMOS (laterally diffused metal oxide semiconductor) device with current sampling function |
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