WO1990003011A1 - Procede et circuit pour affichage - Google Patents

Procede et circuit pour affichage Download PDF

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Publication number
WO1990003011A1
WO1990003011A1 PCT/US1989/003895 US8903895W WO9003011A1 WO 1990003011 A1 WO1990003011 A1 WO 1990003011A1 US 8903895 W US8903895 W US 8903895W WO 9003011 A1 WO9003011 A1 WO 9003011A1
Authority
WO
WIPO (PCT)
Prior art keywords
alternate
display
information
registers
video
Prior art date
Application number
PCT/US1989/003895
Other languages
English (en)
Inventor
Arun Johary
Tetsuji Oguchi
Original Assignee
Chips And Technologies, Inc.
Ascii Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chips And Technologies, Inc., Ascii Corporation filed Critical Chips And Technologies, Inc.
Priority to KR1019900701037A priority Critical patent/KR900702469A/ko
Publication of WO1990003011A1 publication Critical patent/WO1990003011A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/147—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using display panels
    • G06F3/1475—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using display panels with conversion of CRT control signals to flat panel control signals, e.g. adapting the palette memory

Definitions

  • the invention relates to a video graphics controller for a personal computing system. More par ⁇ ticularly, the invention selects between main video information and alternate video information to provide video control information compatible with either a CRT or a flat panel display.
  • the typical personal computing system employs a central processing unit, a video controller, and a video display device.
  • the central processing unit pro ⁇ vides address, data, and clock information to the video controller which interacts with the system memory and ultimately controls the images displayed in the video display device.
  • CTR cathode ray tube
  • personal computing systems have used cathode ray tube (CRT) type display devices. More recently, however, many manufacturers and vendors have employed flat panel display devices. Among other advantages, a flat panel display can be fabricated thinner and more compactly than can a CRT display.
  • a flat panel display has a slower response time than a CRT display because it is a chemically operative system.
  • This difference in re ⁇ sponse time requires differences in timing, sync, hori- zontal, vertical, and other display control functions for the two types of devices.
  • These control differences necessitate different hardware and circuitry in the controllers used with a flat panel display as compared to a controller used with a CRT.
  • processors and graphics controllers are designed to interface with only a CRT, or possibly a flat panel display, but not both.
  • U.S. Patent No. 4,338,597 pertains to a method for co - municating between a CRT and its controller over long distances.
  • U.S. Patent No. 4,739,313 describes a method and circuit for using a composite video input to generate a plurality of video outputs.
  • U.S. Patent No. 4,563,676 discloses a circuit for generating a composite video signal.
  • U.S. Patent No. 4,626,837 describes a technique for superimposing video information.
  • British Patent No. 2085257 involves a text mode display. The size of display characters is controlled by changing the frequency of the clock while the character is being displayed (horizontally) and by repeating the character line (vertically) .
  • the invention is useful in a data processing system having a processor, a display device, and a video controller.
  • the video controller receives address, data, and clock information from the processor, interacts with a memory, and generates video output for display by the display device.
  • the invention comprises a controller that includes a plurality of main circuits. alternate circuits, select circuits, and a circuit for identifying the display device used in the system.
  • Each main circuit receives information from the processor and generates main video information.
  • Each alternate circuit receives information from the processor and generates alternate video information.
  • the identifying circuit receives information from the display device or the processor and generates display identification information.
  • Each select circuit receives main video information from a main circuit and alternate video function information from a corresponding alternate circuit.
  • Each select circuit provides the main video information as output when the display is a main display such as a CRT and the alternate video information as output when the display device is an. alternate display such as a flat panel.
  • At least one alternate circuit comprises a register. In one embodiment of the invention, at least one alternate circuit is programmable. In another embodiment of the invention, at least one alternate circuit is pro ⁇ grammable by the processor during system powerup.
  • the video functions that are selected include the following: horizontal display size, vertical display size, blanking, blink rate, and sync functions.
  • the invention also includes a plurality of tables, each having a program corresponding to a possible display device.
  • a decoder decodes the device identification information and en ⁇ ables a table corresponding to the identified device.
  • the enabled table programs the alternate registers to provide video functions compatible with the identified device.
  • FIG. 1 is a data processing system according to one embodiment of the invention.
  • FIGS. 2A and 2B show an array of main circuits, alternate circuits, and select circuits according to embodiments of the invention
  • FIG. 3 is a block diagram of a controller subsystem for generating timing signals according to one embodiment the invention.
  • FIGS. 4 and 5 are block diagrams of various embodiments of the invention.
  • the invention will now be explained first by reference to the operation of a controller in a data processing system as shown in FIG. 1.
  • the invention will be further explained by reference to the operation of main registers and alternate registers according to the embodiment of the invention shown in FIG. 2.
  • the invention will be further explained by reference to a circuit for selecting timing signals for a flat panel and CRT as shown in FIG. 3.
  • the invention will then be explained by reference to the operation of tables which program alternate registers to provide video functions for a plurality of alternative display devices as shown in FIG. 4.
  • the invention will be explained by reference to the use of a select logic circuit as shown in FIG. 5.
  • FIG. 1 shows components commonly used in a typical personal computing system.
  • the system 2 has a central processor 10, a video graphics controller 12, and a video display device 14.
  • Processor 10 provides address, data, clock and other video control information to a plurality of main registers 20, alternate registers 30, and to a memory (not shown) .
  • the registers 20, 30 control controller hardware 50.
  • CRT controller overflow registers; preset roll scan registers; maximum scan line registers; cursor start scan line registers; cursor end scan line registers; start address high registers; start address low registers; cursor location high .registers; cursor location low registers; vertical sync start registers; light pin high registers; light pin low registers; vertical sync end registers; vertical display enable end registers; offset registers; underline location registers; start vertical blanking registers; end vertical blanking registers;
  • CRT mode control registers line compare registers; graphics address registers; set/reset registers; enable said reset registers; color compare registers; data rotate registers; read map select registers; graphics mode registers; color don't care registers; bit mask registers; feature control registers; input status registers; seek point registers; character font select registers; color registers; pixel panning registers; pixel padding registers; global control registers; general purpose output registers; video interface registers; emulation mode registers; light registers; and other miscellaneous registers.
  • Each of the foregoing registers may be included as a main register in controller 12 to generate video control information that is provided to a corresponding video hardware circuit 50 in controller 12.
  • ⁇ • register primarily refers to the conventional registers used in a conven- tional video controller. In a broader sense however,
  • register is used to refer to any conventional digital circuit which receives and outputs digital bits.
  • register should also be understood to apply to discrete physical registers which output a plurality of bits which are processed essentially as one word.
  • register is not strictly limited by the physical proximity of bit handling circuits but is directed to the logical relationship between bit handling circuits.
  • the hardware 50 in controller 12 could be conventional circuits for performing the previously mentioned video control functions.
  • Each hardware cir ⁇ cuit 50 generates video information that is provided to display 14 either directly or through a data handler circuit (not shown) as is generally known in the art.
  • controller 12 includes alternate registers (represented by alternate register 30) , a display type register 31, and select circuits (represented by select circuit 40) .
  • Alternate registers 30 receive video informa ⁇ tion from main registers 20 or, alternatively from pro ⁇ cessor 10, and output alternate video control information to select circuit 40. Main video control information from main registers 20 is also provided to select circuit 40. Alternate registers 30 may perform the same, or substantially the same, functions as the main registers 20 listed above but will cause
  • Each alternate register 30 may be a conventional register as each main register 20.
  • alternate registers 30 are programmed by processor 10 when processing system 2 is powered up. Processor 10 programs alternate registers 30 depending on the identity of display device 14. Registers 30 are programmed such that the video control information output from each register will cause the video display to be compatible with the alternate display device 14. ( In a simple case, the alternate registers can be generically programmed to generate the same video control information wherever a standard flat panel display is used. In a more elaborate embodiment, processor 10 can include application software such that the alternate registers are programmable to provide compatibility for a number of identifiable display types or display modes.
  • processor 10 provides address, data, and other information to the alternate registers in parallel with the main registers.
  • the alternate registers output alternate video information to select circuit 40.
  • Select circuit 40 receives main video information from main registers 20 and an identification signal identifying the display device from a display type register 31 in alternate registers 30.
  • Select circuit 40 will provide main video information as output when the display device is a main preferred display such as a CRT display device.
  • select circuit 40 will provide as output alternate video control information generated by the alternate registers 30.
  • the selected video control information will be provided as input to hardware circuits 50, and thereafter processed as in a conventional controller.
  • central processing unit 10 will program alternate registers 30 during system powerup.
  • processing unit 10 will be totally unaware of the existence of the alternate reg ⁇ isters and will continue to interface with the main registers. According to the invention, however, alter ⁇ nate registers 30 and select circuit 40 will generate video control information compatible with an alternate display device.
  • the processor can now drive a plurality of display devices with minimal changes to the processor hardware.
  • the processor's application software will continue as if it is in communication only with the main registers; however, the alternate registers will provide actual control of the controller hardware.
  • alternate registers and a select circuit have been added to resolve the need for generating video control information compatible with a flat panel display without modifying normal processing in the processor or the other controller circuitry for the CRT.
  • the alternate registers and the se ⁇ lect circuit have been described as being programmed based on information identifying the display device, it should be understood that the registers and the select circuit can be programmed and made responsive to other desirable information.
  • the identification information could identify a current display mode de ⁇ fined by certain graphics, horizontal display size, vertical display size, and font characteristics.
  • the processor will program the alternate registers to provide video control information compatible with a very specific display device in a particular display mode.
  • FIG. 2 shows a main register array 20 and an alternate register array 30 that feed an array 40 of select circuits for generating sync information for both a CRT and flat panel display.
  • Main register array 20 includes among its many regis- ters a CRT horizontal sync register 24 and a CRT vertical sync register 26.
  • Alternate register array 30 includes reg- isters having functions corresponding to the functions of the registers in main register array 20.
  • alternate register array 30 includes a flat panel horizontal sync register 34 and a flat panel vertical sync register 36.
  • the video control information from CRT hori ⁇ zontal sync register 24 (main video information) and flat panel horizontal sync register 34 (alternate video information) are fed into a select circuit 42.
  • select circuit 46 receives main video information and alternate video information from registers 28 and 38, and 29 and 39, respectively. Each select circuit in select circuit array
  • main display type such as a CRT
  • select circuits will provide as output the alter ⁇ nate video information.
  • each select circuit is provided to controller hardware circuitry to control specific video display functions.
  • the horizontal sync signal selected by select circuit 42 is provided to a horizontal sync circuit 54.
  • the vertical sync information selected by select circuit 46 is provide to a vertical sync circuit 56.
  • the video information selected by each of select circuits 44 and 48 is likewise provided to their counterpart hardware circuits.
  • FIG. 2B is a more sophisticated circuit diagram showing the relationship between main registers 20, alternate registers 30, select circuits 40A and 40B, and hardware 50 according to another embodiment of the invention.
  • FIG. 2B emphasizes that main registers 20 will typically interact with the alternate registers and the hardware in three different ways according to the invention.
  • main registers 20 will always interface with the controller hardware 50 regardless of whether the display is a CRT or a flat panel display.
  • a graphics controller register will always provide con ⁇ trol information to its hardware whether the display is a CRT or a flat panel display.
  • main registers 23 will be used when the display is a CRT display but will not be used when the display is a flat panel display.
  • main registers 23 will be used when the display is a CRT display but will not be used when the display is a flat panel display.
  • a horizontal sync register in registers 20 will be used in a CRT mode but will not be used in a flat panel mode. The horizontal sync information will then be obtained from horizontal sync register and alternate registers 30.
  • registers 25 are used in both the CRT mode and in the flat panel mode.
  • the contents of registers 25 are used in the flat panel mode to generate a control signal that is used for selecting between the contents of various alternate registers.
  • main registers 25 refer again to FIG. 2B.
  • registers 25 provide an output to a decoder 39. Decoder 39 provides a control signal output that is used as a select signal input to an alternate select circuit 40B.
  • the inputs to alternate select circuit 4OB are the contents of alternate registers 33A, 33B and 33C.
  • alternate select circuit 40B selects alternate video information from alternate register 30, and the selected alternate information is provided to select circuit 40A.
  • Select circuit 40A is represen ⁇ tative of the select circuits used for selecting between the contents of main registers 20 and alternate registers 30.
  • Select circuit 40A is responsive to a select signal from a display type register 31 in the alternate registers,30.
  • main regis ⁇ ters 25 may be used to provide a control signal for selecting between the contents of a plurality of alter ⁇ nate registers.
  • FIG. 3 shows a circuit for generating alternate timing signals according to one embodiment of the invention. As shown in FIG.
  • a 25 megahertz clock 62 and a 28 megahertz clock 64 each provide a clock signal to a select circuit 68.
  • a 22 megahertz clock 66 also provides a clock input to select circuit 68. It should be understood that any alternate frequency (clock) other than 22 MHz required by a flat panel can be provided within the spirit of the inven- tion.
  • Select circuit 68 selects one of the three clock input signals in response to information provided from a select circuit 76.
  • Select circuit 76 is in turn fed the output from a main clock register 72 and an alternate clock register 74.
  • Select circuit 76 will output main clock information when an identification signal received by select circuit 76 indicates the display device is a CRT.
  • select circuit 76 will output alternate clock information when the identification signal indicates the display device is a flat panel display.
  • Select circuit 68 will select the clock in ⁇ formation from CRT clock circuit 62 or 64 when the se ⁇ lect circuit 76 outputs main clock information.
  • select circuit 68 will output the 22 megahertz clock when the select circuit 76 outputs alternate clock information.
  • FIG. 4 shows a data processing system 2 that includes an array of tables 90 for programming alternate registers 30 and a decoder 100 for enabling table array 90.
  • Decoder 100 receives identification information that identifies a current display mode or a current display device 14A used in processing system 2. Decoder 100 decodes the identification information and provides an output to one of the tables in table array 90.
  • Table array 90 includes a plurality of tables 92, 94, 96, 98, and 99, etc. Each table programs alternate registers 30 differently depending on the identity of display device 14A or the display mode. For example, if display 14A were a flat panel display having specific font, vertical, horizontal, and text or
  • table A will be configured to program alternate registers 30 so that video control information will be provided to the controller hardware compatible with the display mode.
  • Tables 90 may be included in the controller circuitry and could, upon receiving the identification information, program alternate registers 30 during sys ⁇ tem powerup. Thereafter, alternate registers 30 would provide alternate video control information to select circuits 40 as has been previously discussed.
  • FIG. 5 shows yet another embodiment of the invention. This embodiment is distinguished by the use of a select control logic circuit 41 for generating a select signal for select circuit 40.
  • Select control circuit 41 receives mode bits from main registers 20 and display type information from display type register 31 and alternate registers 30.
  • the mode bits indicate the desired mode for the display, such as texts or graphics mode, number of lines, color or monochrome, and similar information.
  • the select control logic circuit receives the mode bits and display type information and generates select control signals that are provided to the select circuits represented by select circuit 40.
  • alternate registers have been used according to various embodiments in parallel with the main registers used in some conventional controllers. It should be understood, however, that where other circuits (than registers) are used in a controller to generate video control information, similar alternate circuitry may be employed according to the invention. For these non-register applications, the video control information from the main circuit and alternate circuits would be provided to a select circuit that would output the appropriate information depending on the identity of the display device to be used in the system.
  • select circuit refers to a digital circuit or circuits that selects between a plurality of inputs in response to identifiable control signals.
  • circuit diagrams herein are illustrative only and that circuits designed using state of the art computer assisted design techniques might look very different from the disclosed circuits without at all escaping the scope, spirit, and function of the invention and the embodiments disclosed herein.

Abstract

Une unité de commande d'affichage vidéo (12) peut fournir des informations de commande vidéo soit pour un affichage à écran plat soit pour un affichage à tube à rayon cathodique. L'unité de commande (12) comprend plusieurs circuits principaux (20), des circuits secondaire (30), des circuits de sélection (40) et un circuit (50) d'identification du dispositif d'affichage (14) utilisé dans le système. Chaque circuit principal (20) reçoit des informations provenant du processeur (10) et génère des informations vidéo principales compatibles avec un tube à rayon cathodique. Chaque circuit secondaire (30) reçoit des informations provenant du processeur (10) et génère des informations vidéo secondaires compatibles avec un affichage à écran plat. Chaque circuit de sélection (40) reçoit des informations vidéo principales et secondaires et sort des informations vidéo principales lorsque le dispositif d'affichage (14) est un dispositif d'affichage à tube à rayon cathodique et des informations vidéo secondaires lorsque le dispositif d'affichage (14) est un affichage à écran plat. Dans un mode de réalisation, les circuits secondaires sont des registres programmables. Dans un autre mode de réalisation, des tables (90) sont utilisées pour programmer les registres secondaires (31) de manière à établir une compatibilité pour plusieurs dispositifs d'affichage possibles.
PCT/US1989/003895 1988-09-16 1989-09-08 Procede et circuit pour affichage WO1990003011A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900701037A KR900702469A (ko) 1988-09-16 1989-09-08 디스플레이를 위한 페이크아웃(fakeout) 방법 및 회로

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US24587488A 1988-09-16 1988-09-16
US245,874 1988-09-16

Publications (1)

Publication Number Publication Date
WO1990003011A1 true WO1990003011A1 (fr) 1990-03-22

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ID=22928448

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1989/003895 WO1990003011A1 (fr) 1988-09-16 1989-09-08 Procede et circuit pour affichage

Country Status (2)

Country Link
KR (1) KR900702469A (fr)
WO (1) WO1990003011A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4760387A (en) * 1985-03-19 1988-07-26 Ascii Corporation Display controller
EP0295692A2 (fr) * 1987-06-19 1988-12-21 Kabushiki Kaisha Toshiba Dispositif de commande d'affichage pour un appareil à TRC/plasma

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4760387A (en) * 1985-03-19 1988-07-26 Ascii Corporation Display controller
EP0295692A2 (fr) * 1987-06-19 1988-12-21 Kabushiki Kaisha Toshiba Dispositif de commande d'affichage pour un appareil à TRC/plasma

Also Published As

Publication number Publication date
KR900702469A (ko) 1990-12-07

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