Classifications

• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B19/00—Programme-control systems
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B19/00—Programme-control systems
  • G05B19/02—Programme-control systems electric
  • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
  • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B2219/00—Program-control systems
  • G05B2219/10—Plc systems
  • G05B2219/11—Plc I-O input output
  • G05B2219/1151—Fast scanning of I-O to put I-O status in image table
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B2219/00—Program-control systems
  • G05B2219/10—Plc systems
  • G05B2219/11—Plc I-O input output
  • G05B2219/1159—Image table, memory
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B2219/00—Program-control systems
  • G05B2219/10—Plc systems
  • G05B2219/13—Plc programming
  • G05B2219/13064—Execute reverse sequence
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
  • G05B2219/00—Program-control systems
  • G05B2219/10—Plc systems
  • G05B2219/15—Plc structure of the system
  • G05B2219/15102—Programmer simulates, behaves like a programming drum

Definitions

• This invention relates generally to
• a programmable logic controller or PLC furnishes a drum- ype sequencer contained in firmware memory step or scan an array of addresses and switches sequentially and sense or be responsive to time inputs, to event inputs, ⁇ r to a combination of time and event inputs.
• the operation may be stepped sequentially or non-sequentially and may be operated both forwardly and backwardly.
• Figure 1 is a block diagram showing a drum-type function sequencer in accordance with the invention, positioned in the executive memory of a programmable logic controller;
• Figure 2 shows a sequencer coupled in a rung of a ladder array
• Figure 3 shows the configuration table register and the step table registers of the sequencer
• Figure 4 shows an example of a drum- type sequencer in a ladder program
• FIGS 9 and 10 are flow charts depicting the operation of the inventive drum sequencer.
• FIG. 1 shows a block diagram of a communications system 11 including a drum-type function drum sequencer 20.
• the system 11 of Figure 1 includes a control processor 12, which may be of suitable known design, provides management functions for the system and coordinates the operation of all the components of system 11.
• System 11 includes an executive memory 14 (which may be part of the control processor 12) , and executive memory 14 includes the drum-type function sequencer 20.
• system 11 further includes a compiled user memory 15, a communications interface 28, a system bus interface 23, an image memory 16, and a keyswitch 21.
• the information to and from the system bus 25 is provided through system bus interface 23 and its port 23A.
• the system 11 includes a scan processor 22 and math co-processor 27.
• Control processor 12 either performs or coordinates all processor system 11 operations. This includes performing all communication via a communications interface port and a master bus, and handling all interrupts and error conditions from the scan processor, communications interface network bus, and the remainder of the programmable controller system.
• a scan processor is not included in the system of Figure 1.
• the control processor 12 functions as a scan processor.
• a math co-processor 27 may not be included in the system 11 and the control processor 12 accomplishes this math function.
• Executive memory 14 comprises firmware and includes the drum-type sequencer 20.
• Compiled user memory 15 comprises a RAH and in operation contains a compiled version of the executive memory to serve as executable instructions for the scan processor 22.
• the compiled user memory 14 is randomly accessible by the control processor 12 for purposes of loading and editing user programs.
• the scan processor 22 accesses the compiled user memory 15 as an executive memory of successive instructions.
• the compiled user memory 15 provides the ladder rung, rack addressing, and label data to requesting devices connected to the communications ports. This RAM is implemented with static CMOS devices which are battery backed and parity protected.
• the image memory 16 receives the input data from the control processor 12 and stores it for access by the scan processor 22.
• Keyswitch and status LED 21 provide a turn-on control and status indicator for the system.
• the inventive system 11 including the drum sequencer 20 allows the outputting of information based on either, or both, time driven or event driven conditions.
• Figure 2 shows that the sequencer 20 is operated in a ladder configuration.
• a minimum of two rungs are required for the sequencer operation.
• the logic in the first rung allows the sequencer to be reset, or , enabled.
• the second rung specifies the addresses and instructions.
• the required entries to the sequencer 20 for operation will be discussed hereinafter.
• Figure 3 depicts the memory register allocation for the sequencer 20.
• Registers D1-D10 are the configuration table registers and serve to define the operating conditions for all of the possible 255 steps in the sequence function. Each of the 255 steps is then defined by six sequential register positions. Since each step requires six registers, the total number of registers required for each sequencer is given by the relation.
• Register Dl contains the step number currently being carried out by the sequencer. This number can be changed by the user, and will result in the sequencer immediately going to the newly changed step.
• Register D2 is the Operating Mode or Status register. All of the main operating conditions for the sequencer are contained in this register.
• Register D3 will contain the amount of time that the current step has been executing. A step advance will be enabled when this register is incremented to equal the 'step time' condition.
• Register D4 contains the address of the register that will contain the input. Bits in the register being pointed to will be compared to the 'step input* condition.
• Register D5 contains the address of the first output register, and is, therefore. a pointer. The 'step output' will be written to the register to which this register is pointing.
• Register D6 controls the width of the output data, as defined in bits.
• the 5 width of the output data can be varied by the user, from 1 to 64 bits. This register will therefore determine how many 16-bit registers will be required to make up the output register, beginning with the register that is 10 pointed to by D5.
• Register D7 points to a step that is not in sequence. This register contains the address of an out-of-sequence step that will be used only if bit 8 of register D2 is set. 15 Setting bit 8 of D2 is not the only condition required to cause the sequencer to move to the step in D7; the out-of-sequence jump will also require that all other conditions for advancing out of the current step are
• Register D8 functions the same as register D7, except that it uses bit 9 as the signal to step out of sequence, provided bit 9 is set, and all other step advance conditions
• Register D9 holds the step number of the previous scan. The sequence will immediately go to the new step (as pointed to in Dl) if register D9 is not equal to register
• Register D10 is a spare.
• Figure 3 also indicates the step table registers for the first step, generally labeled as 18 and individually as D11-D16.
• Each set of six step table registers apply to one particular step in the sequence.
• the fixed size for each step table register block is six registers long. A description of each of the six registers follows.
• Register Dll (D17 in step 2, D23 in step 3, etc.) is the time condition advance register.
• the register contains the user specified step time of this step. This time is entered in 0.1 second increments. When this time is equal to the Running Time Register D3, a step advance based on time is enabled. This register will be strictly input driven (with time ignored) if this register is set to zero.
• Register D12 (D18 in step 2, D24 in step 3, etc.) is the input condition advance register. This register contains the bits that must be set at the input, before the sequencer will recognize that the required input conditions have been met. Upon the inputs matching this register, the step advance condition is recognized (see Figure
• Register D13 (D19 in step 2, D25 in step 3, etc.) is the step 1 output states (1st register) .
• This register contains the first 16 output bits for each of the respective sequence steps. These bits are written to the 'pointed at' register from the first output register for the current sequence step.
• Register D14 (D20 in step 2, D26 in step 3, etc.) is the step 1 output states (2nd register) : It is the same as output register 1, except that these are the output states for the second register.
• Register D15 (D21 in step 2, D27 in step 3, etc.) is the step 1 output states (3rd register) . It is the same as output register 1, except that these are the output states for the third register.
• Register D16 (D22 in step 2, D28 in step 3, etc.) is the step 1 output states (4th register) . It is the same as output register 1, except that these are the output states for the fourth register.
• Register D2 provides an important control function. A listing of the purpose of various bits in register D2 follows. Register D2 Bit Number Purpose
• sequencer is controlled by time/input advance information.
• sequencer advance is controlled by bit 7.
• all outputs will reset and the "current step" register Dl will indicate "0".
• step advance is enabled when input condition is satisfied ONLY AFTER the time advance condition has been met.
• step advance is enabled when either the time or input conditions has been satisfied.
• the sequencer requires the following actions: The two rungs in Figure 2 must be entered. The LET rung must be executed every scan even when the sequencer is reset. Whatever register is specified to the left of the * «* (equal) sign contains the current step number. For convenience zzzz should equal xxxx so that the sequencer can be located in the program by searching for the first register in the block.
• the drum sequencer is executed during each scan of the ladder program, assuring program control of the outputs based on user-defined status.
• the sequencer operates as follows:
• the Current Step Running Time (D3) register will begin to accumulate time.
• Step conditions of the next advance contained in registers Dll and D12 are compared with the real-time states of the Current Step Running Time register D3, and with the bit pattern of the input register being pointed at by register D4.
• Bit 10 of the Operating Mode register is checked to determine if either or both conditions must be met prior to a step advance.
• the Current Step Running Time register accumulates time as long as it has not timed out (equals Dll) , or bit 3 of the operating mode register isn't set to *1*.
• the sequencer checks the status of bit 5 in the Operating Mode register Dl. This is a check for AUTO or MANUAL operation. Whether in AUTO or MANUAL, the sequencer now knows what criteria to monitor when determining a step advance. Once the appropriate criteria for a step advance are satisfied, bit 4 of register D2 is checked to see if advance is inhibited.
• bits 8 and 9 of register D2 are checked to see if the advance will be non ⁇ sequential.
• bit 2 of register D2 is checked to see if the advance will be incrementing or decrementing.
• the sequencer checks to see if it has just completed a pass through the final step. If it has, then bit 6 of register D2 is also checked. Finally, the output states for the appropriate step are written to the outputs being pointed at. The entire process then starts anew.
• the operator controls the sequencer in the Manual Mode.
• the values of these drum sequencer control registers and bits can be
• the sequencer has the capability of operating in a manual mode, a time mode, an event mode, and a combination time and event mode.
• the manual sequencing mode provides override control by toggling bit 7 of register D2.
• bit 5 of register D2 is set to *1*; and in this manual operation, the sequencer is advanced by toggling bit 7 of
• the time sequence mode operates based on time inputs.
• the following parameters apply for a time-advanced operations
• the operation is automatic, so bit
• register D12 (and D18/D24/etc., depending on the number of steps) is set to *0*.
• Time Advance condition is entered into register Dll (and
• the time is entered in tenth-second (0.1 second) increments.
• Register D3 will now reset and begins timing again. When the time specified 10 by register D17 has accumulated in D3, the advance to step 3 occurs.
• bit 1 of register D2 is set to *1', and bit 5 of register D2 is set to '0'.
• the time sequence mode can be modified as follows:
• sequencer can be set to operate in reverse by setting bit 2 of D2 to '1') .
• the Current Step Running Time can be inhibited fran timing by setting bit 3 of register D2 to "1".
• a step advance inhibit is enabled by setting bit 4 of register D2 to "1". This inhibits an advance even if the time requirement for the advance has elapsed.
• the event sequence mode operates based on event inputs.
• the following parameters apply to an input-advanced operation:
• Load register D4 with the address of the input register being pointed at. This will be used for comparison to determine advance conditions. All Time Condition advance registers (Dll, D17, etc.) should be set to "0". Input condition advance registers (D12, D18, etc.) should be preset with the bit pattern which, when compared to the register that is pointed at by D4, will allow a step advance.
• This process continiies as long as bit 1 of register D2 is set to “1” and bit 5 of register D2 is reset to "0".
• the default incremental-forward stepping mode may be altered in the following four ways: A. Backward advance (decrement step) .
• bit 2 of register D2 is set to '1', causing the sequencer to step backward. Decrementing from sequencer step 1 causes the sequencer to go to the last step of the sequence.
• Bit 8/register D7 and bit 9/register D8 function identically; two pairs are provided for user convenience.
• D9 is compared with Dl. If they differ, a new step has been specified in Dl. Normal sequencer operation resumes from that point - register D3 resets and begins timing, and the Input Condition advance register for the new step is used for comparison.
• the Automatic Step Advance Inhibit applies regardless of whether the step change is to be forward or backward.
• output control reverts to control of the automatic advance condition. For example, if the only condition for advance is inputs (which happen to be satisfied) , the step advance will occur the instant that bit 4 is reset to *0*.
• Input Register Address . . . 0001 (any or all of the 16 bits can be used to establish advance conditions).
• bits 2, 3 and 4 of the output register (4) are to be set to "1".
• the initiation rungs needed are shown in Figure 4.
• 0752-01 is the RESET/ENABLE bit for the sequencer.
• 0751 is the address that identifies the start of the register block.
• SPEC 65 identifies the special instruction as a sequencer, while 20 is the number of steps in the sequencer. The following registers have to be set up for the first step (step 1) in Example One:
• Step 1 Output States bit 1 through 16. Since bits 2, 3 and 4 of register 0004 will be set to '1*, preset to 14
• Step 1 Output States bits 17 -64. Since the sequencer's output width is less than 17, these registers are not applicable.
• registers 0751 and 0753 will equal zero, and bits 1 through 12 of register 0004 will be reset to *0* every time the initiation rungs (see Figure 4) are scanned.
• the sequencer sets register 0751 to
• Bit 23 of register 0752 is set to *1' for one scan.
• Register 0753 begins to time (to be compared with register 0761) to determine Time Advance enable.
• register 0001 (the Input Register pointed at by register 0754) is compared to register 0762 to see if
• Step advance to step 1 is now complete. Assuming no Operating Mode register bits are set, the next step advance will occur when bits 1, 3 and 4 (specified in register 0762) of register 0001 (pointed at by register 0754) are set to *1'. Before this comparison occurs however, the time condition for advance (60 seconds) must be satisfied.
• step 2 10 bits are set to *1*.
• the output bit pattern for step 2 is fixed such that bits 1, 4 and 5 of register 0004 are to be set to '1' (all other bits '0') .
• step 20 the last step
• bit 5 of register 0752 is set to '1' and the sequencer will ignore both time and input advance conditions. Toggle bit 7 of register 0752 to manually step the sequencer.
• bits 8 and 9 of register 0752 are used to make the sequencer jump to a step that is not in numerical order (for example, jump from step 1 to step 4, ignoring 2 and 3).
• Register 0757 or 0758 will need to be loaded with a valid step number (1 to 20) , otherwise the current step will be maintained. If bit 8 or 9 of 0752 is set, and advance conditions are satisfied, the sequencer jumps to the step specified in register 0757 (if bit 8 is set) or register 0758 (if bit 9 is set) .
• Figures 9 and 10 show self- explanatory flowcharts or diagrams depicting operating steps for the sequencer.
• sequencing may be performed forwardly, backwardly or non- sequentially.
• a step advance may be based on time or on up to 16 input events; or, the step
• 10 advanced may be based both on time and/or event.
• the time accumulated during a step may be held or paused.
• Output state changes may be inhibited despite step completion. Further, a sequence may be repeated or halted.

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• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Automation & Control Theory (AREA)
• Programmable Controllers (AREA)

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Citations (6)

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• 1989
  • 1989-04-10 CA CA000596163A patent/CA1337877C/en not_active Expired - Fee Related
  • 1989-04-11 WO PCT/US1989/001516 patent/WO1989009952A1/en not_active Application Discontinuation
  • 1989-04-11 AU AU33638/89A patent/AU621606B2/en not_active Ceased
  • 1989-04-11 JP JP1505833A patent/JPH03500589A/ja active Pending
  • 1989-04-11 BR BR898906813A patent/BR8906813A/pt unknown
  • 1989-04-11 KR KR1019890702315A patent/KR900700937A/ko not_active Application Discontinuation
  • 1989-04-11 EP EP19890905915 patent/EP0366775A4/en not_active Ceased

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