WO1989001653A1 - Processeur et procede de traitement de chaine en parallele pour micro-ordinateur - Google Patents

Processeur et procede de traitement de chaine en parallele pour micro-ordinateur Download PDF

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Publication number
WO1989001653A1
WO1989001653A1 PCT/US1988/001119 US8801119W WO8901653A1 WO 1989001653 A1 WO1989001653 A1 WO 1989001653A1 US 8801119 W US8801119 W US 8801119W WO 8901653 A1 WO8901653 A1 WO 8901653A1
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WIPO (PCT)
Prior art keywords
register
string
shift register
bit
byte
Prior art date
Application number
PCT/US1988/001119
Other languages
English (en)
Inventor
David Methvin
Angus Mclagan
Chong Sam Un
Gei Jon Pao
Original Assignee
Davin Computer Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Davin Computer Corporation filed Critical Davin Computer Corporation
Priority to KR1019890700674A priority Critical patent/KR890702109A/ko
Publication of WO1989001653A1 publication Critical patent/WO1989001653A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90—Details of database functions independent of the retrieved data types
    • G06F16/903—Querying
    • G06F16/90335—Query processing
    • G06F16/90344—Query processing by using string matching techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/02—Indexing scheme relating to groups G06F7/02 - G06F7/026
    • G06F2207/025—String search, i.e. pattern matching, e.g. find identical word or best match in a string

Definitions

  • the present invention relates generally to computer systems for processing strings of data, and also to a parallel string processor for a minicomputer and a method of 5 searching strings of bits and bytes for the presence of a desired keyword.
  • Prior art computers and microprocessors process data strings one byte at a time.
  • One of the most frequently occurring processing tasks is to attempt to locate one or 0 more control characters in a data string.
  • Prior art systems compare the data one byte at a time to the control or reference characters which are loaded into a CPU (central processing unit) register. After a byte is compared, the data string is rotated one byte so that the next byte in the 5 data string is compared, continuing until all bytes are compared.
  • search and replace operations are also used in connection with automatic spelling check programs that are offered by many commercially available word processing programs.
  • each letter of the alphabet as well as each symbol such as an asterisk or hyphen is represented as a unique string of eight 1 or 0 logic bits, also known as a byte.
  • the corresponding bits in each byte are compared to determine whether they are th same. If all of the bits in the two byte strings ar identical, the two byte strings represent the same word.
  • a portion of text can be thought of and is represente as a long, continuous string of bytes, one byte for eac letter appearing in the portion of text.
  • current string processors typically, starting at the beginning of the byte string that represents
  • the processor compares the first byte of the keyword with the first byte of the character string. If these two bytes match (the first letter of the keyword matches the first letter in the portion of text) , then the processor compares the second byte in the keyword to the second byte in the character string. If these two bytes match, then the processor compares the next pair of bytes in the two strings, and so on. If all of the respective bytes in the two strings match, the processor has found an occurrence of the keyword in the portion of text.
  • the keyword does not usually appear as the first word in the portion of text being searched.
  • the character string is shifted one byte relative to the keyword so that the first byte of the keyword is compared to the second byte of the character string. If these two bytes match, then the second byte of the keyword is compared to the third byte of the character string, and so on. If one of the pairs of bytes do not match, then the character string is again shifted one byte relative to the keyword so that the first byte of the keyword is now compared to the third byte of the character string.
  • This general process repeats, usually until all occurrences of the keyword in the portion of text have been found.
  • this particular example required 21 comparisons to find the keyword "the” in the character string "that time is the essence.” In particular, four comparisons were required even where the keyword matched the same word in the character string (the blank space required one comparison) .
  • encryption and decryption algorithms used to scramble . and unscramble binary information to protect it from unauthorized reception. Such algorithms are often used in the intelligence field to protect highly classified information from being intercepted and used by foreign countries having adverse interests. These algorithms are also used by corporations to safeguard their valuable commercial information and trade secrets.
  • these encryption and decryption algorithms may perform similar search and replace operations as described above in connection with word processing programs.
  • Processors such as those described above in connection with word processing programs do not even have this capability since they shift strings of bits eight bits, or one byte, at a time. Even if such processors had the capability to shift strings of data one bit at a time, their use as described above on strings of bits would be even slower due to the large number of comparisons that would be necessary.
  • the bit string "11001110011011" is to be searched for the presence of the keyword "1101." Initially, as described above, the first bit of the keyword would be compared to the first bit in the bi string as set forth below:
  • the processor would need to make four comparisons before i could determine that the four bits in the keyword do no match the first four bits in the bit string. Again, a described above, the processor would then, shift the bi string relative to the keyword string as set forth below an compare the respective bits again:
  • the present invention comprises a portion of a computer system for comparing a number of bytes simultaneously.
  • the parallel processor, of the present invention includes a first
  • the parallel byte processor has the ability to branch to a predetermined memory location if any of the byte pairs being simultaneously compared are equal. If any byte of
  • the instruction branches or proceeds to a second predetermined memory location.
  • a number of bytes may be moved and checked for control characters with a single instruction, thereby substantially reducing the processing time.
  • Another aspect of the invention is directed towards a novel parallel bit and byte string processor for a minicomputer.
  • the processor In its byte mode, stores a portion of a string of bytes that is to be tested for the
  • the processor instead of testing the portion of the byte string one byt at a time, the processor simultaneously tests each byte i the keyword with a respective byte in the byte string.
  • the processor In its bit mode of operation, stores portion of a bit string that is to be tested for th presence of a desired string of bytes in a first registe location and the desired keyword in a second registe location.
  • the processor simultaneously tests each bit i the keyword with a respective bit in the bit string. As result of this simultaneous testing, only one comparison i needed to determine whether the keyword is present in th portion of the bit string being tested- If the keyword i not present, .the bit string is shifted one bit relative t the keyword and a single comparison of the keyword with th new portion of the bit string is made. This proces continues until the keyword is found or until the end of th bit string is reached. Because each bit in the keyword i simultaneously tested with a respective bit in the bi string, only a single comparison is required to determin whether the keyword matches a portion of the bit string, an as a result, processing time is minimized.
  • Another feature of the invention is the capability o the processor to automatically function either as a paralle bit processor or as a parallel byte processor.
  • the processo functions as a parallel byte processor
  • the processor functions as a parallel bit processor.
  • FIG. 1 and 2 are block diagrams of two registers of the parallel byte comparison processor
  • Fig. 3 is a circuit diagram of the comparison circuit 15 of the parallel byte comparison processor
  • Fig. 4 is a representative instruction sequence of the parallel byte comparison processor
  • Fig. 9 is a detailed flowchart of the operation of the parallel processor of Fig. 5 in its bit mode of operation.
  • a selected control character such as "EOS" (end of sector)
  • EOS end of sector
  • a selected control character such as "EOS" (end of sector)
  • an 8-byte (64 bit) data string is loaded into a Register B and compared to the "EOS" reference characters in Register A in order to determine whether ther are any "EOS” characters in any byte of the data string i the Register A.
  • the results of the comparison whether an particular byte of Register A matches the corresponding byt in Register B, is stored in a Processor Status Register 10 (also referred to as the "hit register") .
  • any number of. bytes may be simultaneously compared, th number depending on the particular computer system utilized.
  • the compute is a 64-bit machine; therefore, 8 bytes are simultaneousl compared to determine whether they contain a contro character.
  • FIG. 3 is a functional diagram to illustrat the invention. In the actual embodiment, an arithmeti logic unit (ALU) is utilized to perform the exclusive-O function as shown in Fig. 5 and discussed in further detai hereinafter.
  • ALU arithmeti logic unit
  • A67 refers to bit 7 of byte 6 of the Register A.
  • the components of the exclusive-NOR circuit 109 ar also shown in Fig. 3 as comprising first and second AN
  • the bit pairs, for example, A77 and B77 are input to the AND gate 110.
  • the bits A77 and B77 ar also inverted by inverters 112 and 113, respectively, an are input into the second AND gate 111 of the exclusive-NO
  • IfX circuit. The output of the first AND gate 110 and th output of the second AND gate 111 are input to the OR gat
  • each OR gate is provided as an input t one of eight 8-input NAND gates 115-122 (the NAND gates 116
  • the output of any of the 8-input NAN gates 204-210 will be low or logical "0" only when all eigh bits being compared are equal and thus will indicate tha the particular byte pair is equal to each other (e.g., when all the bits A00-A07 of the Register A are equal to the
  • An instruction causes the system to branch or proceed
  • the system proceeds to execute the instruction found in the next sequential memory location in the control memory of the processor. If a hit occurs, the location of the particular bytes which do match can be determined by looking at which bits of the Processor Status Register 100 5 indicate a match. For example, if byte 3 of the Register A is equal to byte 3 of the Register B, bit 3 in the Processor Status Register will be zero, indicating that the byte 3 pair matches.
  • Fig. 4 shows a representative instruction sequehce. The left column corresponds to the line number in the control program of the processor. The instruction at line SO causes the control character being compared to be loaded into the Register A.
  • the instruction at line 82 causes the loading of Register B with the first eight bytes of data (data word 1, indicated as "DATA1" in Fig. 4) .
  • the instruction at line 84 performs the multibyte "exclusive- NOR" operation of the present invention on the data in the Register B and the Register A.
  • the instruction at line 86 causes the system to branch to a memory location 400 if any of the bits in the Processor Status Register 100 (Fig. 2) are zero indicating that a match was found between the Registers A and B.
  • At memory location 400, which is executed if a hit is found, is the beginning of a routin which examines the bits of the Processor Status Register 100 to determine the location of the characters within data wor 1 which match the control character "EOS" for example.
  • Register A is loaded with a secon control character and at line 90 the exclusive-NOR operatio is performed to determine whether the second control character is present in any of the eight bytes of data i DATA1. If the second control character is found in DATA1, then at line 92 the program branches to memory location 400.
  • the instruction at line 94 is executed and the data i Register B is stored in a buffer. Thereafter, the syste proceeds to execute the instruction at line 80 and th process described above repeats. Thus, eight bytes ar checked for two different control characters with only two compare cycles in contrast to the 16 compare cycles required in prior art machines.
  • a "branch on no-hits” may be utilized as an alternative to the "branch on any hit” instruction, which branches to a memory location if none of the bytes in the data word contain the control character.
  • the Register A When the data is checked for more than one set of characters, the Register A may be reloaded with the characters for each compare sequence. However, to increase the execution speed, reloading the register may be avoided by various methods known to those skilled in the art.
  • An n- to-1 multiplexer may be substituted for the Register A, where n is the number of character sets to be searched for in the data. For example, if the data is to be searched for two sets of characters-, "EOS" and "CR,” a 2-to-l multiplexer may be utilized, with the registers • containing "EOS" and
  • CPU permits the selection of the desired register for input to the exclusive-NOR circuit. Instructions cause the CPU to route the contents of the selected register to the exclusive-NOR circuit. Alternatively, tri-state devices may be utilized.
  • an arithmetic logic unit (ALU) is utilized to perform the exclusive-OR function.
  • the End of Sector (EOS) or other control characters are loaded into the A register file.
  • the data which is to be searched for the End of Sector flag is loaded in register B via the B bus 172.
  • the EOS flag is input to the ALU through the A latch 142 and the data to be compared to determine whether it contains "EOS" characters is input to the ALU through B latch 144.
  • the ALU compares each bit of input from the A register to the corresponding bit of input from the B register. For each matching bit pair, the ALU will generate a zero on the respective output line.
  • the output of the ALU is input to the zero detect circuit (which comprises 8-input NOR gates) via the F bus 148.
  • the zero detect circuit determines whether all of the bits within a byte are zero.
  • a one is generated by the zero 5 detect circuit indicating that a particular byte from the A register matches the byte from the B register.
  • the foregoing embodiment utilizes inverse logic from the illustrative circuit shown in Fig. 3. In the circuit shown in Fig. 3, a zero is generated when the byte pairs match.
  • the processor includes a dual register file 120 comprising an A register file and a B register file. Although only nine registers are shown in each register file, each register file includes
  • the processor of Fig. 5 is for a 64 bit minicomputer, and so each of the registers in the A and B register files is 64 bits, or eight bytes, wide.
  • the A register file is shown to include an address register 122, a
  • the address register 122 is used to store the address of a data string, either a bit string or a character string, that is to be searched by the processor for a particular keyword.
  • the length register 124 is used to store the address of a data string, either a bit string or a character string, that is to be searched by the processor for a particular keyword.
  • the bit mask register 126 is used to store a desired pattern of bits that is used to mask the keyword. For example, the bit mask register 126 might be used to ignore capital letters so that the
  • the byte mask register 128 contains a desired pattern of bytes used to mask the keyword. For example, the byte mask register 128 might be used to ignore the second letter of a word so that the processor would
  • test register 130 contains the desired keyword after it has been masked with the desired byte mask.
  • the B register file contains a bit count register 132 and a byte count register 134 which, as is explained in more 5 detail hereinafter, determine when the next portion of the data string being tested for the presence of the keyword needs to be fetched from memory.
  • a keyword register 136 contains the binary data string corresponding to the desired keyword, and the end-of-string (END) flag register 138 0 ' contains a flag that indicates whether or not a data string has been completely searched for the presence of a desired keyword.
  • the A and B register files are connected to an arithmetic logic unit (ALU) 140 through an A latch 142 and a B latch 144, respectively.
  • ALU 140 is a conventional arithmetic logic unit, which in this embodiment may include
  • the arithmetic logic unit 140 performs various operations on the data supplied to its dual data inputs, depending upon the combination of binary signals supplied to its control inputs by an ALU function select circuit 146. For example, when the ALU 140 receives a particular combination of control inputs, the ALU 140 adds its two data inputs. In response to a different combination of its control inputs, the ALU 140 performs an exclusive-or operation on its data inputs.
  • the A and B register files are designed so that at any time, the binary information stored in each register is equal to the binary information stored in its adjacent register so that the A register file is a copy of the . B register file, and vice-versa.
  • This register organization speeds up the operation of the processor. In order to perform an operation on two operands, one operand must be - transmitted to the A latch 142 and the other to the B latch 144. If there were only an A register file, the processor would require an extra cycle to perform any given ALU operation.
  • the output of the ALU 140 is connected via an 64-bit- wide F-bus 148 to a zero-detect circuit 150 which detects when all the outputs of the ALU 140 are zero.
  • the ALU 140, ALU function select circuit 146, and zero detect circuit 150 are shown in detail in Fig. 7.
  • the ALU function select circuit 146 is shown functionally (in dotted lines) for purposes of explaining the invention. In reality, the function select circuit 146 is implemented with programmable array logic integrated circuits commercially available from Monolithic Memories, Inc. of Santa Clara, California, that are programmed with many equations that do not facilitate explanation.
  • the ALU comprises 16 separate, 4-bit '381 integrated circuit chips 152.
  • the data inputs of the ALU chips 152 that are connected to the A and B latches 142, 144 have been omitted from Fig. 7, and only the outputs of the chips 152 are shown.
  • Each pair of the chips 152 is connected to a respective multiplexer 154 which supplies the control inputs for the chips 152.
  • Each of the multiplexers 154 either supplies a desired 3-bit FUNCTION signal or a 3-bit CLEAR signal to the control inputs of the pair of chips 152 to which it is connected, depending upon the value of its address signal sent from a register 156 which stores the 8 bits of the byte mask.
  • the byte mask causes the processor to ignore certain bytes in the data string being searched so that, for example, the processor would equate the keyword "string” with the word “spring” in the data string, in which case the second bit of the byte mask would be set to logic "1" so that the "p” in "spring” is ignored. Similarly, if it were desired that the fourth letter of a word were to be ignored, the fourth bit of the byte mask would be set to logic "1.”
  • the multiplexers 154 either supply a specified FUNCTION signal or a CLEAR signal to the chips 152, depending upon whether the value of the particular bit of the byte mask in the register 156 is logic "1" or "0.” If the bit in the byte mask is logic "0,” the desired 3-bit FUNCTION signal is transmitted, and if the bit in the byte mask is logic "1,” the 3-bit CLEAR- signal is sent, which causes the outputs of the ALU chips 152 to which it is connected to be forced to logic "0.”
  • the zero detect circuit 150 comprises 16 NOR gates 158 connected to receive the outputs of the ALU chips 152.—The outputs of the NOR gates 158 are connected to eight AND gates 160, which in turn are connected to a pair of NAND gates 162 which are connected to a NOR gate 164.
  • the particular logic gates used in the zero detect circuit 150 are not important to the invention since other circuits could be easily designed to detect that all outputs of the ALU chips were logic "0," such as, for example, a single 64-bit NOR gate.
  • the F-bus 148 is connected to an A-bus 168 via a buffer 170 and a B-bus 172 via another buffer 174.
  • the zero-detect circuit 150 is coupled to the B-bus 172 through a buffer 176.
  • a memory 178 is connected to the bus 180 that connects the output of the A latch 142 to the ALU 140 through a buffer 182 connected to an M-bus 184. Because this embodiment is for a 64 bit minicomputer, the A-bus 168, the B-bus 172, and the M-bus 184 are also 64 bits wide.
  • a pair of serially connected 64-bit shift registers comprising a J shift register 186 and a K shift register 188 are connected to the B-bus 172.
  • a mask register 190 is connected to the J shift register 186 via a mask bus 192. As is explained in more detail below, these shift registers are used to store portions of the data string to be tested for the presence of a desired keyword.
  • a trio of control signals is supplied to each of the two shift registers 186, 188.
  • a LOAD signal causes the register to which it is attached to be parallel-loaded with a portion of a data string.
  • the data is loaded into the registers 186, 188 from the memory 178 through a data route consisting of the ALU 140, the F-bus 148, the buffer 174, and the B-bus 172.
  • a second signal SI causes its respective shift register to be shifted left one bit
  • a third signal S8 causes its respective shift register to be shifted left eight bits, or one byte.
  • Fig. 6 is a portion of a substantially functional equivalent of the J shift register 186 used for purposes of explaining the invention.
  • the actual embodiment of the J and K shift registers 186, 188 comprises specially programmed conventional programmable array logic integrated circuits commercially available from Monolithic Memories, Inc. of Santa Clara, California.
  • a portion of the J shift register 186 consisting of logic gates and flip-flops 196 is shown. Although only six flip-flops 196 are shown, the J shift register 186 is 64 bits wide and thus includes 64 serially connected flip-flops 196. In Fig. 6 the flip-flops
  • Each of the flip-flops 196 has a data input D connected to the output of a logic circuit 198 and a clock input C connected to receive a CLOCK signal that controls the speed of operation of the shift registers 186, 188.
  • the logic circuits 198 control the loading and shifting
  • Each of the logic circuits 198 comprises a three-input OR gate 200 and three two-input AND gates 202.
  • One of the AND gates 202a has a first input connected to one of the 64 lines of the B-bus
  • AND gate 202a in each of the logic circuits 198 causes the flip-flop to which it is connected to be loaded with the binary value of the B-bus 172 when the LOAD signal is activated, which occurs when the LOAD signal is logic "1."
  • the Si signal is activated to logic "1" while the LOAD and S8 signals remain at logic
  • Each AND gate 202c to which the SI signal is supplied has its other input connected to the output of the first 5 upstream flip-flop, "upstream" meaning the direction from which data is being shifted.
  • upstream meaning the direction from which data is being shifted.
  • upstream flip-flop is the first flip-flop to the right o the circuit element and the first "downstream” flip-flop i the first flip-flop to the left of the circuit element.
  • the output of the AN gate 202c to which it is connected is equal to the input o the upstream flip-flop. Since the output of the AND gat
  • the activation of the S signal causes the shift registers 186, 188 to perform a one bit logical left shift on the portion of the data strin stored therein.
  • the activation of the S8 signal causes an eight-bit, o one-byte, logical left shift to be performed by the shif registers 186, 188.
  • Each AND gate 202b to which the S signal is connected has its other input connected to th output of the eighth upstream flip-flop so that when the S signal is logic "1," the output of each of the flip-flop 196 is passed to the eighth respective downstream flip-flo so that the portion of the data string is shifted eight bit to the left.
  • Another portion of the J shift register 186 performs bit mask operation so that any desired bits of the strin being searched may be ignored. For example, as describe above, it might be desirable to ignore capital letters s that the processor would consider the letter "a" to b equivalent to the letter "A.”
  • the output o each of the flip-flops 196 is supplied to one input of two-input AND gate 204 having its other input connected t receive the output of a NAND gate 206.
  • One input of th NAND gate 206 is connected to receive a respective bit o the bit mask from the mask register 190 connected to the shift register via the mask bus 192.
  • the NAND gate 206 i also connected to receive a BIT MASK ENABLE signal tha selectively activates or deactivates the bit mask operation In particular, when the BIT MASK ENABLE signal is logic "0,” the outputs of all of the NAND gates 206 are forced to logic "1" so that the outputs of the AND gates 204 equal the output of the flip-flops to which they are connected and are not affected by the outputs of the NAND gates 206. However, when the BIT MASK ENABLE signal is logic .
  • each of these logic “0”s causes a forced match when the masked portion of the data string is compared to the keyword string by the processor.
  • the output of each of the AND gates 204 is connected to the B-bus 172 so that the masked or unmasked portion of the data string stored in the shift registers may be supplied to the ALU 140 for comparison to the keyword string.
  • bit masking functions are not important, and alternative logic could be used. For example, selected bits in a bit string could be masked off if the corresponding bits in the bit mask were logic "0" instead of logic "1” if the NAND gates 206 were replaced with OR gates, in which case the bit mask enable signal would be activated when logic "0" instead of logic "1.”
  • the functional circuit diagram of the K shift register 188 is substantially identical to the diagram of the J shift register shown in Fig. 6, except that the AND gates 204 and the NAND gates 206 used in connection with the bit mask and the BIT MASK ENABLE signal are not required since only the output of the J shift 186 register is sent to the ALU 140 for comparison to the keyword, as is explained in more detail below.
  • the processor compares a selected string of bytes to determine the presence of a selected keyword. Both the byte string and the keyword are selectable by the user of the processor.
  • the basic process by which the processor tests for the presence of a selected keyword string within a selected data string includes initially loading the J and K shift registers 186, 188 with the first portion of the data string to be tested. Then, the entire contents of the J shift register 186 are simultaneously compared with the keyword stored in the test register 130. If there is a match, the presence of a match is Indicated by the processor. Then, the contents of the J and K registers 186, 188 are shifted left one byte and the contents of the J register 186 are again compared with the contents of the test register 130. Any match is indicated, and the process is repeated.
  • the K register 188 will become empty since its contents are gradually shifted into the J register 186, and so the K register will be periodically reloaded with the next portion of the data string to be tested. In this manner, the entire keyword is simultaneously compared with a corresponding portion of the data string. This process reduces the number of comparisons required as shown by the example shown below, in which th keyword is "the,” the data string is "that time is the essence," and each number above the data string represents the number of comparisons that were required to determin whether or not the keyword matched that particular portio of the data string:
  • this particular example required 14 comparisons to find the keyword "the” in the character string "that time is the essence” in contrast to the" 21 comparisons that were required by a conventional data string processor as shown above. This reduction results from the entire keyword -23- simultaneously being compared with a portion of the data string, instead of being compared one byte at a time.
  • Fig.. 8 is a flowchart of the microcode that controls the operation of the processor shown in Fig. 5, and Table 1 includes a software program that is substantially functionally equivalent to the microcode actually used. The operation is explained with reference to Table 1 and not the
  • the binar representation of the keyword is stored in the keywor
  • the address of the byte string in memory 17 to be searched is stored in the address register 122, an the length in bytes of the byte string being searched i stored in the length register 124.
  • step 40 whether or not the data string has been completely searche for the presence of the keyword.
  • step 212 of Fig. 8 the value of the END flag is reset to indicate that the end of the string has not yet been reached.
  • step 214 the keyword is masked with the bit mask to ensure that the processor ignores any bits in any desired byte as selected by the user. This step is carried out by instructions 2-5 of Table 1. Instructions 2 and 3 supply the bit mask to one data input of the ALU 140 and the keyword to the other data input.
  • Instruction 4 causes the appropriate control signal to be supplied to the ALU so that its two data inputs are logically "anded” together, and the ALU output, which is the value of the masked keyword, is stored in the test register 130 in the A register file via a data path ' consisting of the F-bus 148, the F-A bus buffer 170, and the A-bus 168.
  • the ALU output which is the value of the masked keyword
  • the J shift register 186 is loaded with the first word of the data string to be tested, "word” meaning a block of binary data eight bytes long to correspond to the eight byte width of the J shift register 186.
  • the step 216 is accomplished by instruction 6 in Table 1 which moves the contents of the memory at the address where the data string is stored to the J shift register 186 through a path including the memory buffer 182, the M-bus 184, the ALU 140, the F-bus 148, the F-to-B buffer 174, and the B-bus 172.
  • the next word, or eight bytes, of the data string are loaded into the K shift register 188 from the memory 178 in a similar manner by instructions 7-11.
  • instructions 7-10 cause the address to be incremented by eight so that the incremented address will point to the next eight bytes of the data string in memory 178. Then instruction 11 causes the next eight bytes to be fetched from memory 178 and put into the K shift register 188 via the same data path as described in connection with the loading of the J shift register 186.
  • the numeric value eight is stored in the byte count register 134 since there are now eight bytes of string data in the K register 188. Because the contents of the K register 188 are periodically shifted left into the J shift register 186, it is important to know 0 how many bytes of the data string are left in the K register 188 so that the processor will known when to reload the K register with the next portion of the data string.
  • step 222 the masked keyword stored in the test register 130 is compared to the portion of the data 5 string stored in the J register 186.
  • This step is implemented by the instructions 13-16 of Table 1. Specifically, instruction 13 causes the masked keyword stored in the test register 130 to be sent to the A latch 142. Then, instruction 14 causes the contents of the J B shift register 186 to be moved to the B latch 144 via the B- bus 172. If the BIT MASK ENABLE signal is logic "1," then the contents of the J register 186 are logically "anded” with the bit mask by the AND gates 204 prior to being sent to the B latch 144. At instruction 15 of the binary value
  • bit-by-bit logical exclusive-or provides a logic "0" output if its two bit inputs are both logic “1” or logic "0,” and hence match, and a logic "1" output if its two bit inputs are different.
  • the processor proceeds to the user's program so that the user program may perform its programmed function, for example, replace the keyword that was located with a different word, whereupon the user program returns control to the processor so that any other occurrences of the keyword can be found.
  • the existence of a match is determined by the zero detect circuit at instruction 16. Instruction 16 causes the contents of the ALU 140 to be sent to the zero detect circuit 150. As mentioned above, for each byte position of the ALU 140 in which there was a match, the ALU output will be zero.
  • the zero detect circuit 150 tests each byte of the ALU to determine whether all bytes are zero, in which case all unmasked bytes of the keyword match all unmasked bytes of the data string portion.
  • the ALU output corresponding to each masked byte is forced to logic "0," which is the same logical output that the ALU provides in case of a match.
  • each logic "1" bit in the byte mask forces a match in its corresponding byte position in the keyword.
  • instruction 18 Upon a match, instruction 18 will cause a return to the user's program, and the user program will return control to the processor at instruction 19.
  • instruction 17 will cause instructions 18 and 19 to be skipped.
  • the length of the data string will be decremented by one byte since one byte has just been tested and thus there is one less byte in the data string that needs to be tested.
  • This step is implemented by instructions 20-23.
  • Instruction 20 causes the number one to be moved to the B latch 144, and instruction 21 causes the current data string length to be sent to the A latch 142.
  • I ⁇ struction 22 causes the ALU 140 to subtract one from the current length, and the new length is stored in the length register 124 by instruction 23.
  • step 2208 the new data string length stored in the length register 124 is tested to determine whether all of the bytes in the data string have already been compared to the keyword, which will be the case if the numeric value of the length is zero. This is accomplished at instruction 24 which sends the output of the ALU 140 to the zero detect circuit 150. If the value of length is zero, then step 230 is executed, causing the END flag to be set to logic "1" to indicate that the end of the string has been reached, and control is returned to the user's program. This is accomplished by instructions 26 and 27.
  • step 232 the program branches to step 232 at which the contents of the J and K registers 186, 188 are shifted left by one byte. This is accomplished by instruction 28, which causes a logic M l" S8 signal to be sent to the shift registers 186, 188 so that their contents are shifted left one byte as explained above.
  • the contents of the byte count register 134 are then decremented by one at step 234 to indicate that there is one less byte in the K shift register 188 since it has just shifted one of its bytes into the J shift register. This step is accomplished by instructions 29-31.
  • step 236 the numeric value of byte count is tested to determine if it is zero, in which case the next eight bytes of the data string need to be moved from the memory 178 into the K shift register 188, and so the program branches back to step 218 so that the K shift register 188 is reloaded. If the byte count is nonzero, the shift register 188 does not need to be reloaded, and the program register 188 does not need to be reloaded, and the program branches to step 222 so that the current portion of the data string in the J register 186 may be compared to the masked keyword.
  • Step 236 is executed by instructions 32-35.
  • r ⁇ struction 32 causes the contents of the ALU 140 to be sent to the zero detect circuit 150. If the zero detect circuit 150 detects a zero, instruction 33 causes a branch to instruction 7. Instruction 34 saves the decremented value of the byte count if it is nonzero, and instruction 35 causes a branch back to instruction 13.
  • the bit mode of operation of the processor is generally similar to its byte mode of operation. In its bit mode of operation, the processor compares a selected string of bits to determine the presence of a selected keyword. Both the bit string and the keyword are selectable by the user of the processor.
  • the basic process by which the processor tests for the presence of a selected keyword within a selected bit string includes initially loading the J and K shift registers 186, 188 with the first portion of the bit string to be tested. Then, the entire contents of the J shift register 186 are simultaneously compared with the keyword stored in the test register 130. If there is a match, the presence of a match is indicated by the processor.
  • the contents of the J and K registers 186, 188 are shifted left one bit and the contents of the J register 186 are again compared with the contents of the test register. Any match is indicated, and the process is repeated.
  • the K register 188 will become empty since its contents are gradually shifted into the J register 186, and so the K register 188 will be periodically reloaded with the next portion of the bit string to be tested. In this manner, the entire keyword is simultaneously compared with a corresponding portion of the bit string.
  • this particular example required only 1 comparisons to find the keyword "1101" in the bit strin "11001110011011” in contrast to the 22 comparisons tha were required by a conventional bit string processor a shown above. This reduction results from the entire keywor simultaneously being compared with a portion of the bi string, instead of being compared one bit at a time.
  • bit mode of the processo is very similar to the byte mode, and can be understood wit reference to Fig. 9 and Table 2 set forth below.
  • Fig. 9 which is a flowchart of the microcode that controls th operation of the processor, is very similar to the flowchar of Fig. 8, except that in a number of instances differen operations are executed since the processor is in its bi mode of operation and not its byte mode.
  • th software implementation set forth in Table 2 is very simila to that of Table 1, so that only the differences need b explained to provide a clear understanding of the detailed operation of the bit mode of operation.
  • the contents of the bit count register 132 are set to 64 since the K shift register 188 will be shifted one bit at a time and 64 bits are initially loaded into the K register 188.
  • the contents of the J and K shift registers 186, 188 are shifted left one bit instead of byte.
  • the contents of the bit count register 132 instead of the byte count register 34 are decremented by one.
  • the conditional branch occurs when the value of the bit count register 132 has reached zero, and not the byte count register 134.
  • the two modes of operation just described are invoked by-a user by including appropriate software instructions in the user's program. Specifically, the byte mode of operation is invoked by the instruction "SCANS” and the bit mode of operation is invoked by the instruction "BITSCAN.”
  • Two further embodiments of the invention are identical to the embodiment just described, except that they are directed towards 16 and 32 bit parallel processors, respectively.
  • the differences between these embodiments include the data width of the buses, buffers, ALU, A and B latches, and registers. Otherwise, the operation, of these additional embodiments is the same.

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Abstract

Un processeur destiné à être utilisé dans un système informatique sert à comparer simultanément un certain nombres d'octets, afin de localiser un caractère de commande dans une chaîne de données. Ledit processeur comprend un registre contenant les octets de données (REGB), un registre dans lequel sont stockés les caractères de commande (REGA), un circuit de comparaison (CMP), destiné à comparer simultanément les octets de données stockées dans les deux registres, et un circuit servant à produire des bits indicateurs en cas d'égalité (100). Dans un autre aspect de la présente invention, un processeur de traitement de chaîne en parallèle comporte un premier registre (136), dans lequel est stockée une chaîne de mots-clé, et une paire de registres à décalage interconnectés (186 et 188), dans lesquels est stockée la chaîne à rechercher pour déterminer la présence du mot-clé. Une unité logique arithmétique (ALU) (140) compare les registres à décalage pour déterminer si le mot-clé est présent dans la partie de la chaîne en cours de recherche. Après chaque comparaison, le contenu des registres à décalage interconnectés est décalé par rapport au mot-clé stocké dans le premier registre. Lorsque le processeur est en mode de recherche pour déterminer la présence d'un mot-clé comportant un nombre prédéterminé d'octets, le contenu du registre à décalage est décalé d'un octet à la fois et, lorsque le processeur est en mode de recherche pour déterminer la présence d'un mot-clé comportant un nombre prédéterminé de bits, le contenu du registre à décalage est décalé d'un bit à la fois.
PCT/US1988/001119 1987-08-20 1988-04-07 Processeur et procede de traitement de chaine en parallele pour micro-ordinateur WO1989001653A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
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WO1994029790A1 (fr) * 1993-06-14 1994-12-22 Apple Computer, Inc. Procede et dispositif permettant de trouver un caractere d'arret dans une chaine de caracteres de longueur variable dans un processeur
EP0907146A2 (fr) * 1997-09-25 1999-04-07 Xerox Corporation Dispositif de compression de données utilisant la comparaison de chaínes

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994029790A1 (fr) * 1993-06-14 1994-12-22 Apple Computer, Inc. Procede et dispositif permettant de trouver un caractere d'arret dans une chaine de caracteres de longueur variable dans un processeur
EP0907146A2 (fr) * 1997-09-25 1999-04-07 Xerox Corporation Dispositif de compression de données utilisant la comparaison de chaínes
EP0907146A3 (fr) * 1997-09-25 2000-03-01 Xerox Corporation Dispositif de compression de données utilisant la comparaison de chaínes

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EP0395636A4 (en) 1991-10-16
EP0395636A1 (fr) 1990-11-07
KR890702109A (ko) 1989-12-22

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