WO1989001204A1 - Acces en memoire pour systeme d'ordinateur - Google Patents

Acces en memoire pour systeme d'ordinateur Download PDF

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Publication number
WO1989001204A1
WO1989001204A1 PCT/US1988/002453 US8802453W WO8901204A1 WO 1989001204 A1 WO1989001204 A1 WO 1989001204A1 US 8802453 W US8802453 W US 8802453W WO 8901204 A1 WO8901204 A1 WO 8901204A1
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WO
WIPO (PCT)
Prior art keywords
memory array
microprocessor
cycle
computer system
bit
Prior art date
Application number
PCT/US1988/002453
Other languages
English (en)
Inventor
Alan Carl Smiley
Original Assignee
Ncr Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ncr Corporation filed Critical Ncr Corporation
Priority to KR1019890700520A priority Critical patent/KR890702135A/ko
Publication of WO1989001204A1 publication Critical patent/WO1989001204A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison

Definitions

  • This invention relates to computer systems of the kind including processing means, a memory array and addressing means adapted to address said memory array.
  • microprocessors formerly operated at clock rates nominally ranging between four and seven megahertz, and occasionally extending to the ten megahertz range
  • the newer devices are capable of operating at clock rates in the range of twenty megahertz or faster. Consequently, such advanced microprocessors are capable of communicating with other devices or memory at frequencies approaching the clock rate when the operations performed within the microprocessor involve relatively few clock cycles.
  • the addressing/accessing of a memory in the execution of a read or write cycle is an example of an operation which entails relatively few, typically two, clock cycles to complete, and consequently can operate at approximately one half the clock rate.
  • Another aspect of the technological evolution which bears upon the present invention is the exponential increase in the bit length of the words handled by the microprocessor.
  • early microprocessor address, instruction and data words were four bits in length, evolving soon thereafter to microprocessors using eight bit words, sixteen bit words, and most recent thirty-two bit length words.
  • the more recent sixteen and thirty-two bit word microprocessors have included the capability to operate software utilizing eight bit words, recognizing that eight bit word length software will be commonly used for an extended period of time.
  • sixteen bit and thirty-two bit word personal computer systems namely those capable of handling such bit lengths in the microprocessor and memory array, and on the data and the address buses, will frequently be operated with software which addresses and utilizes only eight bit long word segments of the memory array structure.
  • the complete thirty-two bit segment of the memory array word is considered to require a precharge cycle.
  • memory access control systems have been configured to introduce "wait" cycles into the timing sequence, thereby causing the microprocessor to sit idle while the memory array is completing its precharge cycle. Obviously such idle periods of the microprocessor reduce the personal computer system's effective data processing rate.
  • a computer system of the kind specified characterized in that said memory array includes m individually addressable segments, an n-bit output bus means, and operates under a defined access repetition rate-, in that said addressing means is adapted to selectively address said segments to selectively provide p output words of q-bit length on said n-bit output bus means, wherein n is 2q or greater; and by wait state generation and timing logic means adapted to effect a comparison between the segment selectively addressed during a first processor memory address cycle and a segment to be selectively addressed during a succeeding second processor memory address cycle, to detect correspondence of selectively addressed segments, and to generate a wait signal for said processing means, whereby accessing of said memory array in said second processor memory address cycle is delayed.
  • a further advantage of a computer system according to the invention arises for computer architectures in which the memory array is significantly slower than the microprocessor, since "wait" delays are particularly significant for such computer architectures.
  • Fig. 1 is a schematic diagram of a memory array with "wait" state detection/ generation circuitry.
  • Figs. 2A and 2B together comprise a block diagram schematically illustrating a preferred embodiment of the present invention as used to generate "wait" states and related microprocessor timing and control signals.
  • Fig. 3 schematically illustrates representative timing waveforms for the invention embodied in Figs ⁇ 2A and 2B using signal voltage versus time plots.
  • Fig. 4 schematically illustrates a memory array bank select circuit.
  • Figs. 5 and 6 schematically illustrate logic for latching and comparing the bank, previous byte, and next succeeding byte signals to generate a "wait" state request signal.
  • Fig. 7 illustrates logic for combining the "wait" state request signals with the clock signals to define the memory array row and column strobe signals.
  • Figs * 8 and 9 schematically illustrate logic for combining memory array bank select signals and segment select signals with strobe signals to address individual byte size data word segments of a four byte size data word memory array.
  • Fig. 1 The signals emanating from a microprocessor ⁇ not shown) and other conventional elements of a personal computer are, in the identification symbols of Fig. 1, clock signals CLOCK suitable to synchronize the memory accessing logic, a READY signal to inform the microprocessor that the desired segment of the memory array is available for an access cycle, a MEMS signal from the microprocessor to request access to " the memory array, the bank select signals SELA and SELB, a set of memory array address signals A0-A27, and a set of thirty-two bit wide memory array output signals on data lines D0-D31 of a common thirty-two bit data bus.
  • the memory array 1, Fig. 1 is comprised of two distinct banks, bank A at 2 and bank B at 3, and utilizes a data word thirty-two bits in length for each bank.
  • the individual banks are accessed by the coincidences of address words A3-A20 on bus 4 and respective row and column strobe signals on lines such as bank A strobe lines 6 and 7.
  • the memory array output words are identified as bits D0-D31 and appear on the common computer system output bus 8.
  • each successive access cycle of memory array 1 is initiated by a microprocessor memory access request signal MEMS.
  • MEMS signal causes a comparison to occur within wait state detection logic block 9, wherein the previously addressed bank and the bank to be addressed are identified and compared. If a coincidence of successive bank addresses is detected, the need for a "wait" cycle is transmitted to timing generator block 11. Timing, generator block 11 then disables the row and column strobe signals normally generated, on lines 12 and 13, and conveys a complement of the READY signal to the microprocessor as indication of the fact that memory array 1 is not available for the desired access cycle.
  • DRAM dynamic random access memories
  • bank A and bank B in Fig. 1 The effects of using memory array devices, commonly dynamic random access memories (DRAM), which are slow in relation to the clock frequency of the microprocessor are somewhat lessened by using the multiple banks illustrated, bank A and bank B in Fig. 1, by selectively organizing the software data addresses so that normal program execution results in access addresses which successively alternate from bank to bank. In this way while one bank is being addressed, the other is given an opportunity to complete its precharge operation. Jump, call and other branching operations result in address sequences which often diverge from the prescribed norm and therefore require the insertion of "wait" cycles.
  • the DRAMs are faster than the microprocessor, there is be no need for multiple banks or memory array initiated "wait" cycles.
  • the use of relatively slow DRAMs in relation to the clock rate of the microprocessor requires the inclusion of wait cycles which extend for multiple microprocessor clock cycles.
  • the use of eight bit length data words in memory array 1 would preferably involve an analogous memory allocation practice by which such words are placed into successive byte size segments, such as 17, 18, 19 and 21, of bank A. Eight bit words, are then individually accessed by microprocessor using bank and segment addresses. However, according to the architecture in Fig. 1, each time an eight bit word is to be addressed, for example the byte comprised of data bits D8-D15 in DRAM 18, a "wait" state evaluation is undertaken for the whole of bank A. Particularly slow microprocessor operation results for eight bit software loaded into and accessed in successive eight bit segments, such as 17, 18, 19 and 21, of memory array 1 in that a "wait" cycle would be added for each byte size access of memory array bank A.
  • the wait state generation and timing logic provides. the user of a personal computer having an advanced technology microprocessor, characterized by high operating speed and extended data bus of, for example, thirty-two bits, with the ability to utilize eight bit software at or near the clock rate of the microprocessor while using somewhat slower DRAM devices. This is accomplished by individualizing the "wait" state evaluation to encompass byte size segments of the memory array, yet retaining a bank select architecture and associated thirty-two bit wide data bus and data word operating capability.
  • the architecture is configured to be transparent to the software whether composed of eight bit, sixteen bit, or thirty-two bit long words of standard convention.
  • the embodiment illustrated in the composite of Figs. 2A and 2B is based upon a computer system in which the memory array is capable of executing a precharge cycle in less than two microprocessor clock cycles.
  • a "wait" cycle is thereby defined to be a single, second, clock cycle.
  • the relative speed of the microprocessor in relation to the access rate of the memory array determines the number of microprocessor clock cycles over which a "wait" cycle must extend, which relationship is prescribed by the computer system designer.
  • the logic schematics which prescribe the elements internal to each block are depicted in Figs. 5-9, the correspondence being individually indicated in each block.
  • Representative waveforms for the signals present on the various interconnecting lines are schematically illustrated in Fig. 3. The waveforms are shown with reference to a set of microprocessor clock, memory request, and address signals.
  • wait state detection logic block 26 The elements within and functions performed by wait state detection logic block 26 can most effectively be understood by considering the combination of Figs. 2A, 2B, 3, 5 and 6.
  • One set of inputs to wait state detection logic block 26 is the group of byte select signals on four line bus 27, which according to this implementation individually identify which of eight bit' size segments 29, 31, 32 or 33 from bank A, or 34, 36, 37 or 38 from bank B, are to be accessed ' . For instance, if the eight bit data word D8-D15 is to be addressed, the second byte select line, BS1 is set to a low signal level while the other byte select lines remain at high signal levels.
  • the choice of memory array banks, A or B is defined by the signal levels on bank select lines SELA and SELB, which as illustrated in Fig.
  • a signal on MEMS line 39 in Fig. 2A represents a request by the microprocessor for access to the memory array, and as such initiates within wait state detection logic block 26 the determination of whether the memory array, access strobes should be commenced with the immediately succeeding clock cycle or be delayed by a wait cycle.
  • the clock input, generally line 41, is the microprocessor clock of +C1K and the complement -C1K.
  • the remaining signals analyzed by wait state detection logic block 26 are the bank A and bank B column address strobe lines, respectively by bank, ACAS0-ACAS3 and BCAS0-BCAS3.
  • Fig. 5 depicts one functional element present in wait state detection logic block 26, shown to be a positive going edge triggered hex D type flip-flop 42 for latching the binary states represented by the signals on SELA, SELB and BS0-BS3 to form latch equivalents on output lines distinguished by the prefix "L".
  • the latched outputs on lines LSELA and LBS0-LBS3 are provided as input signals to bank A driver block 43, while latched outputs LSELB and LBS0- LBS3 are provided as the input signals to bank B driver block 44.
  • the remaining outputs from wait state detection logic block 26 in Fig. 2A are generated by the combination of the logic-elements depicted in Fig. 6, providing as outputs binary signals on respective TO and TW lines 46 and 47.
  • TO is at a low signal level while the MEMS signal is at a high level
  • access to the memory array is permissible and undertaken.
  • TW signal is low when MEMS signal is at a high level, accessing is prohibited in that the memory array segment selected for accessing was accessed in the previous microprocessor cycle and as a consequence requires a wait cycle to complete precharge.
  • Timing generator block 48 also receives microprocessor clock signals and uses those clock signals, as illustrated in Fig. 7, to synchronize D- type flip-flops 49 and 51 for holding wait request signal TO and TW, and to synchronize the generation of the master row address strobe signal TRAS on line 52 from flip-flop 53 and master column address strobe signal TCAS on line 54 from flip-flop 56. Timing generator block 48 also generates on line 57 a READY signal for the microprocessor, which signal if low represents to the microprocessor the unavailability of the memory array for that clock interval.
  • wait state detection logic block 26 and timing generator block 48 can be more comprehensively understood from an analysis of the waveforms illustrated in Fig. 3.
  • a first condition where no wait state is to be requested
  • a second condition where a one clock cycle wait state is to be requested.
  • the events to be described commence with microprocessor cycle n + 1, following the onset of the MEMS signal rise to indicate the desire for a memory access by the microprocessor.
  • the memory array address signals A2- A27 and memory array segment select signals BS0-BS3 stabilize to define both the bank and segment desired.
  • This new memory array access information overlaps in time the trailing edge of any previously initiated column strobe by segment, ACAS0-ACAS3. Consequently, during the concluding time interval of each microprocessor cycle there coexists, for purposes of analysis in determining the need for a wait cycle, information regarding the new and previously accessed memory array segments.
  • Such new bank and segment addresses, as well as the previously addressed segment information embodied in the strobe signal is compared by the logic in Fig. 6 to detect correspondence. Note that during the n + 1 microprocessor cycle the logic in Fig. 6 causes the signal on line ' TO to transition to a low state, representing the absence of any need for a wait cycle.
  • the logic functions incorporated into drivers blocks 43 and 44, as depicted in Fig. 2A, are respectively shown by schematic in Figs. 8 and 9.
  • the logic elements in Fig. 8 provide as outputs the row and column strobe signals directed to bank A DRAM segments 29, 31, 32 and 33 (Fig. 2B) .
  • Each segment of the memory array is independently strobed.
  • segment 31 of the memory array is strobed by ARAS 1 and ACAS 1 for segment selective accessing in response to address signals on address bus 4, composed of lines A3-A20, to provide byte size output data from the memory array 5 on common data bus 10 lines D8-D15. Note "that the logic depicted in Fig.
  • Fig. 8 synchronizes the individual segment strobe signals to the master row and column strobe signals TRAS on line 52 and TCAS on line 53, while selecting the bank A by the presence of an LSELA signal and selecting the memory array segment by the presence of an appropriate LBS1 signal.
  • the configuration in Fig. 8 further provides for the ability to simultaneously strobe two or more segments of the memory array in order to simultaneously read two or more byte size words onto common data bus 10.
  • the strobing of bank A could include a concurrent enablement of segments 29 and 31, or 32 and 33 by signals on lines LBSO and LBS1, or LBS2 and LBS3, to provide sixteen bit data words onto the common thirty-two bit data bus 10.
  • Bank B is operated in analogous fashion using the corresponding set of logic devices- depicted in Fig. 9 and the common master row and column strobe signals TRAS and TCAS.
  • the wait state detection logic depicted in Fig. 6 evaluates the levels of he strobe signals at the conclusion of each microprocessor cycle for all eight memory array segments, and individually compares these with the bank and segment identifications for the next succeeding microprocessor memory array access cycle. Thereby, an attempt to successively access the same memory array segment, singly or in combination with other segments, during two successive microprocessor cycles result in the generation of a wait request upon the onset of the latter microprocessor cycle.
  • the memory array 5 is divided into segments individually providing byte size data words, and is contemplated to operate with byte or- multiple byte word length software.
  • the underlying concepts are not so restricted in that the memory array could be divided into segments providing shorter word length data, for example four bit words, and could be accessed in diverse combinations of segments so defined.
  • a consideration of the wait state detection logic depicted in Figs. 5 and 6 of the timing generator logic depicted in Fig. 7, and the driver logic depicted in Figs. 8 or 9 clearly evidences that extensions of the invention to greater segmentations of the memory array, including segments of differing proportions, can be implemented without unduly complicating the present logic structure.
  • the memory 5 has m individually addressable segments
  • the common bus 10 is an n-bit bus
  • the m individually addressable segments selectively provide p output words of q-bit length on the n-bit bus 10, where n is 2q or greater.
  • refinements can be readily adjusted by extension of the wait state cycle to compensate for selected differences in the speeds of the microprocessor and memory array. From a practical perspective, however, the most important consideration is that these refinements allow the end user to utilize software of differing word length without materially degrading the computer speed as fundamentally defined by the microprocessor, and doing so in the context of a computer architecture which is fundamentally transparent to such refinements.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Dram (AREA)

Abstract

Un système d'ordinateur utilisant un mircroprocesseur à haute vitesse et à longueur de bit étendue comprend une mémoire en réseau (5) qui est segmentée pour pouvoir être adressée par des mots mais partage un bus commun de données de mots multiples. Le système d'ordinateur comprend en outre un circuit logique (26) pour générer sélectivement et synchroniser dans le temps des signaux d'état d'attente pour le microprocesseur. Le circuit logique (26) est sensible à une requête d'accès en mémoire par le microprocesseur. La requête d'accès en mémoire est considérée conjointement aux informations antérieures d'accès du microprocesseur pour déterminer si le même segment du réseau de mémoire (5) doit être adressé pendant le cycle suivant d'accès au réseau de mémoire. Si une coïncidence de segment est détectée, un cycle d'attente est initié pour retarder l'accès au réseau de mémoire. Le cycle d'attente peut être un cycle unique d'horloge de microprocesseur ou des multiples de cet intervalle de temps. Le circuit s'applique à un système d'ordinateur ayant un microprocesseur avec une fréquence des cycles plus rapide que la fréquence de répétition d'accès au réseau de mémoire et qui utilise un logiciel de longueur différente de mots de données.
PCT/US1988/002453 1987-07-23 1988-07-20 Acces en memoire pour systeme d'ordinateur WO1989001204A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890700520A KR890702135A (ko) 1987-07-23 1988-07-20 컴퓨터 시스템

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US7664687A 1987-07-23 1987-07-23
US076,646 1987-07-23

Publications (1)

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WO1989001204A1 true WO1989001204A1 (fr) 1989-02-09

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PCT/US1988/002453 WO1989001204A1 (fr) 1987-07-23 1988-07-20 Acces en memoire pour systeme d'ordinateur

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EP (1) EP0324016A1 (fr)
JP (1) JPH02500143A (fr)
KR (1) KR890702135A (fr)
WO (1) WO1989001204A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0590967A1 (fr) * 1992-10-01 1994-04-06 Hudson Soft Co., Ltd. Contrôle de cycle d'attente sur un bus d'un système de traitement d'information
US5307470A (en) * 1988-11-25 1994-04-26 Nec Corporation Microcomputer having EEPROM provided with detector for detecting data write request issued before data write operation responsive to preceding data write request is completed

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2238191A1 (fr) * 1973-07-19 1975-02-14 Int Computers Ltd
EP0226950A2 (fr) * 1985-12-23 1987-07-01 Kabushiki Kaisha Toshiba Circuit de commande d'accès en mémoire

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2238191A1 (fr) * 1973-07-19 1975-02-14 Int Computers Ltd
EP0226950A2 (fr) * 1985-12-23 1987-07-01 Kabushiki Kaisha Toshiba Circuit de commande d'accès en mémoire

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5307470A (en) * 1988-11-25 1994-04-26 Nec Corporation Microcomputer having EEPROM provided with detector for detecting data write request issued before data write operation responsive to preceding data write request is completed
EP0590967A1 (fr) * 1992-10-01 1994-04-06 Hudson Soft Co., Ltd. Contrôle de cycle d'attente sur un bus d'un système de traitement d'information

Also Published As

Publication number Publication date
JPH02500143A (ja) 1990-01-18
EP0324016A1 (fr) 1989-07-19
KR890702135A (ko) 1989-12-22

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