Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04M—TELEPHONIC COMMUNICATION
  • H04M3/00—Automatic or semi-automatic exchanges
  • H04M3/005—Interface circuits for subscriber lines
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
  • H04B1/40—Circuits
  • H04B1/54—Circuits using the same frequency for two directions of communication
  • H04B1/58—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
  • H04B1/586—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa using an electronic circuit

Definitions

• the present invention relates to an apparatus for providing a controllable line termination impedance for a subscriber line circuit.
• the subscriber line circuit comprises two units, a two wire-four wire converter, i.e. a so-called subscriber line interface circuit (SLIC) and a subscriber line adapting circuit, i.e. a so- called subscriber line audio processing circuit (SLAC).
• SLIC subscriber line interface circuit
• SLAC subscriber line audio processing circuit
• the general task of subscriber line circuits is to connect and form the interface for a telephone line towards a telephone exchange.
• the line circuit can serve several telephone lines to the exchange.
• Incoming two wire connection to the subscriber are converted in the SLIC circuit to a four wire connection towards the following SLAC circuit, where analogue-digital conversion and recoding to PCM is carried out.
• In the SLAC circuit there are furthermore a balancing impedance and an impedance filter.
• This impedance filter should have a value such that the impedance, which from the subscriber line is "seen" towards the line circuit, meets the requirements which are placed on it inter alia by the telephone authorities.
• a prior art line circuit with the above mentioned SLIC and SLAC circuits is described in the EP-B-54024, for example.
• a line circuit with a complex impedance for adapting to a subscriber line is described in the US-B-4,558,185.
• This known line circuit includes a complex impedance with capacitive character for adapting the impedance of the line circuit to the side tone characteristic of the subscriber apparatus, apart from adapting the subscriber line to the two wire-four wire junction, i.e. the SLIC circuit.
• the present invention intends, as well as the above mentioned line circuit according to US-B-4,558,185, to provide a complex impedance in the line circuit for simulating a desired input impedance seen from the two wire side.
• the impedance filter included in the SLAC 5 circuit is utilized to form the complex part in the input impedance, which is furthermore made controllable by controlling the filter coefficients included in the digital impedance filter.
• an analogue part in tfe form of an analogue feedback provided before the analogue-digital and digital-analogue interface in the SLAC circuit.
• the object of the present invention is thus to provide a complex line 1.5 termination impedance for a telephone line circuit, the impedance properties of which can be controlled in accordance with the requirements placed on the transmission between subscriber and line circuit without needing to resort to any alteration in the hardware.
• Figure 1 illustrates a simple circuit diagram of an impedance
• Figures 2a-2d are different diagrams of the voltage and current in the diagram according to Figure 1
• Figure 3 is a block diagram of an 25 apparatus in accordance with the invention, together with closely associated circuits
• Figure 4 is a block diagram of an impedance filter and contiguous blocks included in the block diagram according to Figure 3
• Figures 5a-5f are the current diagrams for the impedance filter according to Figure 4.
• Figures 1 and 2a-2d are referred to for more closely explaining the idea and advantages of the invention.
• Figure 1 is a schematic diagram of an impedance Zi.
• a voltage pulse U of a sinusoidal configuration according to Figure 2a occurs across the impedance Zi a current pulse is obtained through it. If Zi is real (resistive) the current pulse has the same appearance as the voltage pulse U-, , see Figure 2b. If Zi is complex the current pulse will be changed.
• Figures 2c, 2d illustrate the current pulse i when the impedance Zi consists of a resistance-capacitance network. Positive and negative pulses of different appearances are obtained according to Figures 2c and 2d, depending on how the capacitance in Zi is connected, and on the values of the respective resistance and capacitance.
• the current may be said to comprise a part (the positive part) which does not have any delay and a part (the negative part) which is given a given delay relative to the applied voltage pulse U.
• the apparatus in accordance with the invention is intended to simulate this when Zi is the input impedance to a line circuit seen from the two wire side.
• FIG. 3 shows a block diagram of the proposed arrangement, together with contiguous circuit blocks in the line circuit.
• a two wire-four wire converter SLIC has a two wire input across which the voltage U occurs. The voltage U gives rise to a current ⁇ .
• An outgoing four-wire connection (ground is not shown) together with an incoming four wire connection connects the SLIC block to a SLAC circuit. Between the two four wire connections there has been connected an analogous block A with the transfer function Ha.
• the output of the block A is connected to a resistor R in the second four-wire connection via an adding circuit Al
• the block A can comprise a controllable voltage divider or a controllable amplifier for enabling variation of the amplitude of the voltage which is sent to the adding circuit Al.
• a resistor R. is connected between both four-wire branches. There is thus obtained greater freedom for selecting Z., since the resistor R is already fixed to a given value for maintaining prescribed signal levels in the SLAC circuit and across the input to the SLIC circuit.
• the block inclosed by dashed lines in Figure 3 and designated SLAC, is known per se, and is described in detail in the above-mentioned EP-B-54024.
• the analogue-digital converter AD the decimation filter D in one four wire path, with the interpolation filter I and digital-analogue converter DA in the other four wire path.
• the impedance filter Z and the adding circuit A2 are also included in the known SLAC circuit, but at the same time they are a part of the present apparatus together with the block A in the way described hereinafter.
• a coefficient memory M e.g. a RAM, for storing the coefficients to the impedance filter Z is included in the SLAC circuit, but is extended for also being able to store the values for controlling the block A, as described hereinafter.
• the impedance filter Z has a transfer function H-. If it is further assumed that the transfer functions of the units AD, D, I and DA are H A n > H D , H, and H DA , respectively, the input admittance Yi is obtained as
• H . . . H . . H ⁇ . H n is only dependent on the frequency and where I and U are the complex values of i and u respectively.
• the Input admittance Yi to the SLIC-SLAC circuit thus comprises two parts. A first part, which does not give any delay and which is proportional to Ha and 1/R. , and a second part which is dependent on Z.
• the part which does not give any delay comprises an uncontrollable part proportional to 1/R fc and a controllable part proportional to Ha, c.f. Figures 5a and 5b.
• By varying (controlling) the block A there is obtained control of the part which corresponds to Figure 5B, and by controlling Z there is obtained control of the delayed part according to Figures 5c-5f . Since the impedance filter Z is already in the block SLAC, there is only required an addition of the block A and possibly the resistance R.
• FIG. 4 shows in more detail the design of the controllable impedance filter Z in the case where it comprises a four-tap filter.
• the filter Z is implemented conventionally with three delay units DL1-DL3, four controllable multipliers Mo-M3 and an adding circuit A3.
• the input signal to the filter Z is connected to 5 the input of the multiplier MO and to the delay unit DLL
• the delay units DL1- DL3 have a delay equal to V and have their outputs connected to inputs of the mulitpliers M1-M3.
• the adding circuit A3 sums the output signals from the multipliers M0-M3 and sends an output signal to one input of the adding circuit A2, this output signal then being led further to the subsequent units I and DA 1Q and towards the SLIC circuit.
• the memory space in the coefficient memory M only needs to be added by a space for controlling the analogue feedback A, since the digital feedback is already available.
• the block A is a voltage converter.
• the block A can be a voltage-current converter in the form of a controllable resistance, however. In such a case the adder A, sums the currents from the SLAC circuit and from the block A.

Landscapes

• Engineering & Computer Science (AREA)
• Signal Processing (AREA)
• Computer Networks & Wireless Communication (AREA)
• Interface Circuits In Exchanges (AREA)
• Networks Using Active Elements (AREA)
• Devices For Supply Of Signal Current (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=20368864

Family Applications (1)

Country Status (7)

Cited By (10)

Citations (3)

Family Cites Families (1)

• 1987
  • 1987-06-15 SE SE8702486A patent/SE457923B/sv not_active Application Discontinuation
• 1988
  • 1988-05-18 EP EP19880906145 patent/EP0321540A1/en not_active Withdrawn
  • 1988-05-18 WO PCT/SE1988/000254 patent/WO1988010539A1/en not_active Application Discontinuation
  • 1988-05-18 AU AU19576/88A patent/AU1957688A/en not_active Abandoned
  • 1988-06-08 PT PT8768688A patent/PT87686A/pt unknown
  • 1988-06-10 ES ES8801804A patent/ES2008537A6/es not_active Expired
  • 1988-06-13 GR GR880100377A patent/GR880100377A/el unknown

Patent Citations (3)

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