WO1988009995A1 - Structure de memoire ''pipeline'' - Google Patents

Structure de memoire ''pipeline'' Download PDF

Info

Publication number
WO1988009995A1
WO1988009995A1 PCT/US1988/001267 US8801267W WO8809995A1 WO 1988009995 A1 WO1988009995 A1 WO 1988009995A1 US 8801267 W US8801267 W US 8801267W WO 8809995 A1 WO8809995 A1 WO 8809995A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
data
units
pipeline
address
Prior art date
Application number
PCT/US1988/001267
Other languages
English (en)
Inventor
Peter Panec
William P. Real
O. James Fiske
Original Assignee
Hughes Aircraft Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Company filed Critical Hughes Aircraft Company
Publication of WO1988009995A1 publication Critical patent/WO1988009995A1/fr
Priority to NO89890416A priority Critical patent/NO890416L/no
Priority to KR1019890700185A priority patent/KR890702208A/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Definitions

  • the present invention relates generally to high speed computers having task streaming or instruction streaming architectures, and particularly to a pipeline memory structure for such computers.
  • a task stream computer architecture is fundamentally that of a pipeline.
  • an optimal pipeline should be designed so that no conflict ever occurs due to two objects or instructions attempting to enter the same pipeline stage at the same time.
  • the present invention provides a pipeline memory structure having a plurality of randomly accessible memory units and a hierarchical arrangement of data input, data output and address memory interface registers.
  • the data input and address memory interface registers are used to distribute data and address information to the memory units from a data input port and an address port of the processor of a computer, while the data output memory interface registers are used for collecting data information from the memory units and directing this data information to ' a data output port of the -3-
  • the data input, data output and address memory interface registers each comprise a plurality of memory interface units which are interconnected together to form separate branched-tree structures having a plurality of levels.
  • each of the memory interface units contained in the data input, data output and address registers have a substantially identical circuit construction.
  • each of the memory interface units will be capable of generating and appending haxrming code information to the data information being written into the memory units, and a provision for performing error detection and correction on the data information being read from the memory units.
  • Figure 1 is a block diagram of a pipeline memory structure according to the present invention.
  • FIG. 1 is block diagram of the memory blocks shown in Figure 1.
  • Figure 3 is a block diagram of the memory interface units shown in Figure 1.
  • FIG 4 is a block diagram of the PASRAM memory chip shown in Figure 2.
  • FIG. 1 a block diagram of a pipeline memory structure 110 according to the present invention is shown.
  • the pipeline memory structure 110 is shown to be connected to a data input port 112, a data output port 114, and an address port 116.
  • These ports 112-116 may be provided by a processor of any high speed computer, such as a computer employing a task stream or instruction stream architecture.
  • the data input port 112 and the data output port 114 may be comprised of one or more separate data buses within the computer architecture.
  • the address port 116 may be comprised of the address bus within the computer architecture.
  • the pipeline memory structure 110 is generally comprised of a plurality of memory blocks 118 and a plurality of memory interface units 120.
  • the memory interface units 120 fan out from the data input port 112, the data output port 114 and the address port 116 to form three distinct hierarchical arrangements of these memory interface units.
  • Each of these hierarchical arrangements of memory interface units may be characterized as tree structures which branch out to form multiple levels of memory interface units which expand in the number of memory interface units as each level gets closer to the row of memory blocks 118.
  • the data input tree structure 122 is used to distribute data information to the appropriate memory blocks 118 from the data input port 112.
  • the address tree structure 124 is used to distribute address information to the appropriate memory blocks 118 from the address port 116.
  • the data output tree structure 126 is used to collect data information being read from the appropriate memory blocks 118 and direct this data information to the data output port 114 of the computer.
  • FIG. 1 shows only two memory sections or units 128 and 130 which each comprise a row of three memory blocks 118.
  • the pipeline memory structure 110 according to the present invention is capable of being expanded with the appropriate tree structures to provide many memory sections or units.
  • the principals of the present invention are independent of the number of levels to the tree structures 122-126 or the number of memory units 128-130 employed in the memory structure. Additionally, the principals of the present invention are also independent of the number of memory blocks 118 contained in each of the memory sections or units .
  • each of the memory interface units 120 used in the tree structures 122-126 could be of identical circuit construction, different circuit constructions for these memory interface units could also be employed in the appropriate application. While the tree structures 122-126 are shown to have the identical hierarchical arrangement of memory interface units 120, it may also be possible in the appropriate application to provide different arrangements of the memory interface units 120 in the tree structures 122-126. Furthermore, while each level of the memory interface units 120 in each of the tree structures 122-126 doubles the number of these memory interface units used in the previous level, it should be appreciated that the number of memory interface units branching out from any qiven memory interface unit may be increased or decreased at any level from the basic arrangement shown in Figure 1. The present invention may also be used with a greater or smaller number of levels.
  • each of the memory interface units 132 and 134 includes chip select control circuitry which controls the accessing of these memory interface units. Accordingly, the data word present at the data input port 112 may be transmitted to one or both of the memory interface units 132-134.
  • Another pair of memory interface units 136 and 138 are connected to the output of the memory interface unit 134. It should be appreciated that additional memory interface units would be connected to the output of the memory interface unit 132 if Figure 1 were to show the entire pipeline memory structure. While the memory interface units 132 and 134 represent one level in the data input tree structure 122, the memory interface units 136 and 138 represent another level in this tree structure.
  • the memory interface unit 136 is used to direct the flow of data to one or more of the memory blocks 118 in the memory, section or unit 128. Similarly, the memory interface unit 138 is used to direct the flow of data to one or more of the memory blocks 118 in the memory section or unit 130. _,
  • each level of the data input tree structure 122 an address for the memory block 118 to which this data is to be written into will be transmitted down through corresponding levels in the address tree structure 124. Accordingly, when a data word reaches the bottom level of the data input tree structure 122, the appropriate memory address will reach the bottom level of memory interface units in the address tree structure 124.
  • Each of the tree structure levels closest to the memory blocks 118 in the data input and address tree structures comprise a different memorv interface unit 120 connected to each one of the memory sections.
  • the memory interface unit 139 in the address tree structure 124 is connected to the memory section 128, while the memory interface unit 140 is connected to the memory section 130.
  • Figure 1 also shows that the memory interface unit level closest to the memory blocks 118 in the data output tree structure 126 comprises a different memory interface unit connected to each one of the memorv sections.
  • a memory interface unit 141 is connected to the memory section 128, while a memory interface unit 142 is connected to the memory section 130.
  • the memory interface units 141 and 142 will collect the data information being read from the memory sections 128 and/or 130, and direct this information to a memory interface unit 144.
  • the memory interface unit 144 is in turn connected to the data output port 114.
  • An additional memory interface unit 146 is also connected to the data output port 114 for collecting data information from other memory sections in the pipeline memory structure.
  • the memory blocks 118 include two identical sets of memory arrays 148 and 248.
  • Each of the memory arrays 148 and 248 include six pipelined access static random access memory (PASRAM) chips 152.
  • PASR2M memory chips 152 are capable of storing eight bit data words. Accordingly, in order to store a sixteen bit data word plus six bits of hamming code, three of these eight bit PASRAM memory chips 152 must be accessed jointly in one of the memory arrays 148, 248.
  • FIG. 2 Also shown in Figure 2 are a number of memory interface units 120. These particular memory interface units 138-140, 238-240 correspond to the level in the tree structures which are closest to the memory blocks.
  • the address bus 164 supplies address information to the memory interface unit 140 while the address bus 264 supplies address information to memory interface unit 240.
  • data in the upper half of the data word is supplied to the ⁇ emory interface vmit 138, while the data in the lower half of the data word is supplied to the memory interface unit 238.
  • data read from the PASRAM memory chips 152 in the memory array 148 is supplied to the memory interface unit 142, while the data read from the PASRAM memory chips 152 in the memory array 248 is supplied to the memory interface unit 242.
  • address buses 164 and " 264 shown in Figure 2 each comprise seventeen address lines in this embodiment.
  • the "111" designation in the bus lines connected to the memory interface units 140 and 240 indicate that seventeen address lines are provided to both of these memory interface units. This designation for the number of lines is also used for the data input and output buses in Figure 2, as well as for the other buses shown in Figures 3 and 4.
  • the memory interface unit 120 generally includes a latch 166 and latch 168.
  • the latch 166 is used to receive and hold the address or data information being transmitted to the memory interface unit.
  • the latch 168 is used to receive and hold various control signals such as aethe data is to be written into or read from memory, and whether the data word is sixteen or thirty-two bits long.
  • the information from the latch 168 plus two additional control signals i.e., mode select signals) is directed to a control decode circuit 170 which is used to enable the appropriate chip function.
  • the control decode circuit 170 may also include the provision for a lock-out condition which will block the memory interface unit 120 from outputting the address or data information even if the chip has otherwise been directed by other control signals.
  • the output from the control decode circuit 170 is directed to an output control circuit 176 which is used to drive the transmission of address or data information from the memory interface unit 120 to the next memory interface unit in the tree structure or to a memory block. Accordingly, it will be appreciated that the provision of an output driver in each of the memory interface units 120 will distribute the drive load necessary to access a large memory configuration.
  • the memory interface unit 120 may also include a maintenance bus interface 172 which is used for testing the memory interface unit during a debugging process.
  • the maintenance bus interface 172 includes a serial input/output line 174 which is used to shift data into or out of the memory interface unit during this process.
  • the memory interface unit 120 also includes a hamming code generation circuit 178 and an error detection/correction circuit 180.
  • the hamming code generation circuit 178 is used to generate and append a number of hamming code bits (e.g., 6) to each of the sixteen bit data words being written into the memory arrays.
  • the error detection/ correction circuit 180 is used to perform error detection and correction on each data word being read from the memory arrays. Preferably, the error detection/correction circuit will be able to detect the presence the two erroneous bits and correct one of these erroneous bits. If more than one bit error is detected, the error detection/correction circuit 180 will generate an interrupt to the computer.
  • the memory interface unit 120 also preferably includes ' an address decode circuit 182.
  • the address decode circuit 182 performs partial decoding of the memory address so that the memory addresses may be distributed to the appropriate memory arrays.
  • the same general circuit construction of a memory interface unit may be used in each of the tree structures 122-126.
  • the mode select signals could be used, for example, to hard wire the particular memory interface units to their appropriate function in these tree structures.
  • the memory interface unit may be fabricated using VHSIC half micrometer technology, though other suitable technologies may be used. It should be noted that one of the advantages of the circuit construction for the memory interface unit 120 is that the number of gate delavs between pipeline registers or memory interface units can be limited to five or six.
  • the PASRAM memory chip 152 generally includes an 8k x 8 bit RAM array 184.
  • the principals of the present invention are not limited to the particular size of the RAM array.
  • the size of RAM array could be enlarged to 32k x 8 bits in the appropriate application.
  • the PASRAM memory chip 152 also includes a set of five latches 186-194.
  • the latch 186 is used to receive and hold address, chip select (CS) , read, and write information which needs to be decoded in an address and control decode circuit 196. After the address and chip select information are decoded, this information will be transmitted to the latch 188 in a pipeline fashion before the RAM arrav 184 is accessed.
  • the latch 190 is used to receive and hold data information to be written into the RAM array 184.
  • the latch 192 is used to match up the data information being written into the RAM array 184 with the- address information contained in the latch 188.
  • the PASRAM memory chip 152 includes the latch 194 for receiving and holding data information being read frcm the RAM array.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)

Abstract

Une structure de mémoire ''pipeline'' comprend plusieurs unités de mémoire sélectivement accessibles (128, 130) et un agencement hiérachique d'entrée de données, de sortie de données et de registres d'interface de mémoire d'adresses. L'entrée de données et les registres d'adresses sont utilisés pour répartir les informations de données et d'adresses dans les unités de mémoire à partir d'un point d'accès d'entrée de données (112) et d'un point d'accès d'adresses (116) du processeur d'un ordinateur, alors que les registres de sortie de données sont utilisés pour recueillir les informations de données à partir des unités de mémoire et pour diriger ces informations de données vers un point d'accès de sortie de données (114) du processeur. L'entrée de données, la sortie de données et les registres d'adresses comprennent chacun plusieurs unités d'interface de mémoire (MIU) (120, 124, 126) qui sont reliées entre elles de façon à former des structures en arbre ramifié comportant plusieurs niveaux.
PCT/US1988/001267 1987-06-02 1988-04-22 Structure de memoire ''pipeline'' WO1988009995A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
NO89890416A NO890416L (no) 1987-06-02 1989-02-01 Samleledningshukommelsestruktur.
KR1019890700185A KR890702208A (ko) 1987-06-02 1989-02-01 파이프라인 메모리 구조물

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US5694087A 1987-06-02 1987-06-02
US056,940 1987-06-02

Publications (1)

Publication Number Publication Date
WO1988009995A1 true WO1988009995A1 (fr) 1988-12-15

Family

ID=22007502

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1988/001267 WO1988009995A1 (fr) 1987-06-02 1988-04-22 Structure de memoire ''pipeline''

Country Status (7)

Country Link
EP (1) EP0315671A1 (fr)
JP (1) JPH02500697A (fr)
KR (1) KR890702208A (fr)
ES (1) ES2007233A6 (fr)
IL (1) IL86196A0 (fr)
TR (1) TR23376A (fr)
WO (1) WO1988009995A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0393436A2 (fr) * 1989-04-21 1990-10-24 Siemens Aktiengesellschaft Mémoire statique avec des registres "pipe-line"
GB2255209A (en) * 1989-04-21 1992-10-28 Secr Defence Apparatus for pipelining a storage system
WO1994029870A1 (fr) * 1993-06-02 1994-12-22 Microunity Systems Engineering, Inc. Systeme d'acces a la memoire en mode rafale
EP0788110A2 (fr) * 1996-02-02 1997-08-06 Fujitsu Limited Dispositif de mémoire à semi-conducteurs fonctionnant en "pipeline"
EP1028427A1 (fr) * 1999-02-11 2000-08-16 Infineon Technologies North America Corp. Extraction anticipée hiérarchique dans dispositifs de mémoires à semiconducteurs
EP1132925A2 (fr) * 2000-02-25 2001-09-12 Infineon Technologies North America Corp. Calibration de chemin de données et mode de test utilisant un bus de données pour mémoires à semi-conducteurs

Citations (4)

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Publication number Priority date Publication date Assignee Title
US3983537A (en) * 1973-01-28 1976-09-28 Hawker Siddeley Dynamics Limited Reliability of random access memory systems
EP0011374A1 (fr) * 1978-11-17 1980-05-28 Motorola, Inc. Unité de commande d'une installation de traitement d'informations avec des lignes de communication communes segmentées
EP0042966A1 (fr) * 1980-06-30 1982-01-06 International Business Machines Corporation Système et procédé de correction et de détection d'erreur pour données numériques emmagasinés
WO1987001858A2 (fr) * 1985-09-23 1987-03-26 Ncr Corporation Systeme de memoire fonctionnant suivant un mode par page

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983537A (en) * 1973-01-28 1976-09-28 Hawker Siddeley Dynamics Limited Reliability of random access memory systems
EP0011374A1 (fr) * 1978-11-17 1980-05-28 Motorola, Inc. Unité de commande d'une installation de traitement d'informations avec des lignes de communication communes segmentées
EP0042966A1 (fr) * 1980-06-30 1982-01-06 International Business Machines Corporation Système et procédé de correction et de détection d'erreur pour données numériques emmagasinés
WO1987001858A2 (fr) * 1985-09-23 1987-03-26 Ncr Corporation Systeme de memoire fonctionnant suivant un mode par page

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Proceedings SCS 85, 1st International Conference on Supercomputing Systems, 16-20 December 1985, St. Petersburg, Florida, IEEE, (US), J.A. Davis et al.: "On optimizing memory hierarchies for supercomputers", pages 561-567 *

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0393436A2 (fr) * 1989-04-21 1990-10-24 Siemens Aktiengesellschaft Mémoire statique avec des registres "pipe-line"
EP0393436A3 (fr) * 1989-04-21 1992-06-24 Siemens Aktiengesellschaft Mémoire statique avec des registres "pipe-line"
GB2255209A (en) * 1989-04-21 1992-10-28 Secr Defence Apparatus for pipelining a storage system
GB2255209B (en) * 1989-04-21 1993-07-28 Secr Defence Apparatus for pipelining a storage system
WO1994029870A1 (fr) * 1993-06-02 1994-12-22 Microunity Systems Engineering, Inc. Systeme d'acces a la memoire en mode rafale
EP0788110A3 (fr) * 1996-02-02 1999-02-03 Fujitsu Limited Dispositif de mémoire à semi-conducteurs fonctionnant en "pipeline"
EP0788110A2 (fr) * 1996-02-02 1997-08-06 Fujitsu Limited Dispositif de mémoire à semi-conducteurs fonctionnant en "pipeline"
US6055615A (en) * 1996-02-02 2000-04-25 Fujitsu Limited Pipeline memory access using DRAM with multiple independent banks
US6163832A (en) * 1996-02-02 2000-12-19 Fujitsu Limited Semiconductor memory device including plural blocks with a pipeline operation for carrying out operations in predetermined order
US6507900B1 (en) 1996-02-02 2003-01-14 Fujitsu Limited Semiconductor memory device including plural blocks with selecting and sensing or reading operations in different blocks carried out in parallel
EP1028427A1 (fr) * 1999-02-11 2000-08-16 Infineon Technologies North America Corp. Extraction anticipée hiérarchique dans dispositifs de mémoires à semiconducteurs
EP1132925A2 (fr) * 2000-02-25 2001-09-12 Infineon Technologies North America Corp. Calibration de chemin de données et mode de test utilisant un bus de données pour mémoires à semi-conducteurs
EP1132925A3 (fr) * 2000-02-25 2003-08-13 Infineon Technologies North America Corp. Calibration de chemin de données et mode de test utilisant un bus de données pour mémoires à semi-conducteurs

Also Published As

Publication number Publication date
ES2007233A6 (es) 1989-06-01
KR890702208A (ko) 1989-12-23
EP0315671A1 (fr) 1989-05-17
TR23376A (tr) 1989-12-28
JPH02500697A (ja) 1990-03-08
IL86196A0 (en) 1988-11-15

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