GB2255209A - Apparatus for pipelining a storage system - Google Patents

Abstract

A circuit arrangement providing multi-ported (11-18) access to a very large data base where there are more memory devices (28) than can be driven by a single output buffer. The multiple ports access data to and from the memory through a common choke point (22) comprising at least a read data bus (24) and an address bus (23). The flow of data and address signals are pipelined and the data and address buses connect with the memory devices through a bus system which is fanned out or branched (42) at a plurality of stages to provide a tree-structured system of buffers. The arrangement can connect to a ROM or for connection to a RAM (28) the choke point comprises in addition a separate data write bus (25) and at least one logic control wire (23) arranged such that the control signal is also pipelined. The routing of data, address and control signals through the buses is thus pipelined, preferably such that the signals controlling the routing are delayed by a similar amount to the data itself. The delay applied to the data, address and control buses and/or the signals which control the routing is achieved by means of shift registers clocked by a high frequency clock.