ES2007233A6 - Una estructura de memoria de encauzamiento para un computador de alta velocidad, unidad de acoplamiento a memoria para la misma y metodo correspondiente para grabar y leer ionformacion de datos. - Google Patents
Una estructura de memoria de encauzamiento para un computador de alta velocidad, unidad de acoplamiento a memoria para la misma y metodo correspondiente para grabar y leer ionformacion de datos.Info
- Publication number
- ES2007233A6 ES2007233A6 ES8801730A ES8801730A ES2007233A6 ES 2007233 A6 ES2007233 A6 ES 2007233A6 ES 8801730 A ES8801730 A ES 8801730A ES 8801730 A ES8801730 A ES 8801730A ES 2007233 A6 ES2007233 A6 ES 2007233A6
- Authority
- ES
- Spain
- Prior art keywords
- data
- address
- registers
- data input
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Advance Control (AREA)
- Image Processing (AREA)
Abstract
SE DESCRIBE UNA ESTRUCTURA DE MEMORIA DE ENCAUZAMIENTO CON UNA PLURALIDAD DE UNIDADES DE MEMORIA ACCESIBLES ALEATORIAMENTE Y UNA DISPOSICION JERARQUICA DE REGISTROS DE ACOPLAMIENTO A MEMORIA DE ENTRADA DE DATOS, SALIDA DE DATOS Y DIRECCIONES. LOS REGISTROS DE ENTRADA DE DATOS Y DIRECCIONES A LAS UNIDADES DE MEMORIA DESDE UNA PUERTA DE ENTRADA DE DATOS Y UNA PUERTA DE DIRECCIONES DEL PROCESADOR DE UN COMPUTADOR, MIENTRAS QUE LOS REGISTROS DE SALIDA DE DATOS SE UTILIZAN PARA RECOGER INFORMACION DE DATOS DE LAS UNIDADES DE MEMORIA Y PARA DIRIGIR ESTA INFORMACION DE DATOS HACIA UNA PUERTA DE SALIDA DE DATOS DEL PROCESADOR. LOS REGISTROS DE ENTRADA DE DATOS, DE SALIDA DE DATOS Y DE DIRECCIONES COMPRENDEN, CADA UNO, UNA PLURALIDAD DE UNIDADES DE ACOPLAMIENTO A MEMORIA QUE ESTAN INTERCONECTADAS PARA FORMAR ESTRUCTURAS ARBORESCENTES INDEPENDIENTES QUE TIENEN UNA PLURALIDAD DE NIVELES.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US5694087A | 1987-06-02 | 1987-06-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2007233A6 true ES2007233A6 (es) | 1989-06-01 |
Family
ID=22007502
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES8801730A Expired ES2007233A6 (es) | 1987-06-02 | 1988-06-01 | Una estructura de memoria de encauzamiento para un computador de alta velocidad, unidad de acoplamiento a memoria para la misma y metodo correspondiente para grabar y leer ionformacion de datos. |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP0315671A1 (es) |
JP (1) | JPH02500697A (es) |
KR (1) | KR890702208A (es) |
ES (1) | ES2007233A6 (es) |
IL (1) | IL86196A0 (es) |
TR (1) | TR23376A (es) |
WO (1) | WO1988009995A1 (es) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0469024A1 (en) * | 1989-04-21 | 1992-02-05 | The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern | Apparatus for pipelining a storage system |
US5093809A (en) * | 1989-04-21 | 1992-03-03 | Siemens Aktiengesellschaft | Static memory having pipeline registers |
US5410670A (en) * | 1993-06-02 | 1995-04-25 | Microunity Systems Engineering, Inc. | Accessing system that reduces access times due to transmission delays and I/O access circuitry in a burst mode random access memory |
JP4084428B2 (ja) * | 1996-02-02 | 2008-04-30 | 富士通株式会社 | 半導体記憶装置 |
DE60035630T2 (de) * | 1999-02-11 | 2008-02-07 | International Business Machines Corporation | Hierarchische Vorausladung in Halbleiterspeicheranordnungen |
US6799290B1 (en) * | 2000-02-25 | 2004-09-28 | Infineon Technologies North America Corp | Data path calibration and testing mode using a data bus for semiconductor memories |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1461245A (en) * | 1973-01-28 | 1977-01-13 | Hawker Siddeley Dynamics Ltd | Reliability of random access memory systems |
US4296469A (en) * | 1978-11-17 | 1981-10-20 | Motorola, Inc. | Execution unit for data processor using segmented bus structure |
US4334309A (en) * | 1980-06-30 | 1982-06-08 | International Business Machines Corporation | Error correcting code system |
US4823324A (en) * | 1985-09-23 | 1989-04-18 | Ncr Corporation | Page mode operation of main system memory in a medium scale computer |
-
1988
- 1988-04-22 JP JP63504765A patent/JPH02500697A/ja active Pending
- 1988-04-22 EP EP88905056A patent/EP0315671A1/en not_active Withdrawn
- 1988-04-22 WO PCT/US1988/001267 patent/WO1988009995A1/en not_active Application Discontinuation
- 1988-04-27 IL IL86196A patent/IL86196A0/xx unknown
- 1988-06-01 TR TR384/88A patent/TR23376A/xx unknown
- 1988-06-01 ES ES8801730A patent/ES2007233A6/es not_active Expired
-
1989
- 1989-02-01 KR KR1019890700185A patent/KR890702208A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
KR890702208A (ko) | 1989-12-23 |
JPH02500697A (ja) | 1990-03-08 |
IL86196A0 (en) | 1988-11-15 |
TR23376A (tr) | 1989-12-28 |
EP0315671A1 (en) | 1989-05-17 |
WO1988009995A1 (en) | 1988-12-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FD1A | Patent lapsed |
Effective date: 19980504 |