WO1988006760A3 - Central processor unit for digital data processing system including write buffer management mechanism - Google Patents

Central processor unit for digital data processing system including write buffer management mechanism Download PDF

Info

Publication number
WO1988006760A3
WO1988006760A3 PCT/US1988/000364 US8800364W WO8806760A3 WO 1988006760 A3 WO1988006760 A3 WO 1988006760A3 US 8800364 W US8800364 W US 8800364W WO 8806760 A3 WO8806760 A3 WO 8806760A3
Authority
WO
WIPO (PCT)
Prior art keywords
write buffer
processor
processing system
system including
data processing
Prior art date
Application number
PCT/US1988/000364
Other languages
French (fr)
Other versions
WO1988006760A2 (en
Inventor
Paul I Rubinfeld
G Michael Uhler
Robert M Supnik
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of WO1988006760A2 publication Critical patent/WO1988006760A2/en
Publication of WO1988006760A3 publication Critical patent/WO1988006760A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Quality & Reliability (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

A processor for use in a digital data processing system including a main memory and a write buffer for buffering write data and associated addresses from the processor for storage in the storage locations identified by the associated addresses in the main memory. In response to selection occurrences, such as a context switch, which can not be detected outside of the processor, the processor asserts a signal which enables the write buffer to transfer all of its contents to the main memory. The write buffer, in turn, disables the processor while it is transferring data to the main memory.
PCT/US1988/000364 1987-02-24 1988-02-08 Central processor unit for digital data processing system including write buffer management mechanism WO1988006760A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/017,518 US4851991A (en) 1987-02-24 1987-02-24 Central processor unit for digital data processing system including write buffer management mechanism
US017,518 1987-02-24

Publications (2)

Publication Number Publication Date
WO1988006760A2 WO1988006760A2 (en) 1988-09-07
WO1988006760A3 true WO1988006760A3 (en) 1988-09-22

Family

ID=21783038

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1988/000364 WO1988006760A2 (en) 1987-02-24 1988-02-08 Central processor unit for digital data processing system including write buffer management mechanism

Country Status (6)

Country Link
US (1) US4851991A (en)
EP (1) EP0303661B1 (en)
JP (1) JPH01502939A (en)
CA (1) CA1300280C (en)
DE (1) DE3884103D1 (en)
WO (1) WO1988006760A2 (en)

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US4965721A (en) * 1987-03-31 1990-10-23 Bull Hn Information Systems Inc. Firmware state apparatus for controlling sequencing of processing including test operation in multiple data lines of communication
US5317717A (en) * 1987-07-01 1994-05-31 Digital Equipment Corp. Apparatus and method for main memory unit protection using access and fault logic signals
US5003459A (en) * 1988-04-01 1991-03-26 Digital Equipment Corporation Cache memory system
US4993030A (en) * 1988-04-22 1991-02-12 Amdahl Corporation File system for a plurality of storage classes
WO1990003724A1 (en) * 1988-10-04 1990-04-19 Solatrol, Inc. Distributed multiple irrigation controller management system
US5109490A (en) * 1989-01-13 1992-04-28 International Business Machines Corporation Data transfer using bus address lines
CA1325288C (en) * 1989-02-03 1993-12-14 Ricky C. Hetherington Method and apparatus for controlling the conversion of virtual to physical memory addresses in a digital computer system
DE3923872A1 (en) * 1989-07-19 1991-01-24 Philips Patentverwaltung CIRCUIT ARRANGEMENT FOR CONTROLLING ACCESS TO A MEMORY
JPH0666056B2 (en) * 1989-10-12 1994-08-24 甲府日本電気株式会社 Information processing system
DE69032498T2 (en) * 1989-10-23 1999-03-04 Mitsubishi Electric Corp Cell switch
EP0440243A3 (en) * 1990-01-31 1993-12-15 Nec Corp Memory controller for sub-memory unit such as disk drives
US5224214A (en) * 1990-04-12 1993-06-29 Digital Equipment Corp. BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
US5732241A (en) * 1990-06-27 1998-03-24 Mos Electronics, Corp. Random access cache memory controller and system
EP0510429A3 (en) * 1991-04-24 1993-12-01 Ibm Millicode register management system
US5398235A (en) * 1991-11-15 1995-03-14 Mitsubishi Denki Kabushiki Kaisha Cell exchanging apparatus
JP2671699B2 (en) * 1991-11-15 1997-10-29 三菱電機株式会社 Cell exchange device
GB2277181B (en) * 1991-12-23 1995-12-13 Intel Corp Interleaved cache for multiple accesses per clock in a microprocessor
JP2755039B2 (en) * 1992-05-12 1998-05-20 日本電気株式会社 Register access control method
JP3451103B2 (en) * 1992-11-27 2003-09-29 富士通株式会社 Data communication device and method
EP0612171B1 (en) * 1993-02-15 2001-11-28 Mitsubishi Denki Kabushiki Kaisha Data queueing apparatus and ATM cell switch based on shifting and searching
US5584009A (en) * 1993-10-18 1996-12-10 Cyrix Corporation System and method of retiring store data from a write buffer
EP1215577B1 (en) * 2000-08-21 2012-02-22 Texas Instruments Incorporated Fault management and recovery based on task-ID
JP2002358232A (en) * 2001-05-31 2002-12-13 Mitsubishi Electric Corp Memory access device
US7232821B2 (en) 2002-04-08 2007-06-19 Glaxo Group Limited (2-((2-alkoxy)-phenyl) -cyclopent-1enyl) aromatic carbo and heterocyclic acid and derivatives
KR100438736B1 (en) * 2002-10-04 2004-07-05 삼성전자주식회사 Memory control apparatus of performing data writing on address line
US8250412B2 (en) * 2003-09-26 2012-08-21 Ati Technologies Ulc Method and apparatus for monitoring and resetting a co-processor
US7702955B2 (en) 2005-12-28 2010-04-20 De Almeida Adrian S Method and apparatus for detecting a fault condition and restoration thereafter using user context information
KR102576159B1 (en) * 2016-10-25 2023-09-08 삼성디스플레이 주식회사 Display apparatus and driving method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4591973A (en) * 1983-06-06 1986-05-27 Sperry Corporation Input/output system and method for digital computers
EP0208430A1 (en) * 1985-06-28 1987-01-14 Hewlett-Packard Company A method and apparatus for performing variable length data read transactions

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3737861A (en) * 1970-04-01 1973-06-05 Honeywell Inc Input/output bus
US4439829A (en) * 1981-01-07 1984-03-27 Wang Laboratories, Inc. Data processing machine with improved cache memory management
US4500958A (en) * 1982-04-21 1985-02-19 Digital Equipment Corporation Memory controller with data rotation arrangement
US4543628A (en) * 1983-01-28 1985-09-24 Digital Equipment Corporation Bus for data processing system with fault cycle operation
US4713755A (en) * 1985-06-28 1987-12-15 Hewlett-Packard Company Cache memory consistency control with explicit software instructions

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4591973A (en) * 1983-06-06 1986-05-27 Sperry Corporation Input/output system and method for digital computers
EP0208430A1 (en) * 1985-06-28 1987-01-14 Hewlett-Packard Company A method and apparatus for performing variable length data read transactions

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, volume 22, no. 7, December 1979, (New York, US), R.A. Smith et al.: "Parallel micro-processor I/O operation", pages 2715-2716 *
IBM Technical Disclosure Bulletin, volume 26, no. 9, February 1984, (New York, US), E.J. Annunziata et al.: "Central processor retry", pages 4840-4841 *

Also Published As

Publication number Publication date
WO1988006760A2 (en) 1988-09-07
JPH01502939A (en) 1989-10-05
DE3884103D1 (en) 1993-10-21
EP0303661A1 (en) 1989-02-22
CA1300280C (en) 1992-05-05
EP0303661B1 (en) 1993-09-15
JPH0559455B2 (en) 1993-08-31
US4851991A (en) 1989-07-25

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