GB2002936A - Data transfer systems - Google Patents

Data transfer systems

Info

Publication number
GB2002936A
GB2002936A GB7827118A GB7827118A GB2002936A GB 2002936 A GB2002936 A GB 2002936A GB 7827118 A GB7827118 A GB 7827118A GB 7827118 A GB7827118 A GB 7827118A GB 2002936 A GB2002936 A GB 2002936A
Authority
GB
United Kingdom
Prior art keywords
data
main memory
disc
bytes
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB7827118A
Other versions
GB2002936B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/821,931 external-priority patent/US4159532A/en
Priority claimed from US05/821,900 external-priority patent/US4204250A/en
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of GB2002936A publication Critical patent/GB2002936A/en
Application granted granted Critical
Publication of GB2002936B publication Critical patent/GB2002936B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

During the transfer of data between a peripheral storage device and a main memory via a peripheral controller, a predictor first-in first-out buffer in data logic 36 in the controller is loaded with a dummy byte each time transfer of a word is requested, requested words being temporarily stored in data first-in first-out buffers in the data logic, a dummy byte being dropped each time a two word byte is unloaded from the data buffer so that the input register of the predictor first-in first-out buffer is emptied. This results in a control signal being sent to indicate that there is room for a new word to be stored. When a command for eg writing on a disc is detected, the central processing unit supplies configuration words defining a disc track location, followed by a main memory address, a range count representing the number of bytes to be transferred and a task word for storage in a scratch pad memory. To effect the operation the configuration words are fetched from memory and stored in a device adaptor 14 for comparison with track information read from the disc. Whilst logic unit 29 searches for a match, bus logic 34 requests data from main memory and 32 bytes are consequently stored in the data buffer with corresponding decrementing of the range count and incrementing of the main memory address. When a match occurs the data is transferred, 16 bytes at a time, to the device adaptor, additional data from main memory being then requested, this process being repeated until the range count is zero. The process of transferring data from disc to main memory is effected by determining the required disc and an offset count then being accessed to determine how many leading bytes are to be ignored before transfer commences (the range count only being decremented when the offset count has been decremented to zero). <IMAGE>
GB7827118A 1977-08-04 1978-06-16 Data transfer control systems Expired GB2002936B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/821,931 US4159532A (en) 1977-08-04 1977-08-04 FIFO look-ahead system
US05/821,900 US4204250A (en) 1977-08-04 1977-08-04 Range count and main memory address accounting system

Publications (2)

Publication Number Publication Date
GB2002936A true GB2002936A (en) 1979-02-28
GB2002936B GB2002936B (en) 1982-04-28

Family

ID=27124602

Family Applications (2)

Application Number Title Priority Date Filing Date
GB8040431A Expired GB2061577B (en) 1977-08-04 1978-06-16 Data transfer control in a peripheral controller
GB7827118A Expired GB2002936B (en) 1977-08-04 1978-06-16 Data transfer control systems

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB8040431A Expired GB2061577B (en) 1977-08-04 1978-06-16 Data transfer control in a peripheral controller

Country Status (3)

Country Link
DE (2) DE2831709A1 (en)
FR (1) FR2406251B1 (en)
GB (2) GB2061577B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1389761A2 (en) * 2002-08-05 2004-02-18 Seiko Epson Corporation Data transfer control system, program and data transfer control method
WO2013136071A2 (en) 2012-03-16 2013-09-19 Oxsensis Limited Optical sensor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3241356A1 (en) * 1982-11-09 1984-05-10 Siemens AG, 1000 Berlin und 8000 München DEVICE FOR MICROPROGRAM CONTROL OF AN INFORMATION TRANSFER AND METHOD FOR THEIR OPERATION

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3351917A (en) * 1965-02-05 1967-11-07 Burroughs Corp Information storage and retrieval system having a dynamic memory device
GB1264096A (en) * 1970-06-27 1972-02-16
GB1447627A (en) * 1972-12-11 1976-08-25 Cable & Wireless Ltd Buffer stores
FR2260141A1 (en) * 1974-02-01 1975-08-29 Honeywell Bull Soc Ind Data transfer control for data processor - is used between periodic and non-periodic units employing buffer memory
US3993981A (en) * 1975-06-30 1976-11-23 Honeywell Information Systems, Inc. Apparatus for processing data transfer requests in a data processing system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1389761A2 (en) * 2002-08-05 2004-02-18 Seiko Epson Corporation Data transfer control system, program and data transfer control method
EP1389761A3 (en) * 2002-08-05 2004-06-09 Seiko Epson Corporation Data transfer control system, program and data transfer control method
US7165124B2 (en) 2002-08-05 2007-01-16 Seiko Epson Corporation Data transfer control system, electronic instrument, program, and data transfer control method
WO2013136071A2 (en) 2012-03-16 2013-09-19 Oxsensis Limited Optical sensor
US9766099B2 (en) 2012-03-16 2017-09-19 Oxsensis Limited Optical sensor with one or more sensing interference elements
US10545035B2 (en) 2012-03-16 2020-01-28 Oxsensis Limited Optical sensor with one or more sensing interference elements

Also Published As

Publication number Publication date
DE2858284A1 (en) 1985-07-04
DE2831709A1 (en) 1979-02-22
GB2061577B (en) 1982-10-20
FR2406251B1 (en) 1986-01-10
DE2858284C2 (en) 1987-05-21
GB2061577A (en) 1981-05-13
DE2831709C2 (en) 1990-10-04
FR2406251A1 (en) 1979-05-11
GB2002936B (en) 1982-04-28

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19930616