GB2061577A - Improvements in data transfer control in a peripheral controller - Google Patents

Abstract

In a peripheral controller of a data processing system having a plurality of system units electrically coupled to a common communication bus 13 for asynchronous intercommunication, for dynamically tracking data byte transfers an array of counters 77 responsive to both hardware and firmware control are connected in a manner to form a serial control data path. Prior to a data transfer, a serial data stream including an offset range count, a range count and a main memory address is shifted through the counters 77 under firmware control. During a data transfer, the firmware enables the hardware control to increment the memory address and decrement the range count to accommodate the higher data transfer rates characteristic of hardware control. <IMAGE>

Description

1 GB 2 061 577 A 1

SPECIFICATION Improvements in or relating to data transfer control systems in a peripheral controller

The invention relates to the data transfer control systems, and more particularly to a system for maintaining a data transfer rate through a peripheral controller to a peripheral storage device without 5 the loss of data.

Data processing systems having a plurality of system units electrically coupled to a common communication bus for the asynchronous transfer of information therebetween are disclosed in U.S.

Patent 3,993,981 and in U.S. Patent 4,003,033, each assigned to the assignee of the present invention.

In the transfer of data from a main memory unit of such a data processing system to a peripheral storage device, two problems may occur which cause a degeneration of the data transfer rate. If the peripheral controller does not request an additional data word from main memory immediately upon receiving a data word in response to a previous request, the communication bus may be captured by another system unit. Further, if the peripheral controller requests data at a rate exceeding the transfer rate to the peripheral storage device, data may be lost.

In prior systems, the data transfer rate has been decreased belwo a safety threshold to avoid the above-mentioned problems, or data requests have been issued immediately upon receipt of a data word in response to a previous request without regard to the availability of storage locations. In operating environments where the data transfer rates approach the marginal areas of safety, neither of these 20 approaches have proven satisfactory.

Prior systems having the common bus architecture have relied solely on firmware control to accommodate data transfers between mass storage devices such as a disc and the common bus. With the incorporation of mass storage devices supplying data words at a rate of the order of ten times that of the prior transfer rates, a new control architecture was required. Particularly, the time penalties 25 suffered in amending range counts and memory address data directly from a scratchpad memory could no longer be tolerated. Thus, the system data rates requ'ire'd a departure from the previous all firmware control architecture.

Accordingly there is now provided a peripheral device controller having architecture accommodating both the temporary storage of main memory address, range and offset range parameters used during data transfers between the main memory and a peripheral unit via an 30 asynchronous bus and the dynamic amending of said parameters during a data transfer, comprising a scratchpad memory unit, a hardware control means, a plurality of counters including a first counter arranged to recieve an offset range count, a range count and memory address parameters from the scratchpad memory and to retain the memory address information therein, a second counter electrically connected to said first counter to form a serial data path from said first counter and responsive to said 35 hardware control means for accommodating a serial transfer, therethrough, of said offset range and range parameters from the first counter, said second counter retaining said range parameter having means indicating to said hardware control means the completion of a data transfer between said main memory and said peripheral unit, and a third counter electrically connected to said second counter in extension of said serial data path and responsive to the hardware control means for accommodating a 40 serial shift of said offset range parameter from the second counter, said third counter having means for dynamically indicating the occurrence of a first data byte in an information stream to be transferred between said main memory and said peripheral unit, said counters dynamically uOdating said parameters under the control of said hardware means during data transfers, and firmware control means responsive to the hardware control means between data transfers for circulating a serial stream 45 of said parameters through the scratchpad memory unit and respectively through the said counters in sequence, thereby storing control information in the scratchpad memory unit for re-initiating a data transfer in the event of a data transfer error.

In a preferred embodiment of a data processing system according to the present invention, a logic data transfer control system is provided for controlling the transfer of data words from a main memory 50 to a peripheral controller.

More particularly, the logic control system includes an array of data FIF0s and a predictor FIFO operating in parallel. When a data request is made to main memory, the predictor FIFO is loaded with a dummy orflag byte. When the data byte is received from main memory and loaded into the data FIF0s, and the input register of the predictor register is not filled, a next data request to main memory is issued.

If the input register of the predictor FIFO is filled, however, no additional data request is made until the data in the input register fails into the FIFO stack.

When the data FIF0s are filled, the predictor FIFO also is filled, and no further data request to main memory may be made until a data byte is transferred to a peripheral storage device. In that event, the flag byte in the input register of the predictor FIFO fails into the FIFO stack. The input register thereupon 60 signals the occurrence of a favourable prediction for storage capacity, and an additional data word is requested from main memory. When the data is received from main memory and loaded into the input registers of the data FIF0s, the input register of the predictor FI FO again is sensed as before described. If the data byte transfer to the peripheral storage device has emptied the input register of the predictor GB 2 061 577 A 2 FIFO, an additional data request is issued to main memory. Otherwise, no further data requests are made until a transfer to the peripheral storage device is made.

In one aspect, data words received from main memory are stored in a left byte FIFO and a right byte FIFO. In transferring the data to a disk storage device, the left and right bytes are alternately selected for transfer to the disk storage device. When the right FIFO is unloaded, the predictor FIFO is unloaded to synchronize the operation of the predictor FIFO with that of the data FIF0s. For dynamically tracking data byte transfers, address counters, range counters and offset range counters are connected in a manner to a serial data path, thereby accommodating a data load with minimal firmware interaction. A memory address, a range count and an offset range count are loaded from scratchpad memory under firmware control prior to a data transfer. The firmware control thereafter enables the hardware control to increment the address counters and decrement the range counters during the data transfer to accommodate a data transfer rate higher than that possible under firmware control. Hereinafter the invention is described by way of example and with reference to the accompanying drawings, wherein: 15 Figure 1 is a functional block diagram of a data processing system having system units electrically coupled to a common communication bus; Figure 2 is a functional block diagram of the disk controller of Figure 1; Figure 3 is a graphical illustration of communication words transferred through the common bus of Figure 1; 20 Figures 4 and 5 are a detailed functional block diagram of the disk controller of Figure 1; Figure 6 is a functional block diagram of a firmware control system used in controlling the operation of the system of Figures 4 and 5; Figure 7 is a detailed functional block diagram of the range and offset range control unit of figures ^ 4 and 5, Figure 8 is a detailed. logic diagram of the data FIFO unit of Figure 4, which is an embodiment of 25.

the invention; Figure 9 is a timing diagram of the operation of the system of Figure 8; Figure 10 is a timing diagram of the operation of the system of Figures 4- 8 during a data transfer from a disk device to the common communication bus; and Figure 11 is a timing diagram of the operation of the system of Figures 4- 8 during a data transfer 30 from the main memory unit to the disk adapter of Figure 1.

Certain aspects of the apparatus described herein but not cliamed are described in our copending application 27118/78.

FIGURE 1 Figure 1 illustrates in functional block diagram form a computer system having a medi urn- 35 performance disk controller (MPDC) 10 in electrical communication with a central processor unit 11 and a main memory unit 12 by way of a common communication bus hereinafter referred to as megabus 13. The MPDC 10 is a microprogrammed peripheral control subsystem for storing and retrieving data from mass storage media. The controller includes a Read Only Store (ROS) memory to be later described having stored therein microprogram instructions. The ROS communicates with mass storage adapters such as the device adapter 14, which has the facility to support plural daisy-chained disk devices 15.

The megabus 13 provides an information path between any two units in the system. The paths are asynchronous in design, thereby enabling units of various speeds to operate efficiently. The bus accommodates information transfers including communication requests, control commands, status 45 signals and data transfers between main memory 12 and disk devices 15.

Any system unit requiring communication with any other system unit issues a bus cycle request.

When the bus cycle is granted, the requesting unit becomes the master and the addressed system unit becomes the slave. Some bus interchanges required a response cycle as well as a request cycle. By way of example, the master unit may identify itself to a slave unit and indicate that a response is required. 50 When the required information becomes available, the slave assumes the role of master and initiates a transfer to the requesting unit.

processor has the lowest priority, the MPDC 10 has the next to the lowest priority, and the memory 12 Was the highest priority.

A more detailed background description of the system of Figure 1 is given in U.S. Patent No. 55

3,993,981 which ilg assigned to the assignee of the present invention, and which is incorporated by reference herein.

FIGURES 2 AND 3 Figure 2 illustrates in functional block diagram form the MPDC 10 of Figure 1, and Figure 3 graphically illustrates the binary instruction formats necessary for the operation of the MPDC. 60 The megabus 13 is connected to an address logic unit 20 by way of an address cable 2 1. Logic unit 20 is comprised of address transceivers through which memory addresses, channel destination numbers and function codes are transferred between the MPDC 10 and the megabus 13. The logic unit 3 GB 2 061 577 A 3 further is comprised of control logic for distributing information on the address cable 21 throughout the MPDC.

Logic unit 20 is connected to a range and offset range logic unit 22 by way of a unidirectional control cable 23, and connected to an arithmetic logic unit 24 by way of a bidirectional control cable 25. The logic unit 22 includes a 16-bit range counter which is loaded with the number of bytes to be transferred during a read or write operation. The logic unit further includes a 1 6-bit offset range counter which is loaded with a count indicating the number of leading data bytes to be ignored during a read data transfer.

The arithmetic logic unit (ALU) 24 is the focal point of all data operations within the MPDC. Such data operations may occur between MPDC 10 and the megabus 13, or between the MPDC and the 10 device adapter 14. The ALU performs both logic and arithmetic operations on incoming data, and is comprised of an A-operand multiplexer XAMUX), a B-operand multiplexer (BMUX), an eight-bit arithmetic unit (AU), and an eight-bit accumulator (ACU) to be further described. Under firmware control, the AMUX selects one of eight data fields and the BMUX selects one of four data fields. The AU performs 8-bit arithmetical and logical operations on the data selected by the multiplexers, and supplies 15 the result to the accumulator for temporary storage.

The ALU receices range and offset range control signals from the logic unit 22 by way of a control cable 26, and firmware control signals from a microprogram control store logic unit 27 by way of a control cable 28. The ALU 24 further communicates with an adapter logic unit 29 by way of a bidirectional control cable 30, and with a scratchpad memory unit 31 by way of a bidirectional control. 20 cable 32. In addition, the ALU 24 communicates with the device adapter 14 by way of a bidirectional control cable 33, and supplies control information to a bus logic unit 34 by way of a unidirectional control cable 35. The ALU also receives and transfers data to a data logic unit 36 by way of a bidirectional data cable 37.

The adapter logic unit 29 is connected to the device adapter 14 by way of a bidirectional 25 communication cable 38. The logic unit 29 provides the MPDC with a communication path to control the transfer of data and status information between the adapter 14 and the MPDC 10.

The scratchpad memory unit 31 includes logic comprised of-an index register, an address register, an address selector, a scratchpad memory, and the logic elements controlling the operation of the scratchpad memory. The scratchpad memory is a 1.024 K-bit by 8-bit read/write memory which is 30 segmented into indexed and non-indexed sections, each section containing two quadrants. The non indexed section of the memory is comprised of 256 work locations and 256 reserve locations. The indexed section of the memory is comprised of 256 locations for the storage of device-related information and 256 reserve location. The 256 locations for device- related information are further sub- divided into four sections, each comprising 64 locations per channel. 35 The address register of the scratchpad memory unit 31 is a 1 0-bit register, wherein the high order bit selects either the indexed or non-indexed mode. The second high order bit selects a 256-location quadrant, and the next two bits select 64 locations within the quadrant. The six low order bits select a scratchpad address. Data is written into the selected address of the scratchpad memory unit from the AMUX of the ALU 24 during the execution of a firmware memory write command. The data out of the 40 scratchpad memory is delivered to the AMUX and the BMUX for distribution throughout the MPDC.

The microprograrn control store logic unit 27 is typical of that known in the art, and includes a return register unit, a selector, a microprograrn address counter, a Read Only Store (ROS) memory, a microprogram instruction register (MPIR), a decoder and a firmware distribution unit to be further -45 described. The ROS provides permanent storage for resident control firmware and diagnostic 45 microprograms, and may be addressed to select various 1 6-bit wide output derived from the outputs of sixteen 1,024 by 4-bit programmable Read Only Memory (PROM) chips. The ROS output is applied to the MPIR which is a 1 6-bit wide register used to store the output of the ROS for one clock cycle during a microinstruction execution.

The bus logic unit 34 receives control signals from the ALU 24 by way of cable 35, and from the 50 microprograrn control store logic unit 27 by way of cable 28 and a control cable 39. The logic unit 34 is connected to the megabus 13 by way of a bidirectional control 40. The bus logic unit 34 performs asynchronous handshaking operations by responding to and generating megabus cycle requests.

Further, simultaneous requests and grants of megabus, cycles are accommodated on a priority basis.

with the MPDC at an intermediary priority position and the main memory at a position of increased 55 priority.

The data logic unit 36 includes error checkers, five 16 word by 4byte first-in-first-out (FIFO) data buffers and a read selector for accommodating the transfer of data or a bidirectional data cable 41 between the MPDC 10 and the megabus 13. Any information entering the MPDC 10 from the medabus 13 is gated through data transceivers and checked for parity. The same logic is used to deliver the MPDC channel number to the megabus 13 in response to a bus cycle request from a system unit. Four of the five FIF0s receive data, and the fifth FIFO is used to prevent the MPDC from making a cycle request when the data FIF0s are full. The FIFO chips are capable of stacking 14 words, plus retaining one word in the output registers to provide a total capacity of 16 words.

Clock signals for controlling the operation of the MPDC 10 are provided by a system clock unit 4265 4 GB 2 061 577 A compfised cif an-8-MHHz crystal oscillaton-The system clock signal is applied to a clock logic unit 43 which provides a 4 MHz square wave that is distributed throughout the MPDC. The clock logic unit 43 also receives control signals from the microprogram control store logic unit 27 by way of a control line 44 to enable or reset the logic unit.

The operations performed by the MPDC 10 include a direct memory access (DMA) read, a DMA write, an 1/0 output command, an 1/0 input command and an interrupt operation. Each of the operations required a single bus cycle except for the DMA read and the 1/0 input commands which require two bus cycles.

Referring to Figures 3a and 3b, the specific parameter formates for machine instructions used in megabus communications with the MPDC are illustrated. When a data transfer is to occur, the CPU 11 10 Figure 1 issues a machine instruction referred to as an 1/0 Output Command which includes a destination channel number, a 6-bit function code, and a data word as illustrated by the 1/0 output command format of Figure 3a. The destination channel number identifies the system device to which a request is directed, and the function code provides the address in scratchpad memory unit 31 to which a data transfer is directed. The function code further identifies a CPU command as an input or an output command. The data word may include a task to be executed, range and offset range counts, a main memory address, or configuration words used to control the disk device during a data transfer. As shown in Figure 3a, the destination channel numbers and function codes are transferred between the megabus 13 and the MPDC 10 by way of the address logic unit 20. The source channel number, main memory addresses, range and offset range and information stored in reserve areas are transferred between the megabus and the MPDC by way of the data logic unit 36. If data is to be written into main memory 12 of Figure 1, the CPU 11 issues a DMA memory write operation. In response thereto, the starting memory address 60a is applied to the megabus 13 via the address cable 2 1, and the data 60b to be written into memory is applied to the megabus via the cable 41. As illustrated in Figure 3a, the memory address register is a 24-bit register, while the data register is a 1 6-bit register.

If data is to be read from main memory 12, the CPU 11 issues a machine instruction referred to as a DMA memory read request. The instruction includes a 24-bit memory address 61 a, a 1 0-bit source channel number 61 b, and a 6bit reserve area 61 c. The memory address 61 a is received from the megabus 13 via cable 21 leading to the address logic unit 20. The channel number 61 b and reserve area 61 c are received by the data logic unit 36 by way of data cable 41. In response to the DMA read 30 request instruction, the MPDC issues a DMA memory read response instruction comprising a 1 0-bit destination channel number 62a, a 6-bit reserve area 62b, and 16 bits of data 62c to be transferred.

The destination channel number and reserve area are transferred to the megabus by way of the address cable 21, while the 16 bits of data are transferred to the megabus by way of data cable 41. It is to be understood that the contents of the reserve area 62b is identical to that of the reserve area 61 c. Thus, 35 information stored by the CPU into the reserve area 61 c is returned to the megabus by way of the reserve area 62b.

The CPU 11 may transfer data from main memory and indicate a task which the MPDC 10 is to perform upon the data. For example, the CPU may issue an 1/0 output command instruction comprising a 1 0-bit destination channel number 63a to identify the MPDC, a 6-bit function code 63b to identify a 40 scratchpad memory address, and 16 bits of data 63c to be stored in the indicated scratchpad location.

As before described, the destination channel number and fu nction code are received by the address logic unit 20 by way of address cable 2 1, and the data is stored in the data logic unit 36. The data is transferred under firmware control from the logic unit 36 to the ALU 24, and thereafter stored in the scratchpad memory unit 3 1. The CPU 11 issues additional 1/0 output commands to store into the scratchpad a range, an offset range, a main memory address, a task to be executed and configuration words for controlling the operation of the disk device during a data transfer. The firmware further may determine from the low order bit of the function code whether the task includes an input or an output operation. The task may include any of the before-described MPDC operations.

If the CPU 11 requires information from the MPDC 10, an Vd input command instructioin may be 50 issued. The instruction is comprised of a 1 0-bit destination channel number 64a, a 6-bit function code 64b, a 1 0-bit source channel number 64c identifying the source of the request, and a 6-bit reserve area 64d. In response to the CPU request, the MPDC issues an 1/0 input response instruction comprising a 1 0-bit destination channel number 65a, a 6-bit reserve area 65b having stored therein the data appearing in reserve area 64d, and 16 bits of data 65c.

When data is to be written into the scratchpad memory unit 3 1, a two cycle operation occurs.

a 25.

The CPU 11 issues an 1/0 load output command which is comprised of two instructions. The first instruction includes an 8-bit module number 66a indicating the high order eight bits of a main memory address, a 1 0-bit destination channel number 66b, a 6-bit function code 66c, and 16 address bits 66d indicating the low order bits of a 24-bit main memory address. The module number, destination channel 60 number and function code are transferred through address logic unit 20 and ALU 24 to the scratchpad memory unit 31 under firmware control. The firmware thereafter accesses the function code in the scratchpad memory to identify the scratchpad memory address into which the main memory address data is to be written. Upon loading the address in the scratchpad memory, ther firmware commands the bus logic unit 34 to issue a ready signal to the megabus 13. aThe CPU in response thereto issues a 65 GB 2 061 577 A 5 second instruction including a 1 0-bit destination channel number 67a designating the MPDC, a 6-bit function code 67b, a high order bit 67c indicating whether the range count is positive or negative, and 15 range bits 67d indicating the number of data bytes to be transferred. The firmware thereupon accesses the function code to determine the scratchpad memory location into which the range and S bit are to be stored.

In an interrupt operation, the MPDC issues an interrupt instruction comprising a 1 0-bit destination channel number 68a, a 6-bit logic zero area 68b, a 1 0-bit source channel number 68c, and a 6-bit source priority level number 68d. When the MPDC completes an operation, the interrupt instruction is issued to the CPU 11. If the priority level number of the MPDC is higher than the priority level of the task that is currently being performed by the CPU, the MPDC interrupt will be serviced immediately. 10 Otherwise, the MPDC enters a wait state until a CPU command is received.

The formats of two configuration words used to control the operation of a disk device during a data transfer are illustrated in Figure 3b. The configuration words A and B include an image of an ID field of a disk sector on which a particular operation will be initiated. More particularly, the configuration word B includes a 7-bit area reserved for user (RFU) 69a, a 1 -bit track number 69b and an 8-bit sector 151 number 69c. The sector number field is incremented by one after each data field is successfully transferred during a read or write operation.

Configuration word A includes a 4-bit RFU field 70a, a 1 -bit platter select field 70b, a 2-bit RFU field 70c, and a 9-bit cylinder number field 70d. The cylinder number and platter select fields are used as the seek arguments for disk seek operations.

The operation of the invention may best be described in the context of a read or write operation. If the firmware on evaluating a task word in memory unit 31 detects a command for writing a record onto a disk, the firmware accesses the configuration words A and B in memory unit 31 by way of the ALU 24. The firmware thereafter stores the words in the device adapter 14, which compares the words with track information read from the disk. During the period that the logic unit 29 is searching for an ID match, the firmware commands the bus logic unit 34 to request data from the main memory unit 12. In response thereto, the main memory transfers 32 bytes of data to the FIF0s of the data logic unit 36. As the data is being loaded into the data logic unit, the count in logic unit 22 is decremented and the address logic unit is incremented. 30 When an ID match occurs, the adapter 14 initiates a write gap operation on the indicated record - 30 of the disk system. Sixteen of the 32 bytes of data in the data logic unit 36 thereupon are moved from the data logic unit 36 to the device adapter 14 by way of ALU 24. As the data is being transferred to the adapter 14, the firmware commands the bus logic unit 34 to request additional data from the memory unit 12. The above- described process continues until the range field of the logic unit 22 is exhausted. If data is to be read from a disk device and written into main memory 12, the CPU 11 first issues 35 machine instructions for storing configuration words A and B, range, offset range, a beginning main memory address and a task to be performed into the scratchpad memory. In response to firmware initiated control signals from the adapter logic unit 29, the device adapter 14 searches a disk device to find the data record to be transferred. When the disk track has been identified as before described, the 40 data is transferred under hardware control to the data logic unit 36 by way of cable 33 and ALU 24. The 40 hardware accesses the offset range count of the logic unit 22 to detect the number of leading data bytes to be ignored. The logic unit 36 thereafter forms 2- byte words from the succeeding data, and transfers a word under hardware control to the megabus 13 each time two bytes are received. The data transfer continues from the disk adapter 14 to the data logic unit 36 until the range register of the address logic unit 20 indicates that the data transfer is complete.

FIGURES 4 AND 5 Figures 4 and 5 illustrate in a more detailed functional block diagram form the system of Figure 2.

A 24-bit address shift register 70 is connected to the megabus 13 by way of a 24-bit data cable 7 1. The output of the shift register is applied to the A2 input of an 8 to 1 multiplexer 72 (AMUX). Bits 15 and 16 of the shift register output are applied by way of a data cable 73 to the two-bit A1 input of an 50 index register 74. The clock (CK) input to shift register 70 is connected to a control line 70a leading to a firmware output terminal to be further described.

The A1 input to AMUX 72 is connected to the 8-bit output of an cumulator 75, and the A3 input to AMUX 72 is connected by way of a data cable 76 to the output of a range and offset range control unit to be later described. The A4 input to AMUX 72 is connected by way of a data cable 78 to an output of an 8-bit scratchpad address counter 79. The A5 input to AMUX 72 is connected to a data cable 80 leading from the D 1 two-bit output ofindex register 74, and the A6 input to AMUX 72 is connected to the 8-bit output of a 1 K by 8-bit scratchpad memory 81. The A7 input to AMUX 72 is connected to the output of a 1 6-bit data register 82. The select (SEL) input to the AMUX 72 is connected by way of a control line 72a to a firmware output terminal. The 8-bit output of AMUX 72 is 60 connected to the A1 input of an OR logic unit 83.

A 4-to-1 multiplexer 84 (BMUX) has an 8-bit output connected to the A2 input of an arithmetic unit 85. The A1 input to BMUX 84 is supplied by firmware on a control cable 86. The A2 input to BMUX 84 is connected to the output of scratchpad memory unit 81 by way of a data cable 87. The A3 input to 6 1.

GB 2 061 577 A 6.

BMUX 84 is supplied by way of a control cable 88, and the A4 input to the multiplexer is connected to the output of accumulator 75 by way of a data cable 89. The select (SEL) input to the multiplexer is supplied by firmware on a control line 84a.

The A1 input to arithmetic unit 85 is connected by way of a data cable 90 to the 8-bit D1 output of logic unit 83, and the mode input to the arithmetic unit is connected to the butput of an arithmetic 5 control unit 91. The 8-bit output of the arithmetic unit is applied to the input of accumulator 75, and applied by way of data cables 92 and 93 to the data iriput of counter 79. Further, the output of the arithmetic unit is applied by way of data cables 92 and 94 to the A2 input of device adapter 14, and by way of data cable 95 to a data cable 96. The arithmetic unit output also is applied by way of data cables 95 and 97 to the input of a second half-read (SHRD) register 98, and by way of data cables 95 and 99 10 to the 8-bit data inputs of a 1 6-bit bus data register 100. The arithmetic unit output in addition is applied to data cables 95 and 101 leading to the data input of a test logic unit 102.

The output of accumulator 75 further is applied to a data cable 103, and to the two bit A2 input of index register 74. The load (LD) input to the accumulator is connected by way of a control line 75a to a firmware output terminal.

The A1 input of arithmetic control unit 91 is connected by way of a control line 106 to an output terminal of the firmware control system, and the A2 input to the control unit 91 is connected by way of a control line 107 to the D1 output of a hardware control unit 108.

The A1 input to control unit 108 is connected to a control line 109 leading to an output of the firmware control system, and the A2 input to the control unit 108 is connected to a control line 1 08a 20 The A3 interrupt input of control unit 108 is supplied by the device adapter 14 to a control line 110. The A4 input to the control unit is connected to a control line 108b leading from system hardware control.

The D2 output of control unit 108 is connected by way of a control line 111 to the A1 input of adapter logic unit 29, and the D3 output of the control unit 108 is connected to a control line 112 leading to the A1 input of a data control unit 113. The D4 output of control unit 108 is connected by way of a control 25 line 70b to the load (LD) input of shift register 70, and the D5 output is connected to the A1 input of test logic unit 102. The D6 output of the control unit is connected to a control line 108c leading to the system hardware control.

Firmware generated clock signals on a control line 79b are supplied to the clock (CK) input of address counter 79, and firmware control signals on a controi line 114 are supplied to the LD input of 30 the counter. Further, the up/down select input to the counter receives firmware control signals by way of a control line 79b. Two output bits of the counter are applied to the A1 input of a selector 115. The low order six bits of the counter output are applied to the A2 input of the scratchpad memory unit 81.

The A2 input of selector 115 is connected to the D2 output of index register 74, the LD input of which is supplied by firmware to a control line 74a. The 3 bit output of the selector 115 is applied to the 35 address (ADDR) input of scratchpad memory unit 81, and the SEL input of the selector receives firmware control signals by way of a control line 116.

The A1 input to memory unit 81 is connected by way of a data cable 117 to the 8 bit D2 output of logic unit 83. The A2 input to logic unit 83 is connected to the D 'I output of data FIFO unit 118, and the A3 input to logic unit 83 is connected to the D2 output of unit 118. The A4 input to logic unit 83 is 40 supplied by the device adapter 114 by way of a data cable 119.

The data input to the data register 82 is connected to a 16 bit data cable 120 electrically connected to the megabus 13, and the output of the data register further is connected to the input of the data FIFO unit 118. The LD input to the register is supplied by hardware control on a control line 82a. The output of the register further is applied to data cables 139 and 140.

The LD input to data register 100 is supplied by data control unit 113 on a control line 12 1. The output of register 100 is applied to the A2 input of a 2-to-1 data multiplexer 122. The 16 bit A1 input to the multiplexer is supplied by the SHRD register 98, the LD input of which is supplied by data control unit 113 on a control line 98a. The output of the multiplexer is applied by way of a 16 bit data cable 123 to the megabus 13.

Referring to test logic unit 102, a status signal is applied to the A2 input of the logic unit by the firmware control system a status signal by way of a control line 102a to the A3 input of the logic unit 102, and the control unit 77 supplies an end of range signal to the A4 input of the logic unit by way of a control line 102b. The A5 input of logic unit 102 is connected to a control line 125 carrying interrupt signals from the D1 output of device adapter 14. The test logic unit supplies a control signal to a control 55 line 126 leading to a firmware control system to be further described.

The adapter logic unit 29 also receives a firmware signal on a control line 127 connected to its A2 input. The output of the logic unit is applied to the A1 input of device adapter 14. A control line 29a leading from the output of the logic unit is connected to the A5 input of data control unit 113, and to a control line 11 8b leading to the transfer on parallel (TOP) input of Data FIFO unit 118.

As illustrated by Figure 5, the megabus 13 is connected to bus logic unit 128 by way of a bidirectional data cable 129. The A2 input to logic unit 128 is connected to data cable 103 carrying the output of accumulator 75, and the A3 input to the logic unit is connected to a control line 130 leading to an output of the firmware control system. The A4 input to logic unit 128 is connected to the D1 output of control unit 77, and the A5 input to the logic unit is connected to the D 1 output of a first-in60- 7 GB 2 061 577 A first-out (F] FO) unit 131. The A6 input to the logic unit is supplied by system hardware on a control line 128a. The D 'I output of logic unit 128 is connected to data cable 88, and the D2 output is connected to a control line 132 leading to the select (SEL) input of data multiplexer 122. The D3 output of the logic unit is connected to the A2 input of data control unit 113, and the D4 output is connected to the A1 input of FIFO unit 13 1. The D5 output of logic unit 128 is connected to the SEL input of a dual 2-to-1 5 address multiplexer 133, and the D6 output of the logic unit is connected to control line 102a.

The A2 input to FIFO unit 131 is connected to the D1 output of control unit 113, and the D2 output of the FIFO unit is connected to the A3 input of control unit 113. The A4 input to control unit 113 is connected to an output of the firmware control system by way of a control line 134, and the A5 input of the control unit is connected to line 29a. The D2 output of the control unit is connected to control line 12 1, and the D3 output is applied by way of a control line 135 to a control (CTR) input of data FIFO unit 118. The D4 output of data control unit 113 is aplied to the A1 input of control unit 77, and the D5 output is applied to control line 98a leading to the LD input of register 98.

The A2 input to control unit 77 is connected to the D 1 output of a bus address register unit 136, and the A3 input to the control unit is connected by way of a control fine 137 to an output of the 15 firmware control system. The D2 output of the control unit 77 is applied to data cable 76 leading to an input of AMUX 72. The D3 output of control unit 77 is applied to a control line 77a leading to the A3 input of device adapter 14, and to control line 102b leading to the A4 input of test logic unit 102 as before described.

The bus address register unit 136 is comprised of a 24-bit up counter which may be controlled to 20 count either bytes or words, where a word is comprised of two bytes. The 8-bit D1 output of unit 136 also is applied to the B 1 input of address multiplexer 133, and the 8- bit D2 output of the unit 136 is applied to the B2 input of multiplexer 133. The 8-bit D3 output of unit 136 is applied by way of a data cable 138 to the megabus 13. The LD input to the register unit 136 is supplied by firmware on a control line 136a. The 8-bit A1 and A2 inputs to address multiplexer 133 are supplied by data register 82 by 25 way of data cables 139 and 140.

In operation, the MPDC 10 interfaces with the disk adapter 14 which in turn may service plural disk devices as illustrated in Figure 1.

If an unsolicited bus request is received from the megabus 13, the bus logic unit 128 issues a signal on line 102a leading to the test logic unit 102. Further, a device adapter 14 request is indicated 30 by an interrupt signal on control line 127. The logic unit thereby is n O- tified whether a device adapter request or a megabus 13 request is to be serviced. The test logic unit 102 thereupon indicates to the firmware by way of a signal on control line 125 the micro-instruction sequence to be executed. In the event that a request is directed to a disk device which is already involved in executing a task, the bus logic unit 128 wIll issue a not accepted (NAK) status signal to the megabus 13 under system hardware 35 control. If a disk device not presently involved in executing a task is addressed by the megabus 13, but the MPDC is presently involved in executing a previous task involving a second disk device, then the logic unit 128 may issue a wait status signal to the megabus 13. If the disk devicea which is addressed is not busy, and the MPDC is not involved in servicing the device while executing a previous task, then an accepted (ACK) status signal is issued to the megabus 13.

It is to be understood that in the operation of the MPDC, the data paths for a data transfer are prepared by firmware operating in combination with the system of Figures 4 and 5. The data transfer, however, occurs under system hardware/firmware control. Detailed descriptions of such hardware may be found in U.S. Patent No. 3,993,981, and in the following Honeywell reference manuals: MPDC Reference Manual, Doc. No. 71010241 -100, Order No. FM55, Rev. 0; MPDC Cartridge Disc Adapter 45 Reference Manual, Doc. No. 71010239-100, Order No. FM57, Rev. 0; and MPDC Disc Adapter Reference Manual, Doc. No. 71010441 -100, Order No. FK90, Rev. 0.

In a read or a write operation, the CPU 11 of Figure 1 initially supplies a channel destination number and a function code to the address shift register 70. The shift register is compared under system hardware control to a destination number set in hex rotary switches, and if a match is detected the bus. 50 logic unit 128 acknowledges the match to the bus 13. As before described, the acknowledgement may be a wait, a non-acceptance (NAK), or an acceptance (ACK). If an ACK acknowledgement is issued by the logic unit 128 to the megabus 13, the logic unit in addition issues a busy signal to the megabus 13 to place subsequent bus requests in a wait state. The system hardware thereafter controls the transfer of data between megabus 13 and MPDC 10.

In order ro provide means for controlling the operation of the disk device during a read or a write operation, the CPU 11 also supplies a configuration word A to megabus 13 which under hardware control is loaded into the data register 82 and address shift register 70. Upon completing the load operation, the system hardware issues an ACK signal to the megabus 13 followed by a busy signal.

Firmware senses the busy signal, and controls the transfer of the data in address shift register 70 and 60 data register 82 through the arithmetic unit 85 for storage into scratchpad memory 81. When the firmware has completed the memory store operation, it signals the system hardware which then controls the loading of the address and data registers with a configuration word B. The configuration word B then is loaded into scratchpad memory under firmware control, and the process is repeated to receive in order a main memory address, a range count, a task and a status request. When the task is 65 8 GB 2 061 577 A 8 loaded into the data register 82 and stored in scratchpad memory 81, the task is executed under firmware control. Upon completing the task, the function code is interrogated to detect the presence of status requests which may be honored.

In the memory store operation, the firmware senses the function code to determine the scratchpad address in which information is to be stored from data register 82. Further, firmware is able to distinguish between data formats by interrogating the function code. A function code of hex 0 7 indicates that a task has been loaded into the scratchpad memory, a function code of hex 1 1 identifies a configuration word A and a function code of hex 1 3 identifies a configuration word B. In addition, a function code of hex 0 D identifies a range count (data bytes to be transferred). It is to be noted that the configuration words A and B, the task, and the range have formates as illustrated by the data field of 1/0 10 output command word of Figure 3a. A main memory address input, however, is comprised of the module number and address fields illustrated bythe 1/0 LD output command word of Figure 3a.

During a read operation wherein data is read from a disk device and stored in main memory unit 12, the system hardware loads the high order bits of a main memory address, a function code and a channel destination number from megabus 13 into the address shift register 70, and loads the low order 15 bits of the main memory address, a range or a task into the data register 82. Under firmware control, the information in the address shift register 70 is clocked through the AMUX 72 and the OR logic unit 83 to the A1 input of the arithmetic unit 85. Further, in response to a firmware command on line 106, the arithmetic control unit 91 issues a mode to the arithmetic unit 85 to select the A1 input. The A1 input to the arithmetic unit thereupon is supplied to the input of the scratchpad address counter 79, and 20 loaded into the address counter under a firmware command supplied to control line 114.

Two bits of the address shift register output on data cable 73 are supplied to the A1 input of index register 74 to indicate the disk device from which information is to be read. Under firmware control by way of control line 74a, the two identification bits are loaded into the index register. The output of the index register is supplied to the selector 115 as is the two high-order bits of the address counter 79. 25 The firmware further initializes the address counter 79 by issuing an up/down signal on control line 79a, and a clock signal on control line 79b. The counter is commanded to count up or down at the rate indicated by the firmware generated clock signal. In response to the inputs from the index register and the address counter selector 115 addresses the scratchpad memory unit 8 1. The data resident in the data register 82 thus is transferred under firmware control to the scratchpad memory address indicated by selector 115 by way of a data path through the AMUX 72, the OR logic unit 83 and data cable 117. The configuration words A and B, a main memory address, a range, and a task thereby are loaded into scratchpad memory.

Upon completing the memory store operation, the firmware accesses the function code in the address shift register 70 to determine whether a task is indicated. More particularly, the firmware supplies a hex code 0 7 by way of cable 86 to the A1 input of BMUX 84. The BMUX is selected to the A1 input via a firmware control signal control line 84a. The hex code thereupon is routed through the arithmetic unit 85 and stored in accumulator 75. Thereafter, the output of address counter 79 is channelled through the AMUX 72 and the OR logic unit 83 to the A1 input of arithmetic unit 85. Under firmware control, the arithmetic unit compares the code in the accumulator 75 with the output of the 40 address counter 79. If a match occurs, a task is indicated and the test logic unit 102 issues a signal to the firmware by way of control line 126 to initiate the execution of a next sequence of microinstructions.

In addition, the bus logic unit 128 in response to firmware control signals on line 130 sets the addressed disk device channel busy. Thereafter, any further information which is sent by way of megabus 13 to address the device for which the present task is assigned shall be acknowledged with a 45 NAK status signal.

Upon detecting the presence of a task, the firmware accesses the task stored in the scratchpad memory 81 and transfers that information through the AMUX 72 and OR logic unit 83 to the arithmetic unit 85. Under firmware control, the arithmetic unit 85 and the test logic unit 102 tests the task information to determine the command to be executed. For example, the task may indicate that a 50 disk seek, a recalibrate, a read or a write operation is required. The results of these tests are supplied by the test logic unit 102 to firmware by way of control cable 126.

In a write operation wherein data is to be read from main memory unit 12 and written on a disk device, the adapter logic unit 29 under firmware control issues a strobe to the device adapter 14 to load an internal data counter with a count of four. Further, the adapter logic unit 29 is commanded to issue a 55 sequence of four strobes to load configuration words A and B into a data buffer of the device 14. More particularly, the information is routed under firmware control from the scratchpad memory 81 through the BMUX 84 and the arithmetic unit 85 to data cables 92 and 94 leading to the device adapter 14.

Before the logic unit 29 issues a BEGIN EXECUTION command to the device adapter 14, the megabus 13 must be set up for the transfer of data. The firmware supplies two dummy bytes of offset 60 range to the BMUX 84 by way of cable 86, and controls the transfer of the bytes through the arithmetic unit 85 and along data cable 96 to the bus address register 136. The loading of the address register 136 is accomplished under firmware control on line 136a. The firmware then accesses the range information stored in the scratchpad memory unit 81, and transfers that information through the BMUX 84 and the arithmetic unit 85 to data cable 96 leading to the bus address register 136. As the range 65 9 GB 2 061 577 A 9 data is loaded into register 136, the offset range data is transferred to control unit 77. The two bytes of range data thereafter are transferred from the bus address register 136 into the control unit 77 under firmware control, and three bytes of address information in scratchpad memory are stored into the bus address register 136. The MPDC thereby is prepared for receiving data from main memory for writing on the 5 indicated disk device.

To initiate a data transfer, the firmware accesses the scratchpad memory 81 to transfer the MPDC channel number previously supplied by the CPU 11, and transfers the channel number through the BMUX and arithmetic unit 85 for storage in the bus data register 100. At this time, the main memory address from which data is to be intially read resides in the bus address register 136, and the MPDC channel destination number resides in bus data register 100.

The firmware also supplies bus logic commands to the BMUX 84 by way of cable 86, and stores those commands in the accumulator 75. From the accumulator, the commands are supplied by way of data cable 103 to the bus logic unit 128. These commands in logical sequence instruct the bus logic unit 128 to issue a response-required request to main memory to acknowledge that data is to be supplied to the MPDC, to issue a main memory channel number identifying the main memory unit as the system unit addressed, and to issue an indication as to whether the MPDC is in a byte or a word mode.

In normal operation, a read or a write command is always preceded by a seek command wherein the firmware commands the adapter device 14 to position the read-write heads of the disk device. In addition, the device adapter is instructed to select ' the proper head from which the information is to be read or written. The device adapter 14 then compares the configuration words A and B with data read 20 from the surface of the disk. If a match is detected which indicates that a designated record is in position, the device adapter 14 issues a write command to the disk device and begins to write a header gap on the record. During this period, the device adapter 14 also issues an interrupt by way of control line 110 to the hardware control unit 108. In response thereto, the control unit issues a signal to the All input of test logic unit 102 to notify firmware by way of control cable 12 that control should be turned 25 over to the before-described system hardware. Firmware thereupon issues an enable hardware command to control line 109, and further issues commands by way of control line 134 to the data control unit 113 to control the operation of FIFO unit 131 in requesting data from memory. The FIFO unit 131 operates to anticipate the availability of space in the data FIFO unit 118 for the receipt of data word from main memory. More particularly, each time the bus logic unit 128 requests a data word from 30 main memory a dummy byte is loaded into the FIFO unit 13 1. The bus logic unit 128 thereafter request a second word of data only if the dummy byte has dropped from the input register of the FIFO unit 131 into the FIFO stack. Main memory thereupon issues data words by way of megabus 13 to the data register 82.

When the bus logic unit 128 has requested a data word from main memory and accepted the 35 word, the logic unit issues a signal to the A2 input of data control unit 113. In response thereto, the control unit issues a command on control line 135 to the data FIFO unit 118 to store data from the data register 82. The above-described operation is repeated until the data FIFO unit 118 is filled with 32 bytes of data.

When the data FIF0s are filled, unit 118 issues a signal by way of control lines 11 8a to the 40 hardware control unit 108. Control unit 108 thereupon issues a strobe by way of control line 111 to the adapter logic unit 29. Logic unit 29 in turn issues a strobe to the device adapter 14 to indicate that a data byte may be transferred from the data FIF0s to the device adapter 14. The same strobe is applied by way of control lines 29a and 1 18b to the TOP (transfer out parallel) terminal of data FIFO unit 118.

The D 'I and D2 outputs of the FIFO unit thereupon are transferred through the OR Logic 83 and through 45 the arithmetic unit 85 to the device adapter 14 by way of data cables 92 and 94.

The logic unit 29 strobe also is applied by way of control line 29a to the data control unit 113 The reception of two of such strobes indicates that a two-byte data word has been transferred from the data F] FO unit 118 to device adapter 14. The data control unit 113 thereupon issues a control signal to the A2 input of FIFO unit 131 to drop a dummy byte out of the output register of the FIFO stack. The 50 input register of the FIFO unit thereby is emptied, and issues a signal to the bus logic unit 128 to initiate a request for an additional data word from main memory. The above- described process continues until the device adapter unit 14 indicates that a record has been written.

It is to be understood that the device adapter 14 controls the write operation on the disk device.

As the data is being written on the disk, the device adapter signals the test logic unit 102 by way of 55 control line 125 to cease supplying data until the internal buffers of the device adapter have been emptied. During this period, the test logic unit 102 notifies the firmware control system that control may be transferred from the hardware to the firmware. When the device adapter 14 is ready to receive additional data, the logic state of control line 125 is changed. The test logic unit 102 thereupon notifies the firmware to return control to the hardware to resume the data transfer. This process continues until 60 a data transfer is completed as indicated by a range count of zero.

Each time the bus logic unit 128 requests an additional data word, the data control unit 113 under system hardware control decrements the range counters of control unit 77 by one. Further, after a data request including a main memory address has been issued to the megabus 13 and accepted by the main memory unit 12, the control unit 77 increments the bus address register 136 by two and 65 GB 2 061 577 A 10 decrements the range counters by one. When the range count has been exhausted, the range control unit 77 issues an end-of-range (EOR) signal by way of control lines 77a and 102b to the device adapter 14 and the test logic unit 102, respectively.

It is to be noted that the control cable 125 includes two interrupt lines. A first interrupt line is a firmware request line to indicate that control should be returned to firmware while the device adapter 5 14 is between records. The second interrupt line is used to notify firmware that non-data service requests may be serviced. Such action normally i indicates that there is some type of error in the device adapter 14.

If the EOR signal is issued during a record or at the end of a record on the disk device, the firmware will terminate the write order. If the EOR signal is received by the device adapter 14 before an end of 10 record occurs, the device adapter fills the remaining portion of the record with dummy bytes. If an EOR signal does not occur, however, and there is no device adapter error indicated on interrupt cable 127, then the firmware will update the configuration words A and B in device adapter 14 to point to a next logical sector of the disk device.

FIGURE 6 Figure 6 illustrates in functional block diagram form a firmware control system for controlling the operation of the system illustrated in Figures 4 and 5.

The 12-bit output of a 16-bit return register 200 is connected to the A1 input input of a selector 201. The 12-bit output of the selector 201 in turn is applied to the input of a 16-bit microprogram address counter 202, and the 12-bit output of the address counter is connected to the input of a 4.OK by 20 16-bit Read Store (ROS) 203 having the microinstructions of a microprogram store therein. The 16-bit D 'I output of the ROS is connected to the input 1 6-bit microprogram instruction register 204, and the D2 output of the ROS is applied to the A3 input of the selector 201.

The microprogram instruction register 204 further receives a control signal from the test logic unit 102 of Figure 4 by way of a control line 126 to reset or clear the register. The 1 6-bit output of the microprogram instruction register 204 is applied to the input, a decoder 205, to the A1 input of a return register unit 200, and to the A1 input of a firmware distributor 206. A one-bit output of the register 204 is applied to the LD input of return register 200.

The D l output of decoder 205 is applied to the A2 input of the selector 201, and the D2 output of the decoder is applied to the A2 input of returnregister unit 200. Further, the D3 output of decoder 205 30 is applied to the A2 input of distributor 206. The D 1 output of the distributor is applied to control line leading to the bus logic unit 128, and the D2 output is applied to control line 134 leading to the data control unit 113. The D3 output of distributor 208 is applied to control line 127 connected to the A2 input of adapter logic unit 29, and the D4 output is applied to control line 106 leading to the arithmetic control unit 91. The D5 output is suppTied to control line 109 connected to the All input of hardware control unit 108, and the D6 output is connected to line 137 leading to the A3 input of control unit 77. The D7 output is connected to control cable 86, and the D8 output is applied to control line 114 carrying load commands to the counter 79. The D9 output is applied to control line 116, and the D1 0 output is applied to control line 124. The D1 1 output is applied to control line 70b, the D1 2 output to control line 72a and the D1 3 output to control line 84a. The D1 4 output 40 is applied to line 75a, the D 15 output to line 74a and the D 16 output to line 79a. The D 17 output is applied to line 79b and the D1 8 output to line 136a. The D1 9 output of distributor 206 is applied to the LD input of counter 202, the clock input of which is supplied by the system hardware by way of control line 207. Control line 207 further is connected to the LD input of reffister 204.

The 1 6-bit firmware commands stored in ROS 203 are divided into four fields: the OPCODE, the 45,

AMUX 7 2 select, the BMUX 84 selector and the miscellaneous fields. The firmware commands further are segmented into seven categories each representative of bit configurations for performing a designated operation. The seven basic categories of firmware commands are: miscellaneous commands, bus logic commands, ALU command constant value data commands, memory commands, test commands, and branch commands. Each of the firmware categories is identified by a particular 50 OPCODE which is a binary decode of bits 0, 1 and 2 of ROS 203.

In operation, the microprogram address counter 202 is loaded from selector 201 under firmware control, and thereafter clocked by hardware system control signals on line 207. The address counter output addresses the ROS 203, which in response thereto supplies microinstructions to the instruction register 204. The register 204 loads the microinstructions under hardware control, and applies the microinstruction bit configuration to decoder 205, distributor 206 and return register 200.

The order in which the microinstruction sequences stored in ROS 203 are executed may be controlled in any of several ways. The test logic unit 102 may issue a reset signal causing a no-op instruction to occur in the instruction register 204. The instruction register thereupon skips the current instruction in the register, and proceeds to the next occurring instruction. In the alternative, the address 60 counter 202 may be loaded with a microinstruction address formed from Read Only Store 203 and register 200. The firmware control system of Figure 6 thus offers significant versatility in the execution of microprograms.

As each microinstruction addressed in ROS 203 is loaded into register 204, the instruction bit 25.

11 GB 2 061 577 A 11 configuration and a binary code from decoder 205 identifying the instruction category are applied to distributor 206. In response thereto, the distributor applies firmware control signals to the system of Figures 4 and 5 as before described.

The operation of decoder 205 and firmware distributor 206 may better be understood by reference to Tables A-K. The OPCODES are defined in Table A, which provides a pointer to one of Tables B-K. For example, the OPCODE 0 0 0 refers to the miscellaneous commands of Table B. The OPCODE of 0 1 0 refers to Table C, the OPCODE 0 1 1 to Table D, the OPCODE 1 0 0 to Table E, and the OPCODE 1 0 1 to Table F. Further, the OPCODE 1 1 0 refersto Table G and the OPCODE 1 1 1 to Table 1.

TABLE A

Opcode Instructions Microinstructions 0 0 0 Miscellaneous 0 0 1 RFU 0 1 0 Bus Logic 0 1 1 ALU 1 0 0 Constants 1 0 1 Memory 1 1 0 Test 1 1 1 Branch TABLE B

Miscellaneous Commands Operation Binary Value MNEMONIC Hex Code No Operation oooooooooodb-oooo NOP 0 0 0 0 Clear Command 0001000000000000 CLR 1 0 0 0 Set Error Flops 000010000o0h0000 SEF 0 8 0 0 Enable Hardware Data Path 0000011000000000 EHP 0 6 0 0 Disable Hardware Data Path 0000001000000000 DHP 0 a 0 0 Reset Diagnostic Mode 0000000010000000 RSD 0 0 8 0 Set Diagnostic Mode 0000000110000000 STD 0 1 8 0 Halt 0000000001000000 H.LT 0 0 4 0 RFU 0000000000100000 0-0 2 0 Clear Flops and Registers 0000000010010000 CRF 0 0 1 0 Reset Device Adapter 0000000010001000 RDA 0 0 0 8 Set QLT (BLT Done) 0000000000000100 QLT 0 0 0 4 Set BUS ACK 0000000000000010 SBA 0 0 0 2 RFU 0000000000000001 0 0 0 1 Enable Read Path 0000011000000000 ERP 0 6 0 0 Enable Write Path 0000011000000001 EWP 0 6 0 1 12 GB 2 061 577 A 12 TABLE C Bus Logic Commands Operation Binary Value MNEMONIC Hex Code increment Address Cntr. 01 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1AC 4 1 0 0 Reset Status 01 0 0 0 0 0 0 1 0 0 0 0 0 0 0 RST 4,0 8 0 Decrement Range Critr. 01 0 0 0 0 0 0 0 1 0 0 0 0 -0 0 DRC 4 0 4 0 Cycle 01 0A.A.A,00001 0000A, CYC Set Channel Ready 01 00 0 0 0000011000 SCR 4 0 1 8 Reset Channel Ready 01 00 0 0 0000010000 RCR 4; 0 1-0 Set Register Busy 01 00 0 0 0000000100 SRB 4 0 0 4 Reset Register Busy 01 00 0 0 0 0 0-0 0 0 0 0 -l 0 RPB 4 0 0 2 Reset Interrupt Latch 01 00 10 0 0000000001 RIL 4 0 0 1 Clear Bus 01 00 0, 0 0010000110 CLB 4 0 8 6 A, A, A, A, = Select AOP MUX Input TABLE D ALU Commands Operation Binary Value MNEMONIC Hex Code AOP Negation 0 1 1.Al A 2 A, B, B, C S 0 0 0 0 1 A,, ANT NIA BOP Negation 01 1 AIA2 A, B,, B, C S 0 1 0 1 1 A, BNT NIA Zero ALU 01 1 A, A 2 A, B, B, C S 0 0 1 1 1 A, ZER NIA AOP Transfer 01 1 AI A 2 A B, B, C S 1 1 1 1 1 A, XFA NIA BOP Transfer 01 1 AI A 2 A, B, B, C S 1 0 1 0 1 A, X1713 NIA NOR A to B 01 1 AI A2 A, B, B, C S 0 0 0 1 1 A, NOR NIA NAND A to B 0 1 1: AI A 2 A 13,131 C S 0 1 0 0 1 A, NND NIA XOR A to B 01 1 ALA 2 A, 13, BI C S 0 1 1 0 1 A, XOR NIA XNOR A to B 01 1 A1A 2 A, B,, B, C S 1 0 0 1 1 A, XNR NIA AND A to B 01 1 AI A 2 A B, B, C S 1 0 1 1 1 A, AND NIA OR A to B 01 1 A, A2 A, B, B, C S 1 1 1 0 1 A,, ORR NIA AOP Plus One 01 1 AI A2 A, 13, B, C S 0 0 0 0 0 A,, INC NIA AOP Minus One 01 1 AI A2 A, B, B, C S 1 1 1 1 0 A, DEC NIA Subtract B from A 01 1 A, A2 A, 13, B, C S 0 1 1 0 0 AO SUB NIA Add A to B 01 1 AI A2 A, B,, B, C S 1 0 0 1 0 A, ADD NIA Left Shift AOP 01 1 AI A2 A, 13, B, C S 1 1 0 0 0 A, LSH NIA Carry Out In 01 1 ALA2AB,,Bil SXXXXXA,, COTI NIA Store Result In AOP 01 1 A1A2A,13013,Cl XXXXXA, SRIA NIA A0 AI A 2 A, = AOP Reg. Select 13, B, = BOP Reg. Select C = Xarry In S = Determine A or B Result Storage 13 GB 2 061 577 A 13 TABLE E

Constant Commands Operation Binary Value MNEMONIC Hex Code Load Constant to AOP 1 0 0 AI A2 A, C C C C C 0 C 0 C C LCN NIA AOP Anded With Constant 1 0 0 AI A2 A, C C C C C 0 C 1 C C ACN N/A AOP Ored with Constant 'A, A, A, C C C C C 1 C 0 0 C OCN NIA 1 0 0 -1 A, A2 A3 = AOP Reg. Select C = Value of Constant TABLE F

Memory Commands Operation Binary Value MNEMONIC Hex Code Memory Write 1 0 1 AI A 2 A3 1 0 0 0 0 0 0 0 0 A, MWT NIA Increment SP Address 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 IMA A 1 0 0 Decrement SP Address 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 DMA A 0 0 S Memory Write & Inc. 1 0 1 AI A 2 A3 1 1 0 0 0 0 0 0 0 A, WIA NIA Memory Write & Dec. 1 0 1 AI A 2 A3 1 0 0 0 0 0 1 0 0 A, WDA NIA Set SP 'rest Mode 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 SPT A 0 8 0 RFU 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 A 0 4.0 Load Requesting Channel 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 LRC A 0 2 0 Load Index Reg.

With AOP 1 0 1 A, A 2 A3 0 0 0 0 1 1 0 0 0 A, LIR NIA Set Module Bad Parity 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 MBP A 0 0 4 RFU 1 0 1 0 0 0 0 0,0 0 0 0 0 0 1 0 A 0 0 2 A,, A, A2 A, = AOP Reg. Select 14 TABLE G

Test Commands GB 2 061 577 A 14 Operation Binary Value MNEMONIC Hex Code Test for Zero 1 1 0 A, A2 A, 0 0 0 1 T T TTTA, TFZ NIA Test for One 1 1 0 AI A2 A, 0 0 1 0 T T TT TA,, TFO NIA Return 1 1 0,0 0 0 1 0 0 0 0 0 0 0 0 0 RTN C 2 0 0 AD AI A 2 A, = AOP Reg. Select. T = Test Nux Input.

TABLE H

Test Parameters 1NEMONIC FUNCTION HEX CODE DESCRIPTION

TAHR HDTSRQ40 00 Adapter Hardware Request TBCA SHRCOM+00 01 Bus Cycle Active TRSP 13SRSVP+30 02 Bus Response Required TEQZ ALUEQZ40 03 ALU Output Equals 00 TEQF ALUEQF40 04' ALU Output Equals FF TCOT ALUCOT+00 05 ALU Carry Out TREQ CREREQ+00 06 Channel Request TACK ACKRSP40 07 Bus Ack Response TAXO ALUAXO-00 08 AOP Multiplexer, Bit 0.

TAX1 1 09 Bit 1 TAX2 2 OA Bit 2 TAX3 3 OB Bit 3 TAX4 4, OC Bit 4 TAX5 5 OD Bit 5 TAX6 6 OE Bit 6 TAX7 ALUAX7-00 OF AOP Multiplexer, Bit 7 TORZ ORCAR3-00 10 Offset Range Zero TRCZ EOR(XXX)+00 11 Range Zero TSBS SI3SOBS+00 12 Single Byte Stored TSAW SPAWRP40 13 SP Address Wraparound TADB BUSY(Xx)+00 14 Adapter Busy TNDR NDTSRQ+00 15 Non-Data Service Request TORH OFRNGZ=00 16 Offset Range History TDSN MYDCNN-00 17 Mv Data Cycle Now TBSY 13DRIBSY+00 18 Bus Data Register Busy TUBR UBRO(XX)40 19 Unsolicited Bus Request TINT RESTNT=00 1A Resume Interrupt TNAK NAKRSPA0 113 NAK Response TBYT BSAD23+00 1C Byte Mode TATY BSPYCK+00 1D Bus Parity Check TNBR N0HTRQ40 1E No Buffer Request TFDR FDTSRQ40 1F Firmware Data'Service Request z GB 2 061 577 A is TABLE 1

Branch Commands Operation Binary Value MNEMONIC Hex Code Go To 1 1 1 1 A A A A A A A AAA A GTO F X X X Load Return 1 1 1 0 1 A A A A 1 A A A A A A A A LRA E X X A A = Branch Address TABLE J

AOP Multiplexer Input Selection A,, A, A, A, Selected Register (SRIA) MNEMONIC Selected Register (SRIA) MNEMONIC 0 0 0 0 Accumulator AAW Accumulator AAW 0 0 0 1 Scratch Pad Memory ASPM Scratch Pad Memory ASPM 0 0 1 0 Scratch Pad Address ASPA Scratch Pad Address (INDEXED) ASPA 0 0 1 1 Index Register AIDX Scratch Pad Address (INDEXED) ASPAI 0 1 0 0 Adapter Data Register AADO Adapter Data Register AADO 0 1 0 1 Adapter Device]D AADI Adapter Data Counter AA131 0 1 1 0 Adapter Status 1 AAD2 Adapter Command Register AAD2 0 1 1 1 Adapter Status 2 AAD3 Adapter Unit Select AAD3 1 0 0 0 Bus Address Out ABUSI Bus Register In ABUS1 1 0 0 1 Bus Data Out 1 ABUS2 Bus Data In 1 ABUS2 1 0 1 0 Bus Data Out 2 ABUS3 Bus Data: I n 2 ABUS3 1 0 1 1 Bus Range Out ABUS4 Bus Address In ABUS4 1 1 0 0 Adapter RFU AAD4 Reset Adapter Index Count AAD4, 1 1 0 1 Adapter RFU AAD5 Adapter Status & FIFO Clear AAD5 1 1 1 0 Adapter RFU AA136 Adapter Seek Pulse AAD6 1 1 1 1 Adapter RFU AAW Adapter Data Byte Taken AAD7 SRIA and SRIA = Store Result in Selected AOP Register.

0) G) m N 0 0) (n -j -4 C) 1 17 TABLE K

BOP MUX Input GB 2 061 577 A 17 B, B1 Selected Data Input MNEMONIC 0.10 Accumulator BACH 0 1 Scratch Pad Memory BSPM 1 0 Bus Status: BBST 0-3 (Zeros) 4,Bus Yellow Ind.

Bus NAK 6 Bus Parity Error 7 Bus Red Ind.

1 1 BOP Constant The instructions of Tables C-G and 1 include A-fields comprised of bits Ad-A,. Each of the Afields refer to registers providing data to the AMUX 72 of Figure 4. Table D further includes instructions having a B-field comprised of bits B. and B,. The B-field is defined by Table K, wherein it is indicated that the BMUX may be selected to the accumulator 75, the scratchpad memory unit 8 1, to the bus logic unit 128 by way of cable 88 for bus status inputs, and to the firmware control system by way of cable 86 for a constant value input. Where two-byte arithmetic is being performed by the arithmetic unit 85, the C-field of Table D is ued to provide a carry-in feature wherein the result of a previous AU 85 operation may be used in a subsequent operation. The F-field of the instructions of Table D provides a command to store the result of the AU 85 operation into a register designated by the A-field. The remaining low-order bits of Table D refer to the mode select bits for commanding the AU 85 to perform the indicated operation.

The instruction set of Table E includes a C-field for constant values, and the low-order bits of the instructions of Table F provide for the generation of strobes for loading the registers indicated by the A- field thereof. The instruction set of Table G includes test or T-fields which are defined by the entries of 15 Table 11. The A-field of Table 1 refers to the address of the microprogram to which a transfer is to be made.

Table L provides a cross-reference between the mnemonics used in the Tables A-K and the component parts of t6e system described in Figures 4-8.

18 GB 2 061 577 A 18 TABLE L

Microins.truction Mnemonic RFU Bus Logic ALU Accumulator Scratchpad Memory Scratchpad Address BLT Address Counter Range Counter AOP BOP SP Address Memory Hardware Device Reserved For User Bus logic unit 128 Arithmetic Unit 85, Arithmetic Control Unit 9 1, Accumulator 75 Accumulator 75 Scratchpad Memory Unit 81 Scratchpad Address Counter 79 Bus Logic Tests Bus Address Counters 300, 302 and 303 Range Counters 306-309 AMUX 72 BMUX 84 Scratchpad Address Counter Scratchpad Memory Unit 81 FIGURE 7 Figure 7 illustrates in a more detailed functional block diagram form the range and offset range control unit 77, the addr'-ess multiplexer 133 and the bus address register-E36.

A bus address counter 300 receives data from AU 85 on an 8-bit data cable 96, and load commands from firmware on control line 136a. The clock input to counter 300 is connected to the clock input of a bus address counter 302, to the clock input of a bus address counter 303, and to the output of an address clock logic unit 304. The 8-bit output of the counter 300 is applied to the megabus 13 by way of a data cable 305, and to the data input of counter 302.

In the preferred embodiment described herein, address counters 300, 302. and 303 form a 24-bit 10 memory address up counter.

- The load input of counter 302 is connected to control line 136a and to the load inputs of counter 303, a range counter 306, a range counter 307, an offset range counter 308, and an offset range counter 309. The counters 306 and 307 form a 16-bit range down counter, and the counters 308 and 309 form a 1 6-bit offset range down counter. The 8-bit output of counter 302 is applied to the A1 input 15 of an address multiplexer 310, and to the data input of counter 303. The 8-bit ouput of of counter 303 is applied to the A1 input of an address multiplexer 311, and to the data input of range counter 306.

Address multiplexer 310 also receives at its A2 input data from data register 82 of Figure 4 by way of cable 139. The 8-bit output of the multiplexer is applied to a data cable 312 leading to megabus 13. The select (SEL) input to multiplexer 310 is supplied by the bus logic unit 128 on a control line 313. 20 The address multiplex&-r31 1 also receives data from the data register 82 by way of data cable 140, and supplies 8 bits data to a data cable 314 leading to megabus 13. The SEL input to multiplexer 311 is connected to the SEL input of multiplexer 310.

The 8-bit output of range counter 306 is connected to the input of range counter 307. The output of counter 307 in turn is applied to the input of counter 308, and the 8- bit output of counter 308 is 25 applied to the input of counter 309. The 8-bit output of counter 309 in turn is applied to control line 76 leading to the A3 input of AMUX 72.

The clock source for the system of Figure 7 is a 4.0 MHz oscillator 315, which supplies clock signals to address clock logic unit 304 and a range clock logic unit 316. The logic unit 304 receives enable signals from bus logic unit 128 and from firmware on control lines 317 and 318, respectively. In 30 response thereto, the logic unit 304 issues increment commands to counters 300, 302 and 303.

The range clock logic unit 31 g-receives enables signals from bu's logic unit 128, the firmware and 19 GB 2 061 577 A 19 the data control unit 113 byway of control lines 319-321, respectively. Further, the control unit 113 supplies an offset range enable signal to the EN4 input of logic unit 316. When enabled, the logic unit 316 supplies decrement commands to counters 306-307 or counters 308-309.

If data is to be read from or written onto a disk device controlled by the device adapter 14, the CPU 11 of Figure 1 supplies a channel destination number and a function code to the address shift register 70 of Figure 4 as before described. In addition, the CPU supplies configuration words A and B, a main memory address, a range count, an offset range count, a task and a status request to the data register 82. The firmware accessesthe function code in register 70 to detect the address in scratchpad memory unit 81 in which the data of register 82 is to be stored.

The firmware then serially shifts seven bytes of data a byte at a time from scratchpad memory unit 10 81 into address counters 300, 302 and 303, range counters 306 and 307, and offset range counters 308 and 309. Upon completion of the load operation, a main memory address resides in address counters 300, 302 and 303, a range count in counters 306-307, and an offset range count in counters 308-309.

In a read operation wherein data is to be read from the disk device and written into main memory unit 12, the megabus 13 is supplied both data and a 24-bit address in main memory in which the data is to be written. More particularly, the data resides in the bus data register 100. When a data word comprising tw d ata bytes is to be transferred from the MPDC 10 to the megabus 13, the bus logic unit 128 selects the multiplexers 3 10 and 311 to the A1 inputs. The main memory module to which the data ii to 6e transferred thereby is' made available to the megabus 13. The main memory address in 20 which the transferred data is to be written thereupon is supplied from address counters 300, 302 and 303 to cables 305, 312 and 314 respectively. Each time the main memory unit issues an acknowledgement signal and accepts data into the indicated address, the main memory address in counters 300, 302 and 303 is incremented by two.

During a data transter trom device adapter 14 to.MPDC 10, the data control unit 113 of Figure 5 25 issues a logic one signal to control - line 322 each time a data byte is transferred. The range clock logic unit 316 is enabled thereby to decrement the offset range counters 308 and 309. The output of counter 309 is applied by way of cable 76 to the AMUX 72 and the AU85 of Figure 4. As long as the offset range count is greater than zero, the data bytes are ignored and are not transferred to megabus 13.

When the offset range count is exhausted, however, data transfer control switches from the offset range 30 counters to the range counters 306 and 307. More particularly, the data control unit 113 disables the EN4 input to logic unit 316, and thereafter issues enable signals to the EN3 input of the logic unit by way of control line 32 1. The logic unit 316 in response thereto decrements the range counters each time a data byte is transferred from the device adapter 14 to the MPDC 10. Each of the data byteg transferred after control switches to the range counters are transferred to megabus 13. 35 When the range count in counters 306 and 307 is exhausted, counter 307 issues an end-of-range (EOR) signal on lines 77a and 102b as before described.

A write operation wherein data is read from main memory and written onto a disk device is accomplished in a manner similar to that of the read operation. A channel destination number and a function code are loaded into the address shift register 70, and data including configuration words A and 40 B, a main memory address, a range count, a task and a status request are loaded from data register 82 into scratchpad memory unit 81. An offset range count is not used in writing data onto a disk device.

After the device adapter 14 has positioned the write heads of the disk device, and issued a hardware service request signal on line 110 of Figure 4, firmware loads two dummy bytes into the offset range counters 308 and 309, a range count into counters 306 and 307, and a main memory 45 address into counters 300, 302 and 303. The firmware further transfers an MPDC channel number from scratchpad memory unit 81 to the bus data register 100, and thence through data multiplexer 122 to megabus 13. Under firmware control, the bus logic unit 128 issues a response-required data request to main memory, and selects the multiplexers 3 10 and 311 to their A2 inputs to supply the main memory 50 channel number in address shift register 70 to megabus 13. The bus logic unit thereafter selects the multiplexers 310 and 311 to their A1 inputs to supply the main memory address to megabus 13.

Each time the bus logic unit 128 requests an additional data byte from main memory, the logic unit also issues a logic one signal to control line 319 to enable the range clock logic unit. The range counters 306 and 307 thereupon are decremented by one. Further, after a data request and a main memory address have been issued to megabus 13 and accepted by the main memory unit 12, the bus 55 logic unit 128 enables the EN 1 input of the address clock logic unit 304. In response thereto, the address counters 300, 302 and 303 are incremented by two.

When the range count has been exhausted, counter 307 issues an EOR signal to lines 77a and 102b as before described. The data transfer from main memory unit 12 to disk device 14 thereby is designated complete.

The system of Figure 7 represents a significant improvement over prior firmware data transfer controls, which required too much time for bookkeeping. Previously, bookkeeping parameters were stored in memory, and had to be retrieved and restored when a parameter was updated. In the instant hardwaare/firmware invention, the bus address counters 300, 302 and 303, the range counters 306-307, and the offset range counters 308-309 maybe loaded serially to substantially decrease 65 GB 2 061 577 A 20 the number of microinstructions required in a load operation. Further, during a data transfer, the counters may be incremented or decremented under hardware control to accommodate an increased data flow rate.

FIGURE 8 Figure 8 illustrates in detailed logic diagram form the FIFO unit 131 of Figure 5, which embodies 5' the invention described herein.

In referring to the electrical schematics illustrated in the Figures, it is to be understood that the occurrence of a small circule at the input of a logic device indicates that the input is enabled by a logic zero. Further, a circle appearing at an output of a logic device indicates that when the logic conditions for that particular device are satisfied, the output will be a logic zero.

An AND gate 400 has one input connected to a control line 401, and a second input connected to both a control line 402 and one input of an AND gate 403. A second input to gate 403 is connected to a control line 404 leading to line 110 of Figure 4, and a third input is connected to a control line 405.

The output of gate 400 is connected to the D input of a flip-flop 405, and to the D input of a flip- 15 flop 406. The output of gate 403 is applied to the trigger (T) input of a flip-flop 407.

The trigger input to flip-f lop 405 is connected to the Q output of flipflop 407, and the reset input of flip-flop 405 is connected to the output register (OPR) output of a 1 6-word by eight bit FIFO 408.

When the OPR output is at a logic 1 level, the output register is filled. Further, when the OPR output is at a logic zero level, the output register is empty. The'llof flip-flop 405 is applied to the transfer on parallel 20 (TOP) input of FIFO 408.

TheU output of the flip-flop 407 is connected to its D input, and to the T input of flip-110p 406. The reset input to flip-flop 406 is connected to the OPR output of a 1 6-word by 8 bit FIFO 410. The Cl output of the flip-flop 406 is connected to the TOP input of FIFO 410, and to the TOP input of a 1 6-word by a 8 bit FIFO 411.

The load (LD) input to FIFO 408 is connected to a control line 412, and the data input to the FIFO is connected to a data cable 408a leading from data register 82 of Figure 4. The parallel data output of FIFO 408 is connected to a data cable 408b leading to cable 94. The LD input to FIFO 410 is connected to a control line 413, and the data input to the FIFO is connected to a data cable 41 Oa leading from data register 82. The parallel output of the FIFO is applied through a data cable 41 Ob to cable 94.

The LD input to FIFO 411 is connected to the output of an AND gate 414. The input register (IPR) output of the FIFO 411 is connected by way of a control line 415 to one input of an AND gate 416. The IPR output is k a logic one level when the input register is empty, and at a logic zero level when the input register is filled. The OPR output of FIFO 411 is applied by way of a control line 411 b to line 102b of Figure 5.

A second input to gate 416 is connected to a third input to gate 403, and to a control line 417. A third input to gate 416 is connected to one input of gate 414, and to a control line 416a. The output of gate 416 is applied to the T input of a flip-flop 418, the Q output of which is applied to a control line 419 leading to the bus logic unit 128.

T - he D input to flip-flop 418 is connected to the output of an AND gate 420, one input of which is 40 connected to a control line 42 1. A second input to gate 420 is connected to a control line 422.

A second input to gate 414 is connected to control line 417, and a third input to gate 414 is connected to a control line 423.

In a write operation wherein data is read from the main memory 12 of Figure 1 and written into a disk device serviced by the device adapter 14, a problem may arise during the transfer of a sequence of 45 data bytes. If a request for additional data i - s not issued by the MPDC 10 when a data byte is received from the main memory unit 12, other system devices may intercede to communicates with the memory unit. The MPDC thus would not be able to maintain a transfer rate to the disk device. If a request for data - is made without regard for empty buffer locations, data stored in the data register 82 of Figure 4 may be lost before the full range of data to be transferred from main memory has been written upon the disk 50 device. The logic system of Figure 8 provides a means for obviating such a problem.

In operation, when data is to be transferred from the main memory unit 12 to the MPDC 10; firmware issues a logic 1 signal to control line 417. If the megabus 13 is clear for a data transfer, the bus logic unit 128 of Figure 5 issues a logic 1 signal to control line 422 to indicate that the megabus 13 is ready. Further, until the data transfer is completed, the control line 421 leading from the range and - offset range control unit 77 remains at a logic 1 level to indicate that the range count has not been exhausted. The output of gate 420, therefore, it at a logic 1 level which is applied to the D input of the flip-flop 418.

Prior to any data being transferred to the MPDC 10, the FIFO's 408, 410 and 411 are empty. The iPR output of FIFO 411 thus is at a logic 1 level indicating that the input register is empty. Further, the 60 bus logic unit 128 supplies a logic 1 signal to control line 41 6a during a time period when the MPDC 10 is not using the megabus 13 in servicing a bus cycle request. Thus, the output of the gate 416 is at a logic 1 level to toggle the flip-flop 418, thereby issuing a bus cycle request on line 419 leading to the bus logic unit 128.

25, 21 GB 2 061 577 A 21 In generating a bus cycle request for output on the megabus 13, the bus logic unit 128 issues a logic 1 signal to control line 423 to indicate that an MPDC 10 bus cycle request has been issued. The firmware control signal on control line 417 thereupon is applied through gate 414 to the load input of FIFO 411. A dummy byte thereby is loaded into the FIFO under firmware control, and the IPR output of the FIFO transitions to a logic zero level. It is thus seen that each time a cycle request is generated at 5 the Q output of flip-flop 418 to request additional data from main memory unit 12, a dummy byte is loaded into the FIFO 411. When the main memory unit responds to the bus cycle request, the bus logic

unit 128 issues a logic zero signal to control line 423 and a logic 1 signal to control lines 412 and 4.13. Data bytes supplied by the main memory unit 12 to the megabus 13 thereby are loaded from data cables 408a and10 41 Oa into FIFO 408 and FIFO 410, respectively. The bus logic unit 128 thereupon transitions the control line 416a to a logic 1 level to indicate that the bus cycle request for data has become inactive. If the dummy data byte loaded into the FIFO 411 has dropped from the input register into the FIFO stack, the IPR output of the FIFO will transition to a logic 1 level to again trigger the flip-flop 418 to issue another cycle request on control line 419.

The above-described process continues until the FIF0s 408 and 410 are filled as indicated by the output register (OPR) outputs of the FIF0s. The FIFO 411 thus serves to indicate in advance that if a data word is loaded into the data FIF0s 408 and 410, the data word will pass into the FIFO stack before another data word can be requested of main memory unit 12. More particularly, each time a data request is made to main memory unit 12 a dummy byte is loaded into the FIFO 411. If the dummy byte 20 has passed into the FIFO stack before a next data request is made to main memory, then the time delays are such that it is known that the data bytes in the FIF0s 408 and 410 shall pass into the respective FIFO stacks before additional data bytes are received from main memoy 1 When the FIFO units 408 and 410 are filled with data, the OPR outputs of the FIFO units are at a logic zero level indicating a filled condition. Further, the IPR output of FIFO 411 is at a - logic zero level. The 25 gate 416 thus is disabled, and the generation of cycle requests on control line 419 is terminated.

When the OPR output of FIFO 411 transitions to a logic 1 level to indicate that the data FIF0s 408 and 410 are filled, the hardware control unit 108 issues a strobe to the adapter logic unit 29. The logic unit 29 in turn issues a strobe to the device adapter 14 to indicate that the data FIF0s may be emptied.

The device adapter 14 thereupon issues a logic 1 hardware service request signal to control line 404, 30 and the firmware in response thereto issues a hardware enable signal to control line 402. The firmware further issues a logic 1 signal to control line 401 to indicate that a write on disk operation has been initiated.

The fiip-f lop 407 is triggered by the output of gate 403, and toggled between set and reset conditions. For example, if the flip-flop is in a set condition, it resets upon being triggered. Further, if the 35 flip-flop is in a reset condition, it sets upon being triggered. The Q and G outputs of the flip-flop alternately trigger the flip-f lops 405 and 406 respectively. If the flip- flop 405 is triggered, the Q output of the flip-flop is applied to the TOP input of the FIFO 408. In response thereto, the data byte in the output register of the FIFO is supplied to data cable 408b leading to the device adaptor 14. When the output register is emptied, the OPR output of the FIFO 408 immediately resets the flip-flop 405. In like 40 manner, when the flip-flop 406 is triggered, theUoutput of the flip-flop supplies an unload signal to the FIFO 410. When the output register of the FIFO is emptied, the OPR output of the FIFO resets the flip flop 406. It is apparent that the flip-flop 407 in combination with the flip-flops 405 and 406 alternately selects data bytes from FIFO 408 and FIFO 410. The data bytes transmitted to the device adapter 14 thus are comprised of a left byte from FIFO 408 and a right byte from FIFO 410.

Each time the FIFO 410 is unloaded, the FIFO 411 also is unloaded. As soon as the input register to the FIFO 411 is emptied, the IPR output of the FIFO transitions to a logic 1 level to generate a cycle requests as before described. As data bytes are loaded into the FIF0s 408 and 410, the FIF0s again are unloaded. Before a cycle request for a next data byte is requested from main memory unit 12, however, the input register to the FIFO 411 must be emptied.

Two conditions may occur which may prevent the generation of a cycle request on control line 419 when the input register to FIFO 411 is empty. When the range count indicating the total number of data bytes to be transferred from main memory unit 12 to the device adapter 14 is exhausted, line 421 transitions to a logic zero. Further, if an unsolicited bus request or other data occurs on the megabus 13 to cause the MPDC 10 to issue a NAK, the gate 420 is disabled. The 0 output of the flip-flop 418 thus 55 does not transition to a logic 1 level when triggered, and no further cycle requests may be made.

In summary, the system is comprised of a logic data transfer control system responsive to both firmware and hardware control, and including data FIF0s operating in parallel with a predictor FIFO.

Each time a data word is loaded from main memory to the data FIF0s, the input register of the predictor FIFO is sensed. If the input register is empty, a data request is issued to main memory and the predictor 60 FIFO is loaded with a dummy byte. Since no data request is issued unless the input register of the predictor FIFO is empty, no data is lost.

When the data FIF0s are filled, the predictor FIFO is filled and no further data requests may be made without unloading data bytes to the disk device. Each time the right data FIFO is unloaded the predictor FIFO is unloaded. Synchronization between the predictor FIFO and the data FIFO thereby is 22 GB 2 061 577 A 22 provided.

The look-ahead characteristic of the predictor FIFO may be seen in the sequence of operating steps. When a data request to main memory is made, the predictor FIFO thereafter is loaded with a dummy byte. The data FIF0s, however, are not loaded until a data byte is received from main memory.

Thus, is the dummy byte in the predictor FIFO had dropped into the FIFO stack by the time a data word 5 is loaded into the data FIF0s, a prediction can be made that the newly received data word will drop into the FIFO stacks before a next data word is received. Under these conditions, a next request for data is issued to main memory.

FIGURE 9 Figure 9 is a timing diagram illustrating in graphic form the operation of the system of Figure 8. 10 It is is to be understood that the system disclosed herein is comprised of devices in intercommunication on an asynchronous bus. Thus, absolute time values are not disclosed in the description of the timing diagrams of Figures 9-11. It is the order of occurrence rather than the absolute time of occurrence which is of primary importance.

Referring to Figure 9, a waveform 501 illustrates a signal issued by firmware to place the MPDC 15 into a write mode, and a waveform 502 illustrates a cycle request signal issued by the bus logic unit 128 of Figure 5 in response to firmware commands. A waveform 503 illustrates a bus cycle request made by the MPDC 10 to the megabus 13, and a waveform 504 illustrates a strobe issued by the bus logic unit 128 to set the cycle request logic signals of waveform 502 onto the megabus 13 as indicated by waveform 503. A waveform 505 illustrates a logic signal formed on the megabus 20 13 in response to the logic signals of waveforms 503 and 504. A waveform 506 illustrates a waveform generated in the MPDC 10 to indicate that the MPDC is busy. A waveform 507 illustrates a logic signal issued by a slave to the megabus 13 in response to a bus request issued by a master device. A waveform 508 illustrates an acknowledgement logic signal issued by the MPDC 1.0 to the megabus 13 in response to a second-half bus cycle signal from the main memory unit 12 as 25, illustrated by a waveform 509. A waveform 510 illustrates the load signal issued by the gate 414 to the FIFO 411 of Figure 8, and a waveform 511 illustrates the logical inverse of the input register output of the FIFO 411. A waveform 512 illustrates the logic signal issued by the output register of the FIFO 411 when the data FIF0s 408 and 410 are filled.

In the mnemonics used to describe the waveforms 501-512 in Figure 9, a plus sign (+) indicates 30 that the condition signified by the mnemonic occurs when the associated waveform is at a logic 1 level.

A negative sign (-) indicates that the designated condition occurs when the waveform is at a logic zero level.

When data is to be written from main memory unit 12 of Figure 1 to a disk device serviced by the device adapter 14, firmware transitions the control line 417 of Figure 8 to a logic 1 level as indicated at 501 a of waveform 501. Since the bus cycle is not active as indicated at 506a of waveform 506, the MPDC 10 is not engaged in servicing a previous bus cycle request. Thus the control line 416a is at a logic 1 level, and a logic 1 signal issued by the input register FIFO 411 as illustrated as 511 a of Figure 11 is applied through the gate 416 to trigger the flip-flop 418. The 0 output of flipflop 418 thereupon transitions to a logic one level as illustrated at 502a. The cycle request 502a thereby is placed onto the megabus 13 a control line 419. When a cycle of the megabus 13 is available, the bus logic unit 128 of Figure 5 will issue a logic 1 pulse 504a to place the cycle request 502a onto the megabus 13 as illustrated by the logic 1 pulse 503a. The signal appearing on the megabus 13 in response to the pulses 503a and 504a is illustrated by a logic 1 pulse 505a of waveform 505.

The bus logic unit 128 issues a logic 1 pulse 506b concurrently with pulse 504a to indicate that 45 the bus cycle is active, i.e., the MPDC 10 is busy. In response thereto, the output of gate 414 transitions to a logic 1 level as illustrated by a logic 1 pulse 51 Oa to load a dummy byte into the FIFO 411. Upon receiving the bus cycle request from the MPDC 10, the main memory unit 12 acknowledges its acceptance of the request by issuing a logic 1 pulse 507a of waveform 507.

When the dummy byte is loaded into the FIFO 411, the waveform 511 transitions to a logic zero 50 level as indicated at 511 a. Since gate 416 will be disabled during the time period that waveform 511.

remains at a logic zero level, no further bus cycle requests may be made until the waveform again transitions to a logic 1 level.

When the main memory unit 12 has retrieved a requested data word and placed it on the megabus 13, the memory unit issues a logic 1 pulse 509a to indicate that the data is available 55 Further, the memory unit issues a logic 1 pulse 505b. Upon receiving the pulses 505b and 509a, the bus logic unit 128 issues an acknowledgement logic 1 pulse 508awhich appears on the megabus 13 as logic 1 pulse 507b. Upon receiving the pulse 507b, the main memory unit releases the megabus 13 to accommodate another bus cycle request. Upon issuing the pulse 508a, the MPDC 10 is no longer in a bus cycle active state as indicated at 506c. Since the output of the input register of the FIFO 411 is 60 again empty as indicated at 511 b, a logic 1 pulse 502b is supplied at the G output of flip-flop 418 to initiate a next bus cycle request operation.

r 23 GB 2 061 577 A 23 FIGURE 10 Figure 10 is a timing diagram illustrating the operation of the system of Figures 4-8 during a data transfer from a disk device to megabus 13.

A waveform 600 illustrates the hardware data service request signal issued by the device adapter 14 to control line 110 of Figure 4, and a waveform 601 illustrates the hardware enable signal -issued by firmware in response to the waveform 600. A waveform 602 illustrates a hardware data service enable signal which is a logical AND of waveforms 600 and 601. Waveform 602 illustrates the enable signal applied by firmware to the EN2 enable input of range clock logic unit 316 of Figure 7 during diagnostic tests.

A waveform 603 illustrates the output of range clock logic unit 316 in response to the enable 10 signal illustrated by waveform 602. A waveform 604 illustrates the output of gate 403 of figure 8, and the output of the adapter logic unit 29 of Figure 4. A waveform 605 illustrates the inverse to the output of flip-flop 407 of Figure 8.

Waveforms 606 and 607 each are formed from waveforms 604 and 605, and indicate the output states of the flip-flop 407. A waveform 608 illustrates the bus cycle request,ignals issued at the Q 15 output of flip-flop 418 of Figure 8, and a waveform 609 illustrates the pulse pairs generated by the address clock logic unit 304 each time a cycle request is made as illustrated by waveform 608.

When data is to be read from a disk device, the device adapter 14 of Figure 4 issues a logic 1 pulse 600a to control line 110 to indicate that a data byte is available for transfer to the MPDC 10. In response thereto, the firmware control system of Figure 6 issues an enable hardware pulse 601 a to the 20 control line 109 of Figure 4 leading to the hardware control unit 108. As the data byte is transferred from the device adapter 14 to the MPDC 10, the timing signal illustrated by waveform 602 is applied to the range clock logic unit 316 of Figure 7. In response thereto, the offset range counters 308 and 309 are decremented until the offset range count is exhausted. The range counters 306 and 307 thereafter are decremented as illustrated by the logic 1 pulses of waveform 603.

Each time data bytes are transferred from the device adapter 14 to the MPDC 10, the output of gate 403 as illustrated by the waveform 604 triggers the flip-flop 407. When the Q output of flip-flop 407 is at a logic 1 level, flip-flop 405 is triggered to load a left byte in bus data register 100 for transfer to the megabus 13. This condition is illustrated by the logic 1 levels of waveform 605 and waveform 607. When the U-output of the flip-flop 407 transitions to a logic 1 level, the flip-flop 406 is triggered to 30 load a right byte in register 100 for transfer to the megabus 13. This condition is illustrated by the logic zero levels of waveform 605 and the logic 1 levels of waveform 606.

When a data word comprising a left and a right data byte have been formed in the register 100, the bus logic unit 128 under firmware control issues a bus cycle active signal to control line 416a of Figure 8 to trigger the flip-flop 418. A bus cycle request thereby is generated as illustrated by the logic" 35 levels of waveform 608. Each time a busy cycle request is generated, the bus Iodic unit 128 enables the address clock logic unit 304 to issue logic 1 pulse pairs as illustrated by waveform 609. The main memory address stored in the bus address counters 300, 302 and 303 thereupon is incremented by two.

Should an interim condition arise wherein data is not available for transfer to the MPDC 10 before 40 the range count has been exhausted, the device adapter issues an interrupt to line 125 of Figure 4 to return control from the system hardware system to the firmware. In that event, the enable hardware signal of waveform 601 transitions to a logic zero level as indicated at 60b. No further MPDC activity occurs until the device adapter 14 indicates that data again is available for transfer by issuing a logic 1 pulse 600b to line 110 of Figure 4. The data transfer thereafter continues as before described until the 45 range counter is exhausted.

FIGURE 11 Figure 11 is a timing diagram illustrating the operation of the system of Figures 4-8 during a write operation.

A waveform 700 illustrates the hardware data service request signal issued by the device adapter 50 14 to the control line 110 of Figure 4, and a waveform 701 illustrates a strobe signal issued by the adapter logic unit 29 to control lines 29a and 1 18b of Figure 4. A waveform 702 illustrates the output of gate 403 of Figure 8, and a waveform. 703 illustrates the logic inverse of the Q output of the flip-flop 407. A waveform 704 illustrates the logic inverse of the dof flip-flop 405, and a waveform 705 illustrates the output register (OPR) output of FIFO 408.

A waveform 706 illustrates the logic inverse of the-U output of flip-flop 406, and a waveform 707 illustrates the OPR output of flip-flop 410. A waveform 708 illustrates the OPR output of FIFO 411, and a waveform 709 illustrates the logic inverse of the IPR output of FIFC 411. A waveform 7 10 illustrates the Q output of flip-flop 418, and a waveform 711 illustrates a bus cycle request signal generaged by the bus logic unit 128 in response to the waveform 7 10.

A waveform 712 illustrates a bus cycle active signal placing the MPDC 10 in a busy state in response to the bus cycle request pulses of waveform 711. A waveform 713 illustrates a data cycle signal issued by the bus logic unit 128 to indicate a time period in which the main memory unit 12 must acknowledge a data request from the MPDC 10. A waveform 71 illustrates the bus request and 24 GB 2 061 577 A 24 acknowledgement pulses occurring on the megabus 13 as a result of the handshaking between the MPDC and the main memory. A waveform 715 illustrates the bus acknowledgement pulses issued by a slave system device in response to a bus request from a master system device, and a waveform 716 illustrates MPDC acknowledgement pulses which are reflected in the pulses of waveform 715. A waveform 717 and a waveform 718 respectively illustrates address increment pulses and range 5 decrement pulses generated during the transfer of data from main memory unit 12 to the device adapter 14.

Prior to the transfer of data from main memory, the device adapter 14 positions the write heads of a disk device at a designated record. After the disk device is prepared for a write operation, the adapter 14 issues a hardware service request signal as illustrated by pulse 700a to the control line 110. The bus 10 logic unit 128 thereupon requests data from the main memory unit 12. The main memory unit 12 in response thereto, supplies data to the data register 82 of Figure 4. Under control of the data control unit 113, the data is transferred from data register 82 into the data FIF0s 408 and 410. When the data FIF0s are filled, the hardware control unit 108 signals the adapter logic unit 29. The logic unit 29 in turn issues a strobe pulse 701 a to the device adapter 14 to indicate that a data byte is being transferred.

Concurrently, gate 403 of Figure 8 issues a pulse 702a to select a data byte from one of the FIF0s 408 and 410 for transfer to the device adapter 14. In response to the gate 403 output, flip-fiop 407 of Figure 8 issues a pulse 703a to trigger the flip-flop 405. Flip-flop 405 in turn issues a pulse 704a to select a data byte from the FIFO 408.

When the data byte is taken from the output register of the FIFO 408, the OPR output of the FIFO 20 transitions to a logic zero level as indicated at 705a. The OPR output further resets the FI FO 405 as indicated at 704b of waveform 704. When the data byte has been taken by the device adapter 14, the adapter issues a second hardware data service request pulse 700b. In response thereto, the adapter logic 29 pulse 701 b and the gate 403 ISulse 702b are generated as before described. Upon the occurrence of pulse 702b, the-Uoutput of the flip-flop 407 triggers the flip-flop 406 as indicated at 703b of waveform 703. The t_output of flip-flop 406 thereupon issue a logic 1 pulse 706a to unload the output register of the FIFO 410. When the data byte is transferred out of the output register, the OPR output of the FIFO 410 transitions to a logic zero as indicated at 707a of waveform 707. In response to the logic transition of the OPR output, the flip-flop 406 is reset as indicated at 706b.

As before described, the FIFO 411 is unloaded at the same time the FIFO 410 is unloaded. Thus, 30 when the OPR output of FIFO 410 transitions to a logic zero, the OPR output of FIFO 411 also transitions to a logic zero as indicated at 708a of waveform 708. When an additional dummy byte enters the output register of FIFO 411, the OPR output transitions to a logic 1 as indicated at 708b. In addition, the input register output IPR changes state as indicated at 709a. A bus cycle request on control line 419 thereby is initiated as indicated by logic one pulse 71 Oa. In response to pulse 71 Oa, the 35 bus logic unit 128 of Figure 5 issues a strobe pulse 713a to place the cycle request pulse 71 Oa onto the megabus 13 as indicated by pulse 711 a. Upon the occurrence of the strobe 713a and the pulse 711 a, a pulse 714a is carried by the megabus 13 to the main memory unit 12.

When the cycle request pulse 71 Oa is generated, the bus logic unit 128 places the MPDC 10 in a busy sta - te as indicated by the logic 1 pulse 712a. During the time period of the pulse 712a, the MPDC 40 issues a data request to the main memory unit 12 as indicated by pulse 714a and awaits a response.

If the memory unit 12 accepts the bus cycle request and the main memory address supplied by MPDC 10, the main memory unit issues a pulse 71 5a. In response thereto, the bus logic unit 128 of Figure 5 transitions the bus cycle request signal illustrated by waveform 711 to a logic zero level as indicated at 711 b. During a time period not exceeding that indicated by the logic 1 pulse 712a, the main memory unit retrieves the contents at the indicated main memory address and supplies the data to the megabus 13. In addition, the main memory unit issues a pulse 714b to notify the MPDC 10 that data at the indicated main memory address is forthcoming. In response thereto, the bus logic unit 128 issues a strobe 716a to place an acknowledgement pulse 71 5b on the megabus 13. Concurrently therewith, the bus logic unit removes the MPDC 10 from the busy state as indicated by the logic zero 50 level 712b of waveform 712.

The above-described process is repeated until the total number of data bytes indicated by the range count has been transferred from the main memory unit 12 to the device adapter 14.

During the data transfer process, the bus address counters 300, 302 and 303 are incremented and the range counters 306-309 are decremented. More particularly, the address counters are incremented twice as indicated by pulses 717a and 717b each time a data request is made to the main memory unit 12 as indicated by pulse 715a. Further, the range counters are decremented each time a data byte is requested by the MPDC 10 from the main memory unit 12. One decrement command as illustrated by pulse 71 Sa is issued when a request 71 Oa for a data word is issued. A second decrement 60 command as illustrated by pulse 718b is issued by the main memory unit 12.

Claims (4)

1. A peripheral device controller having architecture accommodating both the temporary storage of main memory address, range and offset range parameters used during data transfers between the main memory and a peripheral unit via an asynchronous bus and the dynamic amending of said i 25, 45' Ir GB 2 061 577 A 25 parameters during a data transfer, comprising a scratchpad memory unit, a hardware control means, a plurality of counters including a first counter arranged to receive an offset range count, a range count and memory address parameters from the scratchpad memory and to retain the memory address information therein, a second counter electrically connected to said first counter to form a serial data path from said first counter and responsive to said hardware control means for accommodating a serial 5 transfer, therethrough, of said offset range and range parameters from the first counter, said second counter retaining said range parameter having means indicating to said hardware control means the completion of a data transfer between said main memory and said peripheral unit, and a third counter electrically connected to said second counter in extension of said serial data path and responsive to the hardware control means for accommodating a serial shift of said offset range parameter from the second counter, said third counter having means for dynamically indicating the occurrence of a first data byte in an information stream to be transferred between said main memory and said peripheral unit.

said counters dynamically updating said parameters uPder the control of said hardware means during data transfers, and firmware control means responsive to the hardware control means between data transfers for circulating a serial stream of said parameters through the scratchpad memory unit and 15 respectively through the said counters in sequence, thereby storing control information in the scratchpad memory unit for re-initiating a data transfer in the event of a data transfer error.

2. A peripheral device controller according to Claim 1, comprising a clock means for autonomously supplying logic control signals, first logic means connected to said clock means and responsive to said logic control signals for providing address control signals to said first counter and second logic 20 means connected to said clock means and to the hardware control means and responsive to said logic control signals for providing range and offset range control_ signals.

3. A peripheral device controller 'according to Claim 1 or Claim 2 furtrier comprising a multiplex switch having a first input connected to receive memory addresses from said first counter, a second input connected to a register storing a memory channel number and an output coupled to a bus input, 25 said switch being operable to select either the first or the second input under control of signals from the hardware control unit and to transmit signals therefrom to the bus input.

4. A peripheral device controller according to any preceding claim for controlling asynchronous transfers of data between a main memory and a data storage disc device.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1981. Published by the Patent Office, 25 Southampton Buildings, London. WC2A JAY, from which copies may be obtained.