WO1988001079A3 - Traitement de signaux - Google Patents

Traitement de signaux Download PDF

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Publication number
WO1988001079A3
WO1988001079A3 PCT/GB1987/000559 GB8700559W WO8801079A3 WO 1988001079 A3 WO1988001079 A3 WO 1988001079A3 GB 8700559 W GB8700559 W GB 8700559W WO 8801079 A3 WO8801079 A3 WO 8801079A3
Authority
WO
WIPO (PCT)
Prior art keywords
conductor
output
input
recall
low
Prior art date
Application number
PCT/GB1987/000559
Other languages
English (en)
Other versions
WO1988001079A2 (fr
Inventor
Vernon G Dobson
Original Assignee
Vernon G Dobson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vernon G Dobson filed Critical Vernon G Dobson
Publication of WO1988001079A2 publication Critical patent/WO1988001079A2/fr
Publication of WO1988001079A3 publication Critical patent/WO1988001079A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
    • G06F7/5095—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators word-serial, i.e. with an accumulator-register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V30/00—Character recognition; Recognising digital ink; Document-oriented image-based pattern recognition
    • G06V30/10—Character recognition
    • G06V30/19—Recognition using electronic means
    • G06V30/192—Recognition using electronic means using simultaneous comparisons or correlations of the image signals with a plurality of references
    • G06V30/194—References adjustable by an adaptive method, e.g. learning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4804—Associative memory or processor

Abstract

Un circuit à réseau de traitement de signaux pouvant être utilisé, par exemple, comme filtre ou comme mémoire associative, comprend des éléments (101,102,103,104) ayant chacun un conducteur respectif d'entrée (85,86,87,88) et un conducteur respectif de sortie (81,82,83,84), une cellule d'instruction (T) et une cellule de rappel (R). Chaque conducteur d'entrée (85,86,87 ou 88) comprend une pluralité de cellules-mémoire (M) qui servent de dispositifs de couplage de signaux entre des conducteurs de sortie d'autres générateurs et le conducteur d'entrée. En phase d'instruction, des trajets traversant les cellules-mémoire (M) sont coupés chaque fois que le conducteur de sortie est fortement chargé et que le conducteur d'entrée est faiblement chargé. Chaque cellule d'instruction entraîne une baisse de la charge du conducteur d'entrée du générateur respectif si le conducteur de sortie est fortement chargé. En phase de rappel, les cellules de rappel (R) reçoivent des signaux de leur conducteur d'entrée en fonction du nombre de conducteurs de sortie qui y sont couplés via des cellules-mémoire (M). Si les signaux d'entrée reçus dépassent un certain seuil, la cellule de rappel (R) fait baisser la charge du conducteur de sortie, et vice-versa. Les signaux d'entrée sont additionnés et enregistrés dans les cellules de rappel (R), mais se dégradent avec le temps, de sorte qu'après un certain temps, une configuration fixe d'états fortement et faiblement chargés apparaît au niveau des conducteurs de sortie, cette configuration étant susceptible d'être détectée par un circuit détecteur (90) qui valide un tampon de sortie (89).
PCT/GB1987/000559 1986-08-08 1987-08-07 Traitement de signaux WO1988001079A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB868619452A GB8619452D0 (en) 1986-08-08 1986-08-08 Signal generating & processing
GB8619452 1986-08-08

Publications (2)

Publication Number Publication Date
WO1988001079A2 WO1988001079A2 (fr) 1988-02-11
WO1988001079A3 true WO1988001079A3 (fr) 1988-03-24

Family

ID=10602486

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1987/000559 WO1988001079A2 (fr) 1986-08-08 1987-08-07 Traitement de signaux

Country Status (4)

Country Link
US (1) US5072130A (fr)
JP (1) JPH02500392A (fr)
GB (1) GB8619452D0 (fr)
WO (1) WO1988001079A2 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990010977A1 (fr) * 1989-03-10 1990-09-20 Synaptics, Inc. Reseau et element synaptiques
JPH03209553A (ja) * 1990-01-11 1991-09-12 Mitsubishi Electric Corp 自己組織化機能を備えた神経回路網装置
IT1244911B (it) * 1991-01-31 1994-09-13 Texas Instruments Italia Spa Architettura per rete neuronica fisicamente inseribile nel processo di apprendimento.
JPH05251789A (ja) * 1992-03-06 1993-09-28 Ezel Inc ニューロデバイス
GB9205587D0 (en) * 1992-03-13 1992-04-29 Pilkington Micro Electronics Improved artificial digital neuron,neuron network and network algorithm
US5995954A (en) * 1992-03-18 1999-11-30 Loos; Hendricus G. Method and apparatus for associative memory
CA2135857A1 (fr) * 1994-01-03 1995-07-04 Shay-Ping Thomas Wang Reseau neuronal une fonction logarithmique et methode d'utilisation de cette fonction
WO1999033019A1 (fr) * 1997-12-19 1999-07-01 Bae Systems Plc Reseaux neuronaux et memoire neuronale
WO2000029970A1 (fr) * 1998-11-13 2000-05-25 Arizona Board Of Regents, A Body Corporate Acting On Behalf Of Arizona State University Ordinateur neuromimetique oscillatoire a connectivite dynamique
US6957204B1 (en) * 1998-11-13 2005-10-18 Arizona Board Of Regents Oscillatary neurocomputers with dynamic connectivity
US7280989B1 (en) 2000-01-28 2007-10-09 Arizona Board Of Regents Phase-locked loop oscillatory neurocomputer
US7174325B1 (en) * 2002-06-07 2007-02-06 George Mason Intellectual Properties, Inc. Neural processor
US20070280270A1 (en) * 2004-03-11 2007-12-06 Pauli Laine Autonomous Musical Output Using a Mutually Inhibited Neuronal Network
WO2018184570A1 (fr) * 2017-04-06 2018-10-11 上海寒武纪信息科技有限公司 Appareil et procédé de fonctionnement

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3496382A (en) * 1967-05-12 1970-02-17 Aerojet General Co Learning computer element
US3691400A (en) * 1967-12-13 1972-09-12 Ltv Aerospace Corp Unijunction transistor artificial neuron
US3950733A (en) * 1974-06-06 1976-04-13 Nestor Associates Information processing system
JPS58115864U (ja) * 1982-01-27 1983-08-08 三菱電機株式会社 車両用充電発電機
US4660166A (en) * 1985-01-22 1987-04-21 Bell Telephone Laboratories, Incorporated Electronic network for collective decision based on large number of connections between signals
US4731747A (en) * 1986-04-14 1988-03-15 American Telephone And Telegraph Company, At&T Bell Laboratories Highly parallel computation network with normalized speed of response
US4782460A (en) * 1987-04-06 1988-11-01 American Telephone And Telegraph Company, At&T Bell Laboratories Computing apparatus comprising a programmable resistor

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Biological Cybernetics, volume 24, no. 4, 30 November 1976, Springer-Verlag, G. Willwacher: "F{higkeiten eines assoziativen Speichersystems im Vergleich zu Gehirnfunktionen", pages 181-198 see figures 2-4; page 183, left-hand column, line 1 - page 184, paragraph 8 *
Kybernetik, volume 12, no. 2, February 1973, Springer-Verlag, K. Fukushima: "A model of associative memory inh the brain", pages 58-63 see figure 1; page 59 and page 60, paragraph 2 *
Proceedings of the 6th International Conference on Pattern Recognition, 1982, Munich, IEEE, (US), Y Hirai: "A learning network resolving multiple match in associative memory" see pages 1049-1052 *
Proceedings of the Chapel Hill Conference on VLSI, 1985, publ. 1986, Computer Science Press, M. Sivilotti et al.: "A novel associative memory implemented using collective computation", see pages 329-342 cited in the application *

Also Published As

Publication number Publication date
GB8619452D0 (en) 1986-12-17
US5072130A (en) 1991-12-10
JPH02500392A (ja) 1990-02-08
WO1988001079A2 (fr) 1988-02-11

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