WO1987006086A1 - Synchronisateur de blocs de donnees numeriques - Google Patents

Synchronisateur de blocs de donnees numeriques Download PDF

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Publication number
WO1987006086A1
WO1987006086A1 PCT/US1987/000729 US8700729W WO8706086A1 WO 1987006086 A1 WO1987006086 A1 WO 1987006086A1 US 8700729 W US8700729 W US 8700729W WO 8706086 A1 WO8706086 A1 WO 8706086A1
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WIPO (PCT)
Prior art keywords
candidate
sequence
symbol
symbols
predefined
Prior art date
Application number
PCT/US1987/000729
Other languages
English (en)
Inventor
Sohei Takemoto
Original Assignee
Ampex Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ampex Corporation filed Critical Ampex Corporation
Priority to JP62502405A priority Critical patent/JPH0691522B2/ja
Publication of WO1987006086A1 publication Critical patent/WO1987006086A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
    • G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
    • G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
    • G11B27/28—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording
    • G11B27/30—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording
    • G11B27/3027—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording used signal is digitally coded
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/12—Formatting, e.g. arrangement of data block or words on the record carriers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

Definitions

  • the present invention pertains generally to the synchronization of a digital data stream, and is more particularly directed to the accurate recovery of information in a data stream received from a transmission channel.
  • synchronization of the data in order to successfully recover the information transmitted in the data stream.
  • many systems have appended synchronization sequences to the beginning of respective information data blocks to facilitate this task. Recovery is achieved by recognizing a synchroni ⁇ zation sequence and identifying the end of the sequence. Once the synchronization data indicating the end of a sequence have been identified, the information data block is identified as those data which follow the sequence over a predetermined interval.
  • each of these synchronizing sequences is comprised of a set of predefined characters or symbols which occur in a time ordered sequence.
  • While the invention described herein is compatible with any stream digital data transmission system, it has specific utility in recording and reproducing data with magnetic tape record/reproduce devices.
  • the same tracks on the magnetic tape include video and audio data separately recorded at spaced locations along each track.
  • the video data account for as much as 90% of the data recorded on a track, and the audio data represent only a small part of the data on each track.
  • the synchronization sequence included in the audio data may be different and without the benefit of repetitiveness that is the case in synchronization sequences included in the video data.
  • An audio recovery system should be able to recover a synchronization sequence in one pass because there is no or only a few repetitions of the sequence for the audio data, and it should be reliable as it must detect a relatively short data.
  • such system should be able to discriminate between false synchronizing sequences which contain a partial string of synchronizing sequence symbols in the correct order, and actual synchronizing sequences which are in the correct order but have some symbol errors included therein. Because the magnetic recording and reproducing medium is likely to have been recorded previously, there is a possibility that partial false synchronization sequences (previously recorded sequences which have been overwritten and not completely erased) will be defected, and this possibility should be excluded by conclusively identifying the correct sequence for the presently recovered information, in spite of some of the sequence symbols being in error.
  • the invention provides a method and apparatus for reliably detecting the synchronizing sequence of a digital data stream.
  • a plurality of successive different synchronizing symbols in a predeter ⁇ mined sequence are introduced into a data stream for transmission therewith.
  • the synchronizing sequence occupies a predetermined interval upstream of a data block whose timing is to be synchronized.
  • the receiver At the receiver, symbols or characters corresponding to those forming the sequence are detected and identified in the received data stream to identify the transmitted synchronizing sequence.
  • the identified of the synchro ⁇ nizing sequence permits the generation of a. synchronizing pulse relative to the end of the identified sequence which marks the start of the downstream data block.
  • the method includes testing received symbols corresponding to those forming the synchronizing sequence by an arbitration technique to determine whether they are in time positions corresponding to the time positions for such symbols in the predetermined synchronizing sequence. The testing is accomplished by a comparison method wherein a series of candidate sequences of symbols is generated, and symbols in the received sequence are compared with symbols in the candidate sequence to determine the sequence most likely to correspond to the transmitted sequence.
  • the comparison technique includes generating symbols in the predetermined sequence, commencing with a chosen candidate symbol.
  • a comparison of the generated candidate sequence with the received sequence should provide a match for each symbol in each time position, if the candidate symbol is in the correct time position.
  • the first received symbol identified as a valid symbol is used as a first candidate and other candidates are produced by ambiguities developed in the matching procedure. There is an ambiguity where a received valid symbol does not match symbols at corresponding places in the test sequences of the previous candidates, or an invalid symbol, i.e., one not included in the predetermined sequence, is detected in the received sequence.
  • a match between a received symbol with the symbols of the candidate sequence is tallied for each matched candidate sequence.
  • the number of matches or votes tallied for each respective candidate sequence is then compared with the number for each of the other candidate sequences in a logic (arbitration) program to determine which candidate sequence is most likely to correspond to the predetermined sequence entered into the transmitted data stream. From the determined most likely candidate sequence, the end of the predetermined sequence is detected and a timing signal is generated to identify the start of the following block of information data.
  • this method is implemented in a seven trial, three candidate voting system wherein the synchronizing sequence includes a predetermined sequence of symbols representing count down sequence of numbers from 6 to 0.
  • the first symbol which is recognized as a symbol corresponding to one of those forming the predetermined sequence causes a control means to load a first counter with a number corresponding to that represented by the first symbol. Thereafter, the counter counts from the number represented by the first symbol at a rate corresponding to the rate of receipt of the symbols to generate a candidate sequence. Because of the ambiguity of being the first recognized symbol, all that is known is that the first symbol should be tested to determine if it is part of the transmitted predetermined sequence.
  • the candidate symbol Being a recognized symbol, it identifies a candidate symbol representing a particular location or time order in the predetermined sequence. If the candidate symbol in fact represents a sequence corresponding to the trans- itted predetermined sequence, the succeeding received symbols should correspond to the succeeding symbols in the candidate sequence. In such event, the first counter counts down to the final number in the sequence, in this case zero, at the same time a symbol representing the final number is received.
  • Each of successively received symbols is compared with the first candidate sequence and when a match does not occur, another counter is loaded by the control means with a number represented by the received symbol not matching the first candidate sequence. Each such counter also counts in the predetermined sequence in the same manner described with reference to the first counter. In a similar manner, the following received symbols are detected and matched with the candidate sequences and when a match does not occur a third counter is loaded by the control means and then counts to generate a third candidate sequence.
  • control means executes a logic program to determine which symbols cause loading or clearing of the candidate counters, and when. Further, the control means clears the associated counter when a new candidate is loaded into the counter. The control means chooses a candidate when a valid symbol is received and no match of that symbol to the symbols of the prior candidate sequences is made, providing a candidate counter is available.
  • the logic program also contains logic for controlling the contents of the candidate counters based on special conditions such as a candidate sequence reaching a final count symbol and a candidate being selected as the most likely to represent the candidate sequence.
  • the logic of the control means is advantageously implemented in a read only memory (ROM) wherein the input criteria (matches, valid data, candidate selection, final symbol generation, availability for counters, etc.) address the memory to output control signals to the candidate and vote counters from the contents of a memory location.
  • ROM read only memory
  • the three counters count down from the numbers represented by the received symbols, their contents are compared with the received symbols to determine if there is a match between each received symbol and the candidate sequences represented by the contents of the counters.
  • Each match is determined by a comparison circuit and tallied in separate vote counters, each associated with a candidate counter.
  • the outputs of the vote counters are transmitted to a decision logic circuit which determines on the basis of the tallied votes which of the sequences among the candidates is the most likely to correspond to the predetermined sequence included in the transmitted data, i.e., it elects a winner.
  • a candidate has been declared or elected a winner, its final sequence symbol is used as an indication that the end of the synchronizing sequence interval has occurred in the _ ? _
  • a synchronization timing pulse is generated relative to the occurrence of the final symbol to mark the initiation of the data block for the received information.
  • the decision logic circuit executes a logic program which first determines which candidate has the most votes from among the choices and elects a winner based on those criteria.
  • the logic program also contains logic for making decisions on selecting a candidate based on special conditions such as ties in the tallied votes, minimum passing votes, and landslide votes.
  • the logic of the decision logic circuit is advantageously imple- mented in a read only memory (ROM) wherein the input criteria (votes, etc.) address the memory to output the selection of a candidate from the contents of a memory location. This implementation provides a facile method for changing the selection standards of the candidates by reprogramming the ROM.
  • the preferred system disclosed is a seven-trial, three candidate system which arbitrates based on the number of votes for a maximum of three candidates which is the most likely candidate to represent a transmitted synchronizing seven symbol sequence.
  • the number of symbols in a sequence determines the maximum number of possible votes for a candidate, six in the example.
  • the number of trials and number of candidates chosen to implement a system are a function of the error rate of the transmission channel. While it is difficult to make an exact correlation between the number of trials and candidates needed for a particular error rate, statistical simulations of the system can be used with known error distributions for a transmission channel to arrive at an acceptable probability distribution of recovering the correct synchronizing sequence.
  • candidates and trials may be added until the error rate is less than an acceptable level or reaches the point of diminishing 5 returns.
  • the number of candidates to be tested is selected according to the probability of receiving false symbols. There is a tradeoff of whether to add more candidates or more trials as the former increases circuitry for the synchronization detection system
  • FIG. 1. is a system block diagram of a synchronization sequence detection system for transmitted 35. serial digital data which is constructed in accordance with the invention
  • FIG. 2 is a pictorial representation of a digital serial data stream format including an initial _ g _
  • FIG. 3 is a timing diagram for an embodiment of FIG. 1, wherein the synchronization detection circuit operates according to a five phase clock sequence illustrated in FIG. 9;
  • FIG. 4 is a detailed block diagram of synchroni ⁇ zation detection circuit illustrated in FIG. 1;
  • FIG. 5 is a logic diagram of the selection criteria algorithm executed by the voter decision logic of the synchronization detection circuit illustrated in FIG. 9;
  • FIG. 6 is a timing diagram illustrating candidate voting in a synchronization detection circuit according to the invention.
  • FIG. 7 is a timing diagram illustrating candidate voting for a landslide election in a synchroni ⁇ zation detection circuit according to the invention
  • FIG. 8 is a detailed flowchart of the logic algorithm executed by the control means illustrated in FIG. 9;
  • FIG. 9 is a detailed electrical schematic diagram of the synchronization detection circuit illustrated in FIG. 4;
  • FIG. 10 is a representation of the contents of the ROM for the voter decision logic illustrated in FIG. 9;
  • FIG. 11 is a representative table illustrating the functions controlled by the output of the ROM for the voter decision logic illustrated in FIG. 9;
  • FIG. 12 is a representation of the contents of the ROM for the control means illustrated in FIG. 9.
  • FIG. 13 is a representative table illustrating the functions controlled by the output of the ROM for the control means illustrated in FIG. 9. _ m
  • FIG. 1 illustrates in block diagram form an implementation of a synchronization detection system 6 for serial digital data which is constructed in accordance with the present invention.
  • the generalized format of such serial data is illustrated in FIG. 2, where the data includes alternate synchronization sequences 20 and information data blocks 24, with each synchronization sequence 20 being appended to a data block 24.
  • These data packets are asynchronously or synchronously transmitted over a transmission channel 8 to the synchronization detection system 6, and the system responds to the received synchronization sequence 20 to generate a block sync pulse 22 to indicate the initiation of the data block 24.
  • Circuitry or user devices downstream of the synchronization detection system 6 receive the data stream via a data path 18 and use the block sync signal 22 to synchronize the recovery of the information data in data block 24.
  • the synchronization sequence 20 and the information data block 24 can be comprised of any number of intermediate bit divisions, but for convenience and compatibility with other data systems, they are generally separated into conventional byte or nibble format.
  • the invention is applicable to any system which transmits serial digital data in the format shown in FIG. 2, the data format represented can be the audio portion of data as reproduced by a helical scan, magnetic tape record/reproduce apparatus.
  • Each synchronization sequence 20 included in the data stream comprises a plurality of sync units extending from a first unit 26 to a last unit 28.
  • a sync unit consists of a fixed bit pattern (FP) and a character or a symbol for example A in the unit 26.
  • the symbols differ throughout the sequence and are disposed in a predetermined order which has been selected for facile generation and recovery, for example, a countdown sequence 6, 5, 4, 3, 2, 1, 0.
  • the fixed bit pattern has a suitable number of bits forming a sync pattern that can be identified in a data stream to indicate the word boundaries among the symbols and locate the respective symbols of the synchronizing sequence.
  • the respective symbols. A, B, C, D, ... N of the sync units are arbitrary but are all different and form a set in a unique predetermined sequence which can be identified by their order.
  • the synchroniza ⁇ tion sequence by having a fixed bit pattern and symbols in a predetermined sequence, extends for a known interval. This assists in the recovery of the sequence with only a few valid symbols in the correct time order because once a valid sequence is known, the end of the sequence can be generated by timing circuitry. Also, if valid symbols are recovered early in the sequence, the subsequent part of the sequence may be in error and the detection still reliably made.
  • the respective symbols A, B, C, D, ... N are represented by a suitable digital code using a suitable number of bits.
  • the code is capable of checking the validity of the symbols because only symbols of the chosen set in the sequence are used. Because errors in a transmission channel can affect the reception of the sync data, this provides one check on the symbols to • determine whether or not a correct synchronization sequence is being recovered.
  • the data block 24 is identified in the synchronization detection system 6 by generating a block sync signal 22 indicating that the synchronizing sequence 20 has been validly detected and that the following or subsequent information is information data.
  • the format of the synchronization sequence in the format illustrated in FIG. 2 assists its successful recovery in a number of ways.
  • the fixed bit pattern (FP) is sufficient in length to indicate reliably that a symbol follows.
  • Each symbol A, B, C, D, ... N is predefined such that if a symbol is recovered which is not in the known set then the recovered synchronization data are known to be in error.
  • the symbols are in a predefined sequence such that if a valid symbol is identified and it can be reliably validated that it is in the correct time position in the sequence, then the rest of the sequence can be generated because of its known order and time interval. Further, the known time interval permits the recovery of the sequence even if the subsequent and final symbols in the received sequence are in error.
  • the subsequent symbols can be generated.
  • the length of the sequence can increase the probability that sequence can be reliably recovered. The more symbols in the sequence, the higher the probability that at least a few will be validly received after transmission.
  • the synchronization detection system 6 receives the serial data stream over the transmission channel 8 from a transmitter (not shown) .
  • the data stream is transmitted in the format shown in for FIG. 2 and is presented to a serial to parallel converter 12.
  • the serial to parallel converter 12 converts the serial data stream to parallel word form and outputs a serial stream of words on the data path 18 for the downstream utilization device. While the serial to parallel converter 12 could convert the bit serial data into any length of multi-bit word, in one embodiment of the invention, an 8-bit byte word format is used because such division will be more compatible with most utilization devices.
  • the synchronization units of the synchro ⁇ nizing sequence includes 36 bits of the FP data and 4 bits of symbol data, but could be other combinations of such.
  • each synchronization unit is 5 bytes in length, and' a total sequence is 35 bytes in • length for a 7 symbol sequence.
  • the timing signals necessary to detect the boundaries of the words to be converted are produced by a word sync detector 10 which detects the occurrence of each fixed bit pattern (FP) and byte boundaries in the data stream and generates respective timing signals via a conductor 11 to the serial to parallel converter 12.
  • the output on the data path 18 is not only the synchroni ⁇ zation units 26 ... 28 in serial word format but also the data block 24 in serial word format.
  • the word sync detector 10 generates symbol timing signals on a line 13 to a validity checker 14. These signals indicate the boundaries of the synchroni ⁇ zation symbols A, B, C, D ... N and provide a differen- tiation of the symbols from the data in the data block 24.
  • the symbol block timing signals on the line 13 permit the validity checker circuit 14 to extract the 4 bit symbols of the synchronization sequence from the word serial data stream on the data path 18.
  • the validity checker circuit 14 also strips the symbols of the extra bits of fixed pattern and verifies whether the symbols are part of the character set used in the transmitted sequence. The verification can be accom- pushed by a number of techniques. In the disclosed embodiment, the countdown sequence is from "6" to "0" and only three bits are needed to generate these symbols. The fourth bit is used as odd parity to verify a correct or valid symbol, and invalid symbols are converted to the unused character "7" by the validity checker 14.
  • the symbols of the received sequence are received from the validity checker 14 by a synchronization detection circuit 16 via line 15 to determine the end of the synchronization signal 20 and to generate the block synchronization signal 22 on a line 17 to the subsequent utilization circuitry.
  • the word sync timing signals applied on the line 11 from the word sync detector 10 to the synchronization detection circuit 16 are a series of timed pulses based on the timing of the bit-serial data received on the transmission line 8 by the word sync detector 10.
  • FIG. 3 shows the generation of timing signals CT11-CT15, and reset from the word sync detector 10.
  • a further validity signal CLll is generated by the validity checker 14 and applied to the synchronization detection circuit 16 over the line 15.
  • a sync sequence unit 26 is divided into five 8-bit bytes where the . fixed bit pattern (FP) is four-and-a-half bytes and the symbol A is a 4-bit half byte.
  • the control signals CT11-CT15 are generated on the five byte boundaries of each sync sequence unit by the word sync detector 10. These control timing signals form a five phase clock for moving data through the sync detection circuitry 16 in one sync unit time period.
  • the validity signal CLll is generated by the validity checker 14 subsequent to the CT11 signal, but prior to the CT15 timing signal.
  • the CLll signal indicates that the validity checker 14 has found an invalid symbol which should be disregarded.
  • the initialization signal reset, precedes the first timing signal CT11 for the first received symbol.
  • the circuit thereafter, performs the detection function until a block sync signal 22 is generated at one of the sync sequence unit times CT15 at the end of a detected sequence before being reset again.
  • FIGURE 4 illustrates a generalized detailed block diagram of the preferred implementation of the synchronization detection circuit 16. This circuit will now be more fully described to provide an overview of the method for detecting the synchronization sequence and generating the block sync signal 22.
  • the synchronization detection circuit 16 includes of a controller 36 which receives timing signals and a plurality of status indications to control the loading of a plurality of candidate sequence generators 32 and the clearing of associated vote tally circuits 34.
  • the controller 36 operates in a programmed sequence which is initiated with the receipt of the first valid symbol and, thereafter, steps through the program contained therein until an end of the synchroni ⁇ zing sequence is detected, or the controller is reset by a signal on a line 49 from a reset circuit 43.
  • the controller 36 determines from the outputs of a plurality of comparators 30 and a match circuit 45 whether or not to load a present symbol into one of the candidate sequence generators 32.
  • Each comparator 30 compares the output of a corresponding candidate sequence generator 32 with the received symbol sequence on line 15 to output a match signal if the two are equivalent.
  • the match circuit 45 generates a new candidate signal via line to the controller 36 if no match is found and the validity signal CLll indicates a valid symbol is present.
  • the controller 36 will load the present symbol into an available candidate sequence generator 32, if any.
  • the loading is controlled by signal lines 41 which determine which of the candidate sequence generators 32 are to be loaded with the present received symbol.
  • the lines 41 are also used to clear the vote tally circuit 34 associated with the loaded candidate sequences generator.
  • the controller 36 also receives signals from voter decision logic 38 over lines 47 and from the candidate sequence generators
  • the status signals on lines 39 indicate when the last symbol of a sequence has been reached in one of the candidate sequence generators 32, and the status signals on lines 47 indicate when one of the candidate sequences has been selected as the most likely to be the transmitted sequence.
  • the candidate sequence generators 32 are used to generate that part of the predetermined transmitted sequence which is subsequent to a respective candidate symbol.
  • the candidate sequence generators 32 therefore reproduce parts of the total transmitted sequence beginning with the particular candidate symbol loaded therein by controller 36 and ending with the last symbol in the predetermined sequence.
  • the output of the candidate sequence generators 32 will correspond exactly to the transmitted sequence in the predetermined synchronization pattern.
  • the controller 36 will load as many candidate symbols as there are ambiguities in the received symbol sequence and as there are available candidate sequence generators 32.
  • the number of candidate sequence generators is three, or a three candidate system.
  • An increase in the number of candidate sequence generators 32 will increase the _ 1 ? _
  • the outputs of the candidate sequence generators 32 are each input to the respective associated comparators 30.
  • the comparators 30 have as their other input the recovered symbol sequence from the line 15. A match between the incoming symbol sequence and a candidate sequence will produce the match signal or a vote for the candidate symbol which generated the match. These votes are tallied in respective vote tally circuit 34, and the tallies are transmitted to a voter decision logic circuit 38.
  • the voter decision logic circuit 38 is an arbitration circuit which decides on the basis of a logic algorithm and the tally outputs of the vote tally circuits 34 which candidate symbol, if any, to select as the most likely to represent the originally trans ⁇ mitted synchronization sequence.
  • a minimum vote total is used to select a preliminary winner and if no other candidate symbol has received more votes by the time that a preliminary winner sequence reaches its final 5 symbol, then that candidate is selected to generate the block sync signal 22.
  • Detection of a final symbol is achieved by a final character detector 40 to which the output of the selected sequence generator 32 is gated. Upon detection of the final symbol of the selected
  • the final character detector circuit 40 will output the block sync signal 22.
  • FIG. 5 illustrates the preferred logic algorithm executed by the voter decision logic 38.
  • V 15 is the number of votes tallied for the first candidate
  • V2 is the number of votes tallied for the second candidate
  • V3 is the number of votes tallied for the third candidate, as taken from the output of the vote tally circuits 34.
  • the logic indicates which
  • 20 candidate should be chosen or selected based upon the tally of the votes for the respective candidates.
  • the selection of a candidate is based on a candidate sequence obtaining either a greater number of votes or at least an equal number of votes relative to
  • the passing vote count is the minimum number of votes that a candidate must accumulate before being selected. Further, there may be another criteria where, if a candidate tallies a
  • the landslide count is a number of votes that assures to a known probability that the candidate sequence is the trans ⁇ mitted sequence. For example, a number that is greater
  • the landslide vote count would be _ ⁇ g _
  • a landslide number for example, a number as well.
  • VI is less than, equal to, or greater than V2
  • VI is also compared with V3 to determine whether it is greater than, equal to, or less than V3.
  • the second candidate having eliminated, this part of the logic determines whether the first and the third candidate will be selected based upon obtaining the greater number of votes.
  • the first candidate is selected over the third candidate. The first candidate is selected because the later candidate remains a candidate for selection against still later candidates and will supplant the earlier as a selected candidate.
  • VI V2
  • VI is again compared with V3 to determine whether it is greater than, equal to, or less than V3.
  • Ties are then settled by selecting the first candidate over later candidates. If V3 is greater than VI for this condition, the third candidate is selected. Similarly, for the condition where VI is less than V2, V2 is compared to V3 to determine whether it is greater than, equal to, or less than V3. As was the case previously, the determination will either select the second candidate or the third candidate, depending upon which is greater, or in the case of a tie, the second candidate will be chosen over the third candidate. The cases for a tie are decided in a somewhat arbitrary manner but it is believed selecting the previous counter will increase the probability of detecting the correct sequence.
  • FIG. 6 is a timing diagram illustrating a seven-trial, three-candidate, two-vote system.
  • the sequence of symbols in the synchronization sequence will be the numerical symbols 0-6 and the sequence will be in the reverse numerical order, 6-5-4-3-2-1-0. The choice of these symbols and the sequence is to permit a particularly facile implementation of the above-discussed method.
  • Line A of FIG. 4 illustrates the original sequence of transmitted symbols.
  • a synchronizing sequence of 4, 6, 4, E, 2, 1, 3 is recovered from a serial data stream of the transmission channel 8 and is applied to the synchronization detection circuit 16 as a plurality of symbols and timing signals.
  • This reproduced sequence is illustrated on line B of FIG. 6.
  • the symbol E indicates a character which has been recovered that is not within the symbol set; that is, it is known to be in error.
  • Line C of FIG. 6 illustrates the contents of a first candidate sequence generator 32.
  • the contents of the vote tally circuit associated with the first candidate sequence counter is illustrated immediately below the counter contents on line D.
  • the contents of second and third candidate sequence generators 32 are then started, and the contents of their associated vote tally circuits are illustrated on lines F and H.
  • the first, second, and third candidate sequence generators what is meant is the order in which a sequence generator is loaded with a candidate symbol. Because there are a number of different algorithms for loading the candidate sequence generators any candidate sequence generator 32 could be the first, second, or third candidate sequence generator.
  • the first candidate sequence generator When the initial received symbol "4" is entered in the first candidate sequence counter, it initializes a candidate sequence generation operation which follows the predetermined sequence. Therefore, the first candidate sequence generator counts starting with the symbol "4" and finishes the subsequent portion of the original predetermined sequence in order "3-2-1-0" in correspondence with that sequence. The respective comparator for this candidate symbol compares each new incoming symbol of the reproduced sequence with those generated sequence symbols. It can be seen at line C of FIG. 6 that, because none of the recovered symbols match corresponding symbols generated by the first candidate sequence generated, the associated tally circuit will not register any votes for this candidate. When the first sequence generation circuit generates 5 the final symbol "0" and no candidate has been selected, this candidate is then withdrawn by clearing the generator such that it becomes accessible for use with another subsequent candidate.
  • the second candidate sequence generator 15 the second candidate sequence generator.
  • the symbols from the second candidate sequence generator are compared to the corresponding symbols subsequently recovered from the input sequence in timed order, and votes tallied for any matches.
  • FIG. 7 is an example of a similar seven-trial, three-candidate, two-vote system with a landslide criterion of four votes.
  • Lines A, B illustrate the transmitted and received sequences, respectively.
  • Lines C, D illustrate the contents of the first candidate counter and its associated tally circuit, respectively.
  • Lines E, F illustrate the contents of the second candidate counter and its associated tally circuit, respectively.
  • the first received symbol "4" is loaded in the first candidate counter and compared with the received sequence. Because there are no matches, the vote tally circuit accrues no votes for the candidate symbol.
  • the second symbol "5" presenting an ambiguity or no match for the first candidate sequence becomes a second candidate and is loaded into the second candidate counter.
  • the subsequent received sequence matches the second generated candidate sequence and, thus, votes continue to accrue for this candidate. No other candidates are selected because there are no further ambiguities in the input sequence.
  • a landslide number of votes (four) have accrued for the second candidate, it is selected as the most likely candidate, and its last symbol is used to generate the block sync signal 22. It should be noted that by definition the second candidate has passed the minimum passing vote 87/00729
  • the landslide condition is declared and the candidate sequence selection is terminated when the selected candidate sequence reaches the final symbol.
  • FIG. 9 is a detailed circuit schematic of an implementation of the synchronization detection circuit 16 included in a preferred embodiment of the invention.
  • Each of the candidate sequence generators 32 is imple ⁇ mented by a four bit binary candidate counter 102, 108 0 and 112, respectively. This allows a symbol sequence to be generated easily by clocking a counter with a signal which is synchronous to the input symbol sequence.
  • the counters 102, l ⁇ and 112 count synchronously with the clock signal CT12 which is generated in synchronism
  • the input symbol sequence on line 15 is input to a clocked latch 100 which receives the symbol sequence as three parallel bits at the word sync timing rate.
  • the symbols are clocked into the latch 100 by
  • the latch 100 has its output inverted in an inverter 101 and thereafter inputs the symbols to the preset inputs A-C of the candidate counters 102, 108 and 112. Bscause of the inversion of the symbols, the counters 102, 108, and 112 actually
  • a carry signal indicating the last symbol of a candidate sequence is generated by the carry output CR of each counter when it overflows after a count of 15. The carry signal further disables the
  • the received symbols on line 15 are further input to the A inputs of comparators 120, 122 and 124.
  • the comparators 120, 122 and 124 are asynchronous and ⁇
  • the clocking signal CT13 is generated to the CLK input of the counters 126, 128 and 130 to allow an incrementation of their count when the inputs are enabled from the comparators 120, 122 and 124 respectively.
  • the voter decision logic 38 comprises a ROM 132 and a latch 134.
  • the ROM 132 receives the vote total from each vote counters as an address and processes the votes by the outputting of the contents of the location addressed to implement the programmed logic described previously with reference to FIG. 5.
  • the ROM 132 is a 512 x 4 bit device and its contents are illustrated in FIG. 10. Upon the application of the nine bit address
  • the ROM 132 outputs a 4 bit control word depending upon that address.
  • the control word is clocked into the latch 134 in synchronism with the timing signal CT14.
  • These 4 bits become three candidate signals to a multiplexer of the final character detector 40 and a landslide indication signal to the reset circuit 43.
  • Each candidate selection signal enables a respective inverting buffer 114, 116 and 118 forming the multiplexer to pass the symbols of a selected candidate sequence through it and into a latch 140.
  • the selected sequence symbol which is latched into latch the 140 enters the device in synchronism with the timing signal CT15 applied to the CLK input of the device.
  • the control selection outputs of the latch 134 and their functional operations are more fully illustrated in the table shown in FIG. 11.
  • the final character will be generated and detected by a NOR gate 142 decoding a "0 M . Decoding this symbol or number will cause the output of gate 142 to enable gate 144 and pass the clock pulse signal CT15 which becomes the block sync signal 22.
  • the controller 36 is comprised of a ROM 136 and a clocked latch 138.
  • the ROM has address inputs A0-A9 (1028) and a 4 bit output.
  • the program contained within the ROM 136 is more fully illustrated in FIG. 12, which illustrates the contents of the 1028 x 4 bit memory space.
  • One of the input parameters to the address inputs of the ROM 136 are the three candidate selection lines 47 from the latch 134. These lines indicate which of the candidates, if any, has been selected.
  • Three other inputs to the A0-A9 inputs of the ROM 136 are from the carry outputs CR of the counters 102, 108 and 112.
  • the carry output signals are a status indication that a counter has reached the last symbol "0" in the predetermined sequence and, thus, has overflowed and generated a carry signal.
  • an input is made to the ROM 136 from the three candidate loading lines 41 which are the output of a latch 138. These lines indicate the status of the output of ROM 136 one symbol time earlier.
  • the last input to the ROM 136 is from the match circuit 45 which detects the lack of any match by a NOR gate 150 and provides this signal to the A3 input of the ROM 136.
  • This no-match signal is gated through an AND gate 152 provided the validity signal CLll is at a high level.
  • the validity signal CLll is generated from the validity checker 14 (FIG. 1) to indicate that the no-match signal has occurred in response to a valid symbol. If the validity checker 14 finds an invalid symbol, then the validity signal CLll pulled low to _ _
  • the ROM 136 receives these ten inputs and produces 3 bits of output from the addressed location (the fourth bit is not used) .
  • the 3 bits of output from the ROM 136 are clocked into the latch 138 in synchronism with the timing signal CT15 and become the signals which load the symbols from the input symbol sequence into the counters 102, 108 and 112. Further, they clear the associated vote counters 126, 128 and 130 simultaneously with the loading of a symbol.
  • the program commences at block A10 by setting the outputs 01, 02 and 03 of the ROM 136 to zero and then executing a series of tests to determine if the sequence generators, namely, candidate counters 102, 108 and 112 are occupied in generating generated candidate sequences, whether the candidate sequences have reached their final counts, and which, if any, candidate counter is available to commence generation of a new candidate sequence.
  • a logic state of one at the inputs to ROM 136 signifies a candidate counter has previously commenced such generation.
  • the program branches to a second test to determine whether the previously generated candidate sequence has reached its final count.
  • each of the three tests at blocks A12, A14 and A16 is branched to one of the three tests in blocks A18, A20 and A22, respectively.
  • Each branch involves the execution of a series of similar program steps, with each of the series performed in respect to one of the candidate counters. _.
  • block A18 tests the input 17 to ROM 136 to determine if the candidate sequence has reached its final count. If the test is
  • the candidate counter is prepared to commence generation of a candidate sequence in response to a subsequently received valid txymbol in the received data.
  • the program then returns to block A14 to execute
  • the program continues at block A14 to test whether a second of the three candidate centers is occupied in the generation of a candidate sequence. If
  • the program branches to test at block A20 whether the sequence being generated by the counter has reached its final count. Such final count is significant by a logic one at input 16 to the ROM 136. In the manner previously
  • this test determines the manner in which the corresponding counter is prepared for operation in response to a subsequently received valid symbol. If the candidate counter is to continue generation of its candidate sequence, the
  • 35 program branches to block A26 and a logic one to be placed at output 02 of the ROM 136. In any event, the program continues to execute the functions of the block A16, A22 and A28 to determine whether the third candidate counter is occupied in the generation of a candidate sequence and, if so, to determine whether the candidate sequence has reached its final count and prepare the counter for response to subsequently receive valid symbols.
  • the program continues to determine whether a new count sequence should be commenced with such symbol. This is determined by the test performed at block A30. If the input II to ROM 136 is a logic zero the test will signify that a new candidate sequence is not to be commenced and the program continues to block A32 and terminates. However, if a logic one is present at input II to ROM 136, the test will signify that a new candidate sequence is to be commenced. Whether or not such sequence can be commenced depends on availability of candidate counter. To determine this, the program branches to execute a sequence of tests at block A34, A36 and A38.
  • Each of these tests determines whether or not a corresponding candidate ' counter is occupied in generating a candidate sequence. If inputs 17 and 110 to ROM 136 are both zero, this signifies that the corresponding counter is not occupied in generating a candidate sequence. Similarly, if inputs 16 and 19 and inputs 15 and 18 of the ROM 136 are logic zero, the respective corresponding counters are also not occupied in generating candidate sequences. The program proceeds to select the first candidate counter found not to be so occupied.
  • Each of the tests at block A34, A36 and A38 define a respective branch to one of the blocks A40, A42 or A44.
  • Each of these blocks represents the execution of a program step that conditions one of the outputs 01, 02, or 03 of ROM 136 to enable the corres ⁇ ponding candidate counter to commence a new candidate sequence in response to a received valid symbol.
  • This conditioning is effected by setting the appropriate output of ROM 136 to logic 1.
  • the reset circuit 43 acts to reset the 5 controller 36 by clearing the latch 138. This action clears all the candidate counters 102, 108 , and 112 and vote counters 126, 128, and 130. This signal further resets the ROM 136 back to its initial program starting address. The reset signal to the latch 138 is generated
  • NAND gate 146 or the intialization signal reset through the AND gate 148, which acts as a negative true OR gate.
  • the reset signal is from the word sync detector 10 (FIG. 1) and is generated to begin the cycle of
  • the output of gate 144 which generates the block sync signal 22 is normally at low logic level and produces a high level pulse at the time of the decoding of the last symbol "0" at the time of the clock signal CT15. If the
  • the block sync signal when it makes a transition to a high level will produce a pulse from the NAND gate 146 similar to the reset signal to clear the latch 138.
  • a block sync signal 22 is generated for every candidate sequence which reaches its last symbol with at least one vote

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)

Abstract

Procédé et appareil de détection de séquences de synchronisation dans un flot de données numériques. L'appareil comprend une pluralité de compteurs de séquences de candidats (102, 108, 112) et des compteurs de votes associés (126, 128, 130) qui sont utilisés conjointement à des comparateurs (120, 122, 124) pour tester l'ordre de symboles de synchronisation reçus d'une séquence prédéfinie de symboles prédéfinis par rapport à une pluralité de symboles de candidats correspondants de séquences de candidats. Un compteur de candidats commence une nouvelle séquence de candidtats lorsqu'une ambiguïté dans la séquence de symboles d'entrée se produit. L'appareil comprend un circuit logique de décision de votant (38) qui sélectionne un gagnant parmi les candidats en se basant sur le nombre de votes ou de concordances pointés pour chaque séquence de candidats. En outre l'appareil détecte les ambiguïtés dans le flot de symboles d'entrée et charge les compteurs de candidats avec des symboles de candidats pour commencer de nouvelles séquences de candidats.
PCT/US1987/000729 1986-03-28 1987-03-27 Synchronisateur de blocs de donnees numeriques WO1987006086A1 (fr)

Priority Applications (1)

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JP62502405A JPH0691522B2 (ja) 1986-03-28 1987-03-27 同期信号発生装置及び方法

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US84559786A 1986-03-28 1986-03-28
US845,597 1986-03-28

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WO (1) WO1987006086A1 (fr)

Cited By (8)

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Publication number Priority date Publication date Assignee Title
EP0486919A2 (fr) * 1990-11-19 1992-05-27 ANT Nachrichtentechnik GmbH Méthode et dispositif de synchronisation en blocs de données codées avec redondance
EP0630017A2 (fr) * 1993-06-14 1994-12-21 International Business Machines Corporation Détection et validation de blocs formatés sur bande magnétique
US5502749A (en) * 1993-03-30 1996-03-26 Sony Corporation Radio receiver apparatus and phase correcting method thereof
US5815514A (en) * 1996-02-09 1998-09-29 Overland Data, Inc. Variable rate bit inserter for digital data storage
US6167550A (en) * 1996-02-09 2000-12-26 Overland Data, Inc. Write format for digital data storage
US6363512B2 (en) 1996-02-09 2002-03-26 Overland Data, Inc. Digital data recording channel
US6543024B2 (en) 1996-02-09 2003-04-01 Overland Storage, Inc. Write format for digital data storage
US6597526B1 (en) 1998-08-14 2003-07-22 Overland Storage, Inc. Magnetic tape drive apparatus including a variable rate encoder

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US4112498A (en) * 1976-02-24 1978-09-05 Siemens Aktiengesellschaft Digital correlation receiver
US4214124A (en) * 1977-09-29 1980-07-22 De Staat Der Nederlanden, Te Dezen Vertegenwoordigd Door De Directeur-Generaal Der Posterijen, Telegrafie En Telefonie Method and device for extracting a synchronizing signal from an incoming PCM signal

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DE3225365A1 (de) * 1982-07-07 1984-01-12 Robert Bosch Gmbh, 7000 Stuttgart Verfahren zur wandlung serieller datensignale

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Publication number Priority date Publication date Assignee Title
US4112498A (en) * 1976-02-24 1978-09-05 Siemens Aktiengesellschaft Digital correlation receiver
US4214124A (en) * 1977-09-29 1980-07-22 De Staat Der Nederlanden, Te Dezen Vertegenwoordigd Door De Directeur-Generaal Der Posterijen, Telegrafie En Telefonie Method and device for extracting a synchronizing signal from an incoming PCM signal

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0486919A2 (fr) * 1990-11-19 1992-05-27 ANT Nachrichtentechnik GmbH Méthode et dispositif de synchronisation en blocs de données codées avec redondance
EP0486919A3 (en) * 1990-11-19 1993-03-03 Ant Nachrichtentechnik Gmbh Method and circuit for block synchronisation of redundantly encoded data
US5502749A (en) * 1993-03-30 1996-03-26 Sony Corporation Radio receiver apparatus and phase correcting method thereof
EP0630017A2 (fr) * 1993-06-14 1994-12-21 International Business Machines Corporation Détection et validation de blocs formatés sur bande magnétique
EP0630017A3 (fr) * 1993-06-14 1996-10-16 Ibm Détection et validation de blocs formatés sur bande magnétique.
US5815514A (en) * 1996-02-09 1998-09-29 Overland Data, Inc. Variable rate bit inserter for digital data storage
US6167550A (en) * 1996-02-09 2000-12-26 Overland Data, Inc. Write format for digital data storage
US6363512B2 (en) 1996-02-09 2002-03-26 Overland Data, Inc. Digital data recording channel
US6513139B2 (en) 1996-02-09 2003-01-28 Overland Storage, Inc. Digital data recording channel
US6543024B2 (en) 1996-02-09 2003-04-01 Overland Storage, Inc. Write format for digital data storage
US6597526B1 (en) 1998-08-14 2003-07-22 Overland Storage, Inc. Magnetic tape drive apparatus including a variable rate encoder

Also Published As

Publication number Publication date
JPS63502949A (ja) 1988-10-27
JPH0691522B2 (ja) 1994-11-14

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