Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/22—Microcontrol or microprogram arrangements
  • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
  • G06F9/262—Arrangements for next microinstruction selection
  • G06F9/264—Microinstruction selection based on results of processing
  • G06F9/267—Microinstruction selection based on results of processing by instruction selection on output of storage

Definitions

• the present invention relates to microprogram con ⁇ trollers including a memory to store instructions at speci- fied addresses, a register to hold a current instruction and an arithmetic logic unit (ALU) : the ALU executing the current instruction and thereby manipulating external data as well as altering the choice of the following instruction and accessing the corresponding address in the memory.
• ALU arithmetic logic unit
• This device comprises a memory containing coded instructions, and a register, connected in loop arrangement. The simplest arrangement is shown in Fig. 1.
• the register R holds the current micro ⁇ instruction, which is presented to an Arithmetic/Logic Unit (ALU), that executes the instruction, manipulating external data as required.
• An additional field in the micro- instruction represents the memory address of the next instruction to be executed.
• this "next address” can be modified by the ALU outputs, providing a "conditional jump” feature.
• Further prior art systems known to applicant are disclosed in Australian patent specification nos. 535105 and 538215 in the name of Control Data Corporation. The disclosures therein require the use of separate address registers and support circuitry, buses and the like for each memory bank.
• a microprogram controller including a memory to store instructions at specified addresses, a register to hold a current instruc- tion including the address in the memory of the following instruction an arithmetic logic unit to execute the current instruction and thereby manipulating external data as well as altering the choice of following instruction; the improvement comprising dividing the memory into two banks and presenting the output of each memory, each said output being a possible following instruction,, to a first multiplexer which is connected to the register, and providing a second multiplexer to simultaneously with the execution of the current instruction receive as input any number of various conditions (including "1" and "0") one at a time, developed by the arithmetic logic unit and to develop a binary output to determine which of the following instructions at the
• Figure 3 shows a block diagram of a micropro- grammer made in accordance with the invention.
• FIG. 4 is a block diagram of a modified micro ⁇ program controller made in accordance with the invention.
• the circular dashed arrow in Fig. 1 indicates the time sequence of the various operations. The total delay around this path limits the maximum speed of the machine. Since the delays in memory and the ALU represent by far the largest component of this delay, and in practical systems are often approximately equal, the scheme of Fig. 2 may be used to double the speed of the machine, by allowing these functions to proceed in parallel (see the two arrows in Fig. 2).
• the current instruction and the address of its successor are held in the two registers Rl and R2. Simultaneously, the memory presents the following instruction at the input of Rl, while the address of its successor (i.e.
• Fig. 3 The scheme according to the invention is shown in greater detail in Fig. 3.
• the memory is here split into two banks (A and B), each of half of the original size (the total size will be dictated by program requirements), and register R2 of Fig. 2 is replaced by the multiplexer Ml, which can present the output of either memory bank to the register R.
• the two paralleled paths are as before, denoted by circular dashed arrows.
• the current instruction is output from R, and the
• ALU commences to calculate the desired results.
• Various con ⁇ ditions of possible interest (zero, negative, etc.) are offered as inputs to the secondary multiplexer M2, together with the constant values 0 and 1.
• M2 selects one of these inputs, as specified by the instruction, and develops the binary output "SWITCH".
• the address field of the current instruction has accessed both memory banks simultaneously, yielding two possible successor instructions. Note that the slow processes, i.e ALU function and memory access, proceed simultaneously.
• the signal "SWITCH”, acting on multiplexer Ml determines which of the two possible successor instructions is actually loaded into R, and next executed.
• the current instruction has modified its immediate successor, and simple programming methods may be used (as in Fig. 1).
• a one-instruction "loop" is developed by coding the instruction's successor address to point to itself. As long as the looping condition obtains, the instruction (in one bank of memory) is repeatedly executed, when the condition fails, the alternative instruction is executed instead and the program proceeds.
• Normal instructions i.e. those with no condi ⁇ tional effects, merely direct M2 to select one of the literal inputs 0 and 1, so explicitly directing the flow of control into Bank A or B as required.
• Multi-way Branches Modification A limited ability to perform multi-way branches, based on values computed by the ALU, is frequently desirable. Such a feature can readily be added to the architecture of Fig. 3, yielding that of Fig. 4, by parti ⁇ tioning the multiplexer Ml, into two sections, handling the current instruction and next address fields respectively.
• the current instruction field .operates as described above, ' as does most of the next address field.
• a portion of -the address field is provided with an additional input channel ("BRANCH" in Fig. 4) supplied from a register previously loaded by the ALU.
• BRANCH additional input channel
• Literal Outputs Modification Another infrequently used, but nonetheless valuable feature is the ability for the microprogram to supply literal values to the ALU at certain times. This feature may be obtained by addition of the LITERAL register (Fig. 4). On every machine cycle, the current value in one memory bank (in this example memory Bank B) may be loaded into this register, which can be read by the ALU when required. This implies that instructions to load meaningful data into the literal register must themselves reside in Bank A, since the corresponding Bank B location contains literal data, not an instruction. Since no penalty attaches to branching from one bank to another, this is not a problem. Once loaded, the value in the literal register is simply another ALU input, to be accessed when required.

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• Engineering & Computer Science (AREA)
• Software Systems (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Executing Machine-Instructions (AREA)
• Debugging And Monitoring (AREA)
• Advance Control (AREA)

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Cited By (5)

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• 1986
  • 1986-02-19 AU AU54599/86A patent/AU582424B2/en not_active Ceased
  • 1986-02-19 WO PCT/AU1986/000041 patent/WO1986005015A1/en not_active Application Discontinuation
  • 1986-02-19 JP JP61501315A patent/JPS62501940A/ja active Pending
  • 1986-02-19 EP EP19860901305 patent/EP0215028A4/en not_active Withdrawn

Patent Citations (4)

Non-Patent Citations (1)

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