EP0215028A4

EP0215028A4 - Microprogram controller.

Info

Publication number: EP0215028A4
Application number: EP19860901305
Authority: EP
Inventors: David R Brooks; Daniel S O'sullivan
Original assignee: Magellan Corp Australia Pty Ltd
Current assignee: Magellan Corp Australia Pty Ltd
Priority date: 1985-02-20
Filing date: 1986-02-19
Publication date: 1987-07-23
Also published as: JPS62501940A; AU582424B2; AU5459986A; EP0215028A1; WO1986005015A1

Abstract

A microprogram controller having a memory to store instructions at specified addresses, a register (R) to hold a current instruction including the address in the memory of the following instruction, an arithmetic logic unit (ALU) to execute the current instruction and thereby manipulating external data as well as altering the choice of following instruction wherein the memory is divided into two banks (A, B) and the output (each said output being a possible following instruction) of each memory bank is presented to a first multiplexer (M1) which is connected to the register (R), and providing a second multiplexer (M2) to simultaneously with the execution of the current instruction receive as input any number of various conditions (including ''1'' and ''0'') one at a time, developed by the arithmetic logic unit (ALU) and to develop a binary output to determine which of the following instructions at the first multiplexer (M1) is loaded into the register (R) to be next executed. The majority of conditional jump functions are, in fact, two-way decisions, i.e. IF (something) THEN DO (this) OTHERWISE DO (that). The new architecture is designed to optimise this type of decision. A LITERAL register is added to enable the microprogram to supply literal values to the arithmetic logic unit (ALU) at certain times.

Description

MICROPROGRAM CONTROLLER

The present invention relates to microprogram con¬ trollers including a memory to store instructions at speci- fied addresses, a register to hold a current instruction and an arithmetic logic unit (ALU) : the ALU executing the current instruction and thereby manipulating external data as well as altering the choice of the following instruction and accessing the corresponding address in the memory. In prior art controllers known to applicants electronic digital computing devices (in the general case, finite state automata) are generally controlled by a "microprogram -sequencer". This device comprises a memory containing coded instructions, and a register, connected in loop arrangement. The simplest arrangement is shown in Fig. 1. Here the register R holds the current micro¬ instruction, which is presented to an Arithmetic/Logic Unit (ALU), that executes the instruction, manipulating external data as required. An additional field in the micro- instruction represents the memory address of the next instruction to be executed.

In practical systems, this "next address" can be modified by the ALU outputs, providing a "conditional jump" feature. Further prior art systems known to applicant are disclosed in Australian patent specification nos. 535105 and 538215 in the name of Control Data Corporation. The disclosures therein require the use of separate address registers and support circuitry, buses and the like for each memory bank.

It is a principal objective of the present invention to provide a microprogram controller having enhanced features allowing computed jumps and/or sub¬ routines thus providing ease of programming of a single path machine combined with the speed of pipeline architec¬ tures. With this objective in view there is provided according to the present invention, a microprogram controller including a memory to store instructions at specified addresses, a register to hold a current instruc- tion including the address in the memory of the following instruction an arithmetic logic unit to execute the current instruction and thereby manipulating external data as well as altering the choice of following instruction; the improvement comprising dividing the memory into two banks and presenting the output of each memory, each said output being a possible following instruction,, to a first multiplexer which is connected to the register, and providing a second multiplexer to simultaneously with the execution of the current instruction receive as input any number of various conditions (including "1" and "0") one at a time, developed by the arithmetic logic unit and to develop a binary output to determine which of the following instructions at the first multiplexer is loaded into the register to be next executed. To this end, it is recognised that the vast majority of conditional jump functions are, in fact, two- -way decisions, i.e. IF (something) THEN DO (this) OTHERWISE DO (that). The new architecture is designed to optimise this type of decision. Further reference to the prior art systems and the invention will be made having reference to the accompanying diagrams, in which Figures 1 and 2 shown block diagrams of known microprogram sequencer.

Figure 3 shows a block diagram of a micropro- grammer made in accordance with the invention.

Figure 4 is a block diagram of a modified micro¬ program controller made in accordance with the invention. With reference to Figures 1 and 2, the circular dashed arrow in Fig. 1 indicates the time sequence of the various operations. The total delay around this path limits the maximum speed of the machine. Since the delays in memory and the ALU represent by far the largest component of this delay, and in practical systems are often approximately equal, the scheme of Fig. 2 may be used to double the speed of the machine, by allowing these functions to proceed in parallel (see the two arrows in Fig. 2). In Fig. 2, the current instruction and the address of its successor are held in the two registers Rl and R2. Simultaneously, the memory presents the following instruction at the input of Rl, while the address of its successor (i.e. the next-but-one) is presented at R2 by the ALU. Both registers update simultaneously on the system clock. This scheme, known as "pipelining", is widely used. The disadvantage of pipelined systems is inherent in the current/next use of the two registers. An instruc¬ tion that wishes to affect the flow of control (i.e. a jump) cannot affect its successor, whose address is already latched as the conditional jump is executed. It can only affect its successor-but-one. This leads to considerable inconvenience in programming. It also imposes a constraint that the shortest possible program "loop", comprises at least two instructions, even if one were sufficient (in the given ALU structure) to perform all required functions.

The scheme according to the invention is shown in greater detail in Fig. 3. The memory is here split into two banks (A and B), each of half of the original size (the total size will be dictated by program requirements), and register R2 of Fig. 2 is replaced by the multiplexer Ml, which can present the output of either memory bank to the register R. The two paralleled paths are as before, denoted by circular dashed arrows. The current instruction is output from R, and the

ALU commences to calculate the desired results. Various con¬ ditions of possible interest (zero, negative, etc.) are offered as inputs to the secondary multiplexer M2, together with the constant values 0 and 1. M2 selects one of these inputs, as specified by the instruction, and develops the binary output "SWITCH". Meanwhile, the address field of the current instruction has accessed both memory banks simultaneously, yielding two possible successor instructions. Note that the slow processes, i.e ALU function and memory access, proceed simultaneously. Finally, the signal "SWITCH", acting on multiplexer Ml, determines which of the two possible successor instructions is actually loaded into R, and next executed. Hence the current instruction has modified its immediate successor, and simple programming methods may be used (as in Fig. 1). A one-instruction "loop" is developed by coding the instruction's successor address to point to itself. As long as the looping condition obtains, the instruction (in one bank of memory) is repeatedly executed, when the condition fails, the alternative instruction is executed instead and the program proceeds.

Normal instructions, i.e. those with no condi¬ tional effects, merely direct M2 to select one of the literal inputs 0 and 1, so explicitly directing the flow of control into Bank A or B as required.

Multi-way Branches Modification A limited ability to perform multi-way branches, based on values computed by the ALU, is frequently desirable. Such a feature can readily be added to the architecture of Fig. 3, yielding that of Fig. 4, by parti¬ tioning the multiplexer Ml, into two sections, handling the current instruction and next address fields respectively. The current instruction field .operates as described above, ' as does most of the next address field. A portion of -the address field is provided with an additional input channel ("BRANCH" in Fig. 4) supplied from a register previously loaded by the ALU. A control bit in the current instruction would enable this additional selection when required, so replacing the chosen address field with the value previously computed. Literal Outputs Modification Another infrequently used, but nonetheless valuable feature is the ability for the microprogram to supply literal values to the ALU at certain times. This feature may be obtained by addition of the LITERAL register (Fig. 4). On every machine cycle, the current value in one memory bank (in this example memory Bank B) may be loaded into this register, which can be read by the ALU when required. This implies that instructions to load meaningful data into the literal register must themselves reside in Bank A, since the corresponding Bank B location contains literal data, not an instruction. Since no penalty attaches to branching from one bank to another, this is not a problem. Once loaded, the value in the literal register is simply another ALU input, to be accessed when required.

Subroutines Modification If the LITERAL register is capable of passing data to the BRANCH register (or, indeed, if they are the same register), a ready means exists to provide a single level of subroutine linkage. Multiple register sets could provide multiple subroutine nesting levels. This simple scheme onlypermits subroutines to be called from Bank A but as seen above, it is not a serious problem.

Claims

THE CLAIMS DEFINING THE^■INVENTION-ARE-AS-FOLLOWS:

1. In a microprogram controller including a memory to store instructions at specified addresses, a register to hold a current instruction including the address in the memory of the following instruction an arithmetic logic unit to execute the current instruction and thereby manipulating external data as well as altering the choice of following instruction; the improvement comprising dividing the memory into two or more banks and presenting the output of each memory, each said output being a possible following instruction, to a first multiplexer which is connected to the instruction register, and providing a second multiplexer to simultaneously with the execution of the current instruction receive as input any number of various conditions (including "1" and "0") one at a time, developed by the arithmetic logic unit and to develop a binary output to determine which of the following instructions at the first multiplexer is loaded into the register to be next executed.

2. The invention as claimed in claim 1 wherein the first multiplexer is partitioned into two sections for handling the current instruction and next address fields respectively and providing the address field with an additional input channel supplied from a register previously loaded by the arithmetic logic unit.

3. The invention as claimed in claim 1 or claim 2 wherein a LITERAL register is added to enable the micropro¬ gram to supply literal values to the arithmetic logic unit at certain times. 4. The invention as claimed in any preceding claims including means to provide a single or multiple levels of subroutine nesting levels.