Classifications

• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
  • G05F3/02—Regulating voltage or current
  • G05F3/08—Regulating voltage or current wherein the variable is dc
  • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
  • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
  • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
  • G05F3/26—Current mirrors
• • G—PHYSICS
  • G05—CONTROLLING; REGULATING
  • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
  • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
  • G05F3/02—Regulating voltage or current
  • G05F3/08—Regulating voltage or current wherein the variable is dc
  • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
  • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
  • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
  • G05F3/26—Current mirrors
  • G05F3/262—Current mirrors using field-effect transistors only

Definitions

• the present invention relates to a technique for implementing a current source in field effect transistor technology.
• circuits that provide a constant reference voltage, but relatively less on the apparently similar job of producing a constant reference current.
• FET field effect transistor
• steps are frequently taken to mitigate the effects of large lot-to-lot variations in device parameters, for which field effect transistors are notorious.
• circuits are usually designed to minimize the effects of threshold and gain variations that occur for field effect transistors on different wafers.
• a resistor is typically included in the source path of a FET to provide degenerative feedback, which reduces these variations.
• a reference field effect transistor has a resistor connected between the gate and source electrodes. Means are included to cause a reference current to flow in the reference resistor, and be proportional with the channel current of the reference transistor.
• the reference current can be made to have a positive, negative, or zero temperature coefficient.
• the reference circuit When utilized with analog or digital field effect transistor circuitry implemented on the same semiconductor substrate, the reference circuit also compensates for processing variations.
• the field effect transistor is an enhancement mode type.
• FIG. 1 illustrates a field effect transistor current source reference circuit according to the present invention.
• FIG. 2 illustrates a first circuit for implementing the present invention.
• FIG. 3 illustrates a second circuit for implementing the present invention.
• FIGS. 4 and 5 show controlled transistors for implementing current sources relative to positive and negative voltage terminals, respectively.
• FIGS. 6 and 7 illustrate a prior art current source reference resistor.
• FIGS. 8, 9, and 10 illustrate an inventive current source reference resistor.
• FIG. 11 illustrates the effect of process variations on current source output for reference resistors of differing widths for the resistor type shown in FIGS. 8-10.
• the following description relates to a circuit which can provide a temperature and power supply independent currrent, and in a preferred embodiment actively compensates for inherent process variations. This results in a smaller spread of linear circuit parameters, such as operational amplifier slew rate, gain, and gain- bandwidth, than can be obtained with an "ideal" current source.
• the present technique results in part from a recognition that positive and negative temperature coefficient terms can be balanced to a desired degree in a FET, to obtain a desired temperature coefficient.
• the present invention also provides that the current source FET may be fabricated by the same fabrication process (e.g., on the same semiconductor substrate) as the circuits utilizing the controlled current, Then, process variations produce changes in the current source FET that offset changes- in performance parameters (e.g., gain, slew rate, etc.) in the controlled circuit.
• a FET is utilized to good advantage as a current source.
• FIG. 1 The basic core of the source is shown in FIG. 1 , wherein a field effect transistor has a reference resistor (R) connected between the gate and the source.
• the field effect transistor is typically an insulated gate type
• IGFET i.e., an IGFET
• MOSFET metal-oxide-silicon field effect transistor
• the value of Cox can be calculated as: The permittivity of free space times the dielectric constant of the gate insulator (about 3.85 for an oxide) divided by the thickness of the gate insulator. Equation (1) may be solved for VGS:
• the temperature coefficient of VGS is the sum of two terms. The first involves 3, whose temperature dependence arises from that of the mobility of the majority carriers flowing in the channel between the source and the drain.
• the mobility ( ⁇ ) is limited by lattice scattering, which has a temperature dependence of:
• ⁇ Q is the mobility at temperature To.
• the threshold voltage (Vt) has an intrinsic negative temperature coefficient that depends only weakly on process parameters. For a typical Complementary MOS (CMOS) technology based upon 3-5 micrometer design rules, this value is -2.3 v/degree C. Equation (2) can now be written as:
• VGS Vt + (2I/3 0 ) 1/2 (T/T0) 3/4 .
• 3 0 is the gain at temperature To.
• the gain in turn can be set according to considerations known in the art, including, for example, the approximation given above.
• the ability of this source to compensate for process variations is also shown in Equation 4.
• a "fast” (e.g., relatively thin gate oxide and short channel length) process will have a large 3, and thus a -small value of. VGS.
• the reference current (I R ) is equal to VGS/R, so it will decrease.
• a “slow” (e.g., relatively thick gate oxide and long channel length) process with a small 3 will have a larger VGS, and thus a larger reference current.
• a fast process usually results from relatively more etching of the gate material, which. reduces its length relatively more than its width.
• the channel current through the reference transistor (M3) should be held proportional to the reference current (I R ).
• transistor M1 mirrors the channel current in M5, which is connected as a diode.
• M5 also causes the reference current I R to flow through R1.
• I R is identical to the channel current flowing through M5.
• the bias-out positive (BOP) provides a voltage to the gate of one or more P-channel current output transistors M50;.see FIG. 4.
• the output current, I . is proportional to the reference current, I R .
• the proportionality constant depends upon the size of M50 as compared to M5 of FIG. 2 (or as compared to M48 of FIG. 3.)
• a corresponding bias-out negative (BON) can be supplied to one or more N-channel current output transistors M60; see FIG. 5.
• FIG. 3. A more typical circuit employing the inventive concept is shown in FIG. 3.
• M410 is sized to draw a small current, typically less than 0.1% of the current through reference resistor R1 , which is set at a nominal value of 100 ⁇ a.
• M410 and its bias resistors can be replaced by a depletion transistor.
• the other additional transistors are optionally included to improve power supply rejection by cascading all of the mirrors, and to mirror the current to M413, which actually drives the negative bias output (BON).
• a positive bias output (BOP) is provided from the drain of M48.
• the reference resistor R1 can be of any type that gives a positive temperature coefficient of resistance. It is advantageously made with a P+ diffusion, which has a much lower TCR (temperature coefficient of resistivity) and VCR (voltage coefficient of resistivity) than the P-tub. The absolute control of the P+ sheet resistance is also very good, typically within plus or minus 15% of the nominal value. R1 can alternately be made of polysilicon or other material. The sizes of R1 and reference transistor M45 are typically set to give a zero TCC (temperature 'coefficient of current) in M413 and M48 at nominal conditions. The resistance of the reference resistor (R1) is typically greater than 100 ohms, and typically less than 10 megaohms, although a wider range is possible.
• the size of the reference transistor (M45) is desirably chosen so that the channel length ( ) is large enough to minimize processing variations. A length of about 8 to 10 micrometers is suitable for typical processing conditions. Then, the gain may be set by choosing the width, Z, to give the desired temperature coefficient.
• One methodology for obtaining the desired temperature coefficient of the current from the source is as follows:
• Source A 100 ⁇ a ideal source Source B Band-gap source, I VBG/R,
• VBG 1.2 volts
• Source C VBE/R source
• Source D VGS/R source (FIG. 3)
• the resistor R was assumed to be made with P+ diffusion, and to have a plus or minus 15% maximum variation with processing.
• Varying the temperature from 0 to 100°C showed that the VBE/R source has by far the largest temperature variation.
• the band-gap source (B) also has an appreciable TCC due to the finite TCR of the resistor.
• the self-compensating feature of the VGS/R source was apparent.
• the low speed process gives 35% higher current, and the high speed process 30% lower current than nominal. Both cases show a larger TCC than exists with the nominal process, but ho worse than that of the band-gap source (B).
• the effect of the different current sources on the performance of a typical operational amplifier (op-amp) has also been investigated.
• the op-amp used in these simulations was a simple two stage design. There are two independent effects of temperature on op-amp performance. The first is the intrinsic effect of temperature on the op- amp, independent of current. The second is the effect of current variations due to the temperature dependence of the current source.
• the ideal current source (A) is used in these simulations to separate these two effects.
• the slew rate, gain-bandwidth product (GBW) , and gain, as a function of temperature were investigated for nominal processing at a constant current of 100 ⁇ a.
• PSRR power supply rejection ratio-
• CMRR common mode rejection ratio
• common mode range is somewhat worse. This is due to exactly the self-compensating feature that improves the other parameters.
• the smallest common mode range exists when the transistors are slow and the current is high. In other current sources there is no connection between these two; even when the worst-case assumption of high current is made, it is not as high as it is in the self-compensating source. For the op-amp used here, this results in a worse-case loss of 500mv of input range.
• Rs is the sheet resistance of the doped semiconductor
• L and W are the length and width of the field oxide defined opening
• FIGS. 8 and 9 Another way to define the resistor is shown in FIGS. 8 and 9.
• the polysilicon (poly) level is used instead of the field oxide to define the feature size.
• the poly line size is one of the most critical and well controlled parameters in the process, and in self- aligned silicon gate technology, the polysilicon layer defines the gate electrode size. Hence, the poly line size will often determine whether any given wafer is "slow” or "fast". For this reason, a resistor defined by the layer that defines the gate electrode can have a tighter design tolerance than one defined by the field oxide.
• the actual poly line size differs from the nominal size by an amount DL.
• a positive DL means wider poly and a slower process
• negative DL means narrow poly and a fast process.
• a positive DL (slow process) causes the resistor to increase, and the negative DL (fast process) causes it to decrease from the design value. This will oppose the "self-compensation" feature of the VGS/R source, since process induced changes in VGS will now be tracked by a similar change in R.
• the relative value of these two quantities depends on the resistor's nominal width. For an extremely wide resistor, R does not depend on DL at all. As the resistor width decreases, the effect of DL becomes larger. Note that other self-aligned gate electrode materials (e.g., a refractory metal or metal suicide) can be used to define the resistor, to achieve this effect.
• the current I VGS/R for three different resistor widths is shown in FIG. 11.
• the circuit shown in FIG. 3 has been implemented in a typical 3.5 micron Twin-Tub CMOS process on a n-type substrate on a lot in which the poly width was intentionally varied.
• the resistor R1 was poly defined, with a nominal width of 4 microns.
• the current vs. temperature curves for three different wafers were determined.
• the sheet resistance of the P+ diffusion, was measured at 10 percent below the nominal value for this lot. This accounts for most of the difference between the measured current of 107 ⁇ a and the design value of 100 ⁇ a for the nominal poly.
• the current calculated from FIG. 11 was 87% of the nominal value, and the measured current was 84% of the nominal.
• the calculated current was 105% nominal, and the measured current was 114% of the nominal.
• the maximum variation of current over the temperature range 10°C - 120°C was 2.1%. From 25°C - 120°C it is 1.5%. Both the narrow and wide poly had similar temperature variations of their current.
• the temperature coefficient of current can be selected to be either zero (nominally, as second order effects give a slight curvature) , positive, or negative. If a zero temperature coefficient of current is desired, the resulting controlled current can be readily maintained within +5 percent, and typically within +2 percent, of the average value, over a temperature range of from 0°C to 100 ⁇ C, or even wider. These values are even more readily obtained over a typical commercial temperature range of from 0°C to 70 ⁇ C.
• the current source automatically compensates for variations in the transistor process, with a "fast” -process giving lower current and a "slow” one giving a higher current.
• this compensation can be reduced or eliminated with respect to variations in the polysilicon line width size by proper, resistor design. While the above example has been for an enhancement mode MOSFET, similar considerations apply for depletion mode devices, including junction field effect transistors, and Shottky gate field effect transistors (e.g., MESFETS) implemented in gallium arsenide or other III-V materials.
• MESFETS Shottky gate field effect transistors
• enhancement mode FET's i.e., those having a threshold voltage, Vt, that is >0 for an n- channel device, and vt ⁇ 0 for a p-channel device.
• Vt threshold voltage
• VGS vt ⁇ 0 for a p-channel device.
• Enhancement mode field effect transistors are typically of the insulated gate (IGFET) type, of which MOSFET's are an example. Their use is advantageous because a smaller channel current can then typically be utilized in the reference transistor than if a depletion-mode device were used.
• the reference current is directed through the reference resistor in the direction that causes the channel current in the reference transistor to flow (or to increase its flow), as the reference current increases. That is, VGS is generated in the direction of forward bias by the reference current.
• enhancement mode field effect transistors are usually available on an integrated circuit using fewer process steps than depletion mode devices require.
• the means for causing the channel current and the reference current to .be proportional inherently produces the desired direction of reference current flow.
• This is in contrast with the prior art technique*of biasing a current source FET using degenerative feedback by placing a resistor in the source path. In that case, an increase in the current through the resistor causes a change in VGS in the direction that tends to decrease the channel current of the FET.
• the present invention may be used in analog integrated circuits, it may also be used in digital integrated circuits.
• a current source for the sense amplifiers, for improved speed and sensitivity.
• the use of a controlled current source is known for use with digital logic circuits to reduce chip-to-chip performance variations.
• the current source associated with the logic gates has been controlled using a reference clock and comparator circuitry; see “Delay Regulation - A Circuit Solution to the Power/Performance Tradeoff", E. Berndlmaier et al, IBM Journal of Research and Development, Vol. 25, pp. 135-141 (1981).
• the present invention can advantageously be implemented on the same chip or wafer as the logic gates to perform this function.
• a single bias circuit e.g., FIG. 3
• a plurality of current output transistors FIGS. 4, 5
• the term "integrated circuit” as used herein includes both utilizations.
• the controlled current from the present source can be used to produce a controlled voltage, as by passing it through a resistor having a given temperature coefficient, or through a resistor-diode combination; i.e., a band-gap reference, etc.
• the characteristics of a band ⁇ gap reference are described in "New Developments in IC Voltage Regulators", R. J.
• the controlled current can have a desired temperature coefficient chosen over a wide range, the resulting voltage can be used for a variety of purposes.
• the device receiving the controlled current may be formed on a different substrate from the current source.
• an optical emitter e.g., light emitting diode or laser diode
• I R has a positive T.C
• APPENDIX Referring to the current source shown in FIG. 2; define a reference current I R as the current through R1 , IDS3 as the current through M3 with gate to source voltage VGS3, and KI R as the current through M4, where K is the feedback constant determined by the relative sizes of M1 , M2, M4, and M5.
• K is the feedback constant determined by the relative sizes of M1 , M2, M4, and M5.
• Equation (5A) reduces to:
• Equation (5A) Equation (5A) reduces to:
• the temperature behavior of this current source can be varied negative or positive, or made essentially zero, by proper choices of value of the reference resistor, R1 , the size of transistor M3, and the value of the feedbac constant K. Note that these factors influence the channel k current through the reference transistor, as indicated by (1A).

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Nonlinear Science (AREA)
• Electromagnetism (AREA)
• General Physics & Mathematics (AREA)
• Radar, Positioning & Navigation (AREA)
• Automation & Control Theory (AREA)
• Control Of Electrical Variables (AREA)
• Amplifiers (AREA)
• Logic Circuits (AREA)

Priority Applications (4)

Applications Claiming Priority (4)

Publications (1)

Family

ID=27097177

Family Applications (1)

Country Status (8)

Cited By (4)

Families Citing this family (1)

Citations (2)

• 1985
  • 1985-09-18 EP EP85904764A patent/EP0197965B1/en not_active Expired - Lifetime
  • 1985-09-18 KR KR860700318A patent/KR880700349A/ko not_active Application Discontinuation
  • 1985-09-18 WO PCT/US1985/001805 patent/WO1986002180A1/en active IP Right Grant
  • 1985-09-18 DE DE8585904764T patent/DE3581399D1/de not_active Expired - Fee Related
  • 1985-09-26 ES ES547346A patent/ES8700502A1/es not_active Expired
  • 1985-09-30 CA CA000491877A patent/CA1252835A/en not_active Expired
• 1991
  • 1991-10-11 SG SG842/91A patent/SG84291G/en unknown
• 1992
  • 1992-06-18 HK HK446/92A patent/HK44692A/xx unknown

Patent Citations (2)

Also Published As

Similar Documents

Legal Events