WO1984000852A1 - Memoire non-volatile a semiconducteur - Google Patents

Memoire non-volatile a semiconducteur Download PDF

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Publication number
WO1984000852A1
WO1984000852A1 PCT/US1983/001219 US8301219W WO8400852A1 WO 1984000852 A1 WO1984000852 A1 WO 1984000852A1 US 8301219 W US8301219 W US 8301219W WO 8400852 A1 WO8400852 A1 WO 8400852A1
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WO
WIPO (PCT)
Prior art keywords
memory device
silicon
layer
oxide
memory
Prior art date
Application number
PCT/US1983/001219
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English (en)
Inventor
James Anthony Topich
Original Assignee
Ncr Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ncr Co filed Critical Ncr Co
Publication of WO1984000852A1 publication Critical patent/WO1984000852A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors

Definitions

  • This invention relates to non-volatile semiconductor memory devices of the kind including a semiconductor substrate, a first insulator layer formed by a silicon dioxide layer provided on said substrate, a second insulator layer provided on said first insulator layer and a conductive gate electrode provided on said second insulator layer.
  • MNOS Metal gate/silicon gate-insulator-semiconductor devices of the MNOS/SNOS type and their non-volatile charge retention are well-known. Briefly, when a large positive voltage is applied between the gate and the silicon substrate of a MNOS (hereafter MNOS includes
  • SNOS SNOS
  • electrons will tunnel through the thin (10-50 Angstroms thickness) oxide layer and are stored in deep traps at the oxide-nitride interfact or in the nitride bulk under the influence of a high electric field of the order of 10 7 volts per cm. Tunneling of electrons through oxide layers of thickness less than about 20 Angstroms is by direct tunneling and through oxide layers of thickness exceeding about 20 Angstroms is by Fowler-Nordheim tunneling. As a result of this trapping of electrons in the gate dielectric the conductivity of the underlying semiconductor changes. If the semiconductor is of n-type material, the trapping of electrons may invert the semiconductor into p-type material.
  • non-volatile charge retention The electrons stored in the nitride gate dielectric eventually decay in a logarithmic fashion through two possible mechansisms : (1) back tunneling into the silicon substrate; (2) conduction through the nitride itself. Which of these is the dominant charge transfer mechanism depends on such parameters as (1) memory oxide thickness; (2) density of interfacestates created by the lattice mismatch of the two dielectrics and; (3) energy and spatial distribution of traps in the nitride.
  • the memory device written in the above manner may be erased by applying a sufficiently large negative voltage to the transistor's gate with respect to the substrate to cause the electrons trapped in the nitride to return to the substrate and to replace them by trapped positive charges.
  • retention means the capability of the memory device to retain usable data for a period of time.
  • Eundurance means the capability of the device to endure erase/write cycling and still provide adequate retention.
  • a memory device of the kind specified is known from the article by P C Y Chen "Threshold-Alterable Si-Gate MOS Devices" in IEEE Transactions on Electron Devices, Vol. ED-24, No. 5, May 1977, pages 584-586.
  • the Chen article discloses a memory device having a polysilicon-nitride-oxide-silicon structure. This device has the disadvantage of a limited retention capability.
  • the Chen article also discloses a structure wherein undesirable charge injection from the silicon gate electrode is prevented by providing a silicon oxynitride layer between the nitride and the polysilicon gate. This latter structure has the disadvantage that complex processing steps are required for its manufacture.
  • a non-volatile semiconductor memory device of the kind specified, characterized in that said second insulator layer is formed by a silicon oxynitride layer.
  • a memory device according to the invention has a high degree of charge retention as compared with a polysilicon-nitride-oxide-silicon structure device. Furthermore since only two insulator layers are provided, it will be appreciated that a device according to the invention is simple to manufacture because only a small number of process steps are required. The latter advantage leads to improved yields in manufacture and hence to a saving in manufacturing costs.
  • FIG. 1 is a cross-sectional representation of an embodiment of the non-volatile memory device according to the present invention.
  • FIG. 1 there is shown in this Figure a partial sectional view of a portion of an exemplary memory device 50 embodying the principles of the present invention.
  • Fig. 1 in particular illustrates a trigate n-channel field effect transistor 50 having a silicon gate-oxynitride-oxide-silicon or SO n OS (where
  • O n designates oxynitride (O n designates oxynitride) gate structure 40.
  • the device 50 of Fig. 1 comprises a single crystal silicon substrate 10 of one conductivity type, illustratively, ptype. The substrate 10 is partitioned into the device active area by regions 11-11 of thick field oxide.
  • the n- ⁇ hannel FET 50 includes a pair of n-type surface adjacent source and drain impurity regions 15 and 16, respectively, which are self-aligned with the overlying gate structure 40 and which define a channel region in the substrate 10 lying between the source and drain regions 15, 16.
  • the source and drain may be formed by any of the well-known techniques such as by selective diffusion of impurities through an oxide mask or by ion implantation.
  • the exemplary gate structure 40 consists of a central memory portion 12 having a thin (20-35 Angstroms thickness) memory oxide and flanked by two non-memory portions having thick (1,000-2,000 Angstroms thickness) non-memory oxide regions 12A-12A. Overlying these memory and non-memory oxide regions is a uniform thickness (200-500 Angstroms thickness) silicon oxynitride gate insulator 13. The oxynitride 13 in turn is covered by a polyerystalline silicon electrode 14 of thickness (3,000-5,000) Angstroms.
  • the memory oxide 12 and the oxynitride 13 may be formed continuously in the same furnace deposition tube at the same temperature.
  • the oxide 12 is formed by chemical vapor deposition at atmospheric pressure or by steam oxidation of the substrate 10 at a temperature of about 750°C.
  • the oxynitride 13 is formed, immediately thereafter, by LPCVD (low pressure chemical vapor deposition) using reactant gases ammonia (NH 3 ), nitrous oxide (N 2 O) and dichlorosilane (SiH 2 Cl 2 ) in the proportion NH 3 :N 2 O:SiH 2 Cl 2 of 3.5:2:1 at the same temperature as the oxide 12.
  • the polysilicon gate electrode 14 is formed by LPCVD using silane.
  • the ranges of the oxide 12 and oxynitride 13 thicknesses provided above are nominal and are not limiting but are those considered convenient from the point of view of fabrication as well as with respect to convenient values of voltages with which the device may be operated.
  • the oxide 12 and oxynitride 13 may be selected to have thicknesses of about 25 Angstroms and about 275 Angstroms, respectively.
  • a thicker oxynitride, of about 400 Angstroms thickness and an oxide 12 of about the same thickness as in the previous example may be used. It will be appreciated that a SO n OS device having a very thick (i.e.
  • the gate electrode 14 may be of any known highly conductive material, for example, a metal such as aluminum, or alloys such as aluminum-1% silicon, or a refractory metal silicide such as tungsten disilicide or tantalum disilicide or molybdenum silicide.
  • a metal such as aluminum, or alloys such as aluminum-1% silicon
  • a refractory metal silicide such as tungsten disilicide or tantalum disilicide or molybdenum silicide.
  • the gate electrode 14 is made from a nonconductive material, it is doped with n-type impurities to provide a highly conductive gate electrode for the memory device.
  • the memory device 50 is provided with a thick insulating layer 17A-17B-17C made of, for example, phosphosilicate glass, which is appropriately patterned to cover the transistor structure.
  • Insulating layer 17B electrically isolates the gate electrode 14 from the metal conductors 18 and 19.
  • Metal conductors 18 and 19 made of, for example, aluminum make electrical contact with the source 15 and drain 16, respectively.
  • Electrical conductor 20, made of the same material as conductors 18 and 19, is connected to the gate electrode 14.
  • a trigate structure 40 is shown and discussed herein, this invention is applicable to monogate and split gate structures also.
  • the monogate structure consists of a pure memory portion like the central portion of the trigate structure 40 (Fig. 1) having a thin oxide layer and a relatively thick oxynitride layer.
  • the split gate structure consists of a memory portion like the central portion of the trigate structure 40 and a single non-memory portion having thick oxide 12A and oxynitride 13 layers instead of two non-memory portions of structure
  • n-channel trigate devices were fabricated, tested and the test results evaluated. These devices include the conventional silicon gate-nitride-oxide-silicon devices and the present silicon gate-oxynitride-oxide-silicon devices having the basic structure shown in Fig. 1. All the devices had the same thickness memory oxide (20 Angstroms) and polysilicon gate (3,000 Angstroms).
  • Table I The test results which focus on the retention characteristics are summarized in Table I. The procedure used for testing the above devices is well-known. The write and erase curves were generated, for example, by subjecting the devices to various pulse-stressing conditions (pulse amplitude and duration) .
  • the amplitude of the pulse was in the ranges ⁇ 13.5 volts to ⁇ 16.5 volts, the positive and negative values being applicable to the write and erase charging characteristics, respectively.
  • the duration of these pulses was in the range of 100 microseconds to about 1 second.
  • the data to determine the charge retention in the devices were obtained by: (1) initializing the devices and determining the initial write and erase threshold voltages; (2) obtaining retention graphs from these devices by storing the devices at an elevated temperature of 100°C for a time of up to 10 seconds and determining the threshold voltages at intervals during this time.
  • the initialization procedure (step 1) i.e.
  • initial window represents the initial memory margin of the device
  • write state decay rate is the slope of the write (threshold voltage) curve
  • erasesed state decay rate is the slope of the erase (threshold voltage) curve.
  • the device of the present invention was also tested for write/erase cycling (or endurance) effects. These tests showed that the read access performance was not noticeably affected even after 10,000 write/erase cycles, thus indicating that the cumulative write/erase stressing did not increase the rate of charge loss from the oxide-oxynitride gate insulator. In other words, the end result is that the present SOnOS device is inherently better than the SNOS device because of the improved retention.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

Une mémoire non-volatile à semiconducteur comprend un substrat semiconducteur (10), une couche de dioxyde de silicium (12) disposée sur le substrat semiconducteur (10), une couche d'oxynitrure de silicium (13) disposée sur la couche de dioxyde de silicium (12) et une électrode de porte conductrice (14) disposée sur la couche d'oxynitrure de silicium (13). Le dispositif de mémoire non-volatile peut être un condensateur ou, là où existent des régions de sources et de drains (15, 16), un transistor. La couche de dioxyde de silicium (12) peut présenter des parties (12A) d'épaisseur plus grande à proximité des régions de sources et de drains (15, 16). Le dispositif présente une capacité élevée de rétention de charge.
PCT/US1983/001219 1982-08-12 1983-08-08 Memoire non-volatile a semiconducteur WO1984000852A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US40737482A 1982-08-12 1982-08-12

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0617461A2 (fr) * 1993-03-24 1994-09-28 AT&T Corp. Procédé pour la formation de couches diélectriques oxynitrides lors de la fabrication de circuits intégrés
US5397720A (en) * 1994-01-07 1995-03-14 The Regents Of The University Of Texas System Method of making MOS transistor having improved oxynitride dielectric
US5478765A (en) * 1994-05-04 1995-12-26 Regents Of The University Of Texas System Method of making an ultra thin dielectric for electronic devices
EP0844647A2 (fr) * 1996-11-26 1998-05-27 Texas Instruments Incorporated Diélectrique composite à faible densité de défauts

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1951787A1 (de) * 1968-10-14 1970-04-30 Sperry Rand Corp Speicherelement
FR2111866A1 (fr) * 1970-10-27 1972-06-09 Yamazaki Shumpei
EP0006706A1 (fr) * 1978-06-14 1980-01-09 Fujitsu Limited Procédé pour la fabrication d'un dispositif semiconducteur, muni d'une couche isolante de dioxyde de silicium recouverte d'une couche d'oxynitrure de silicium
DE2832388A1 (de) * 1978-07-24 1980-02-14 Siemens Ag Verfahren zum herstellen einer integrierten mehrschichtisolator-speicherzelle in silizium-gate-technologie mit selbstjustierendem, ueberlappenden polysilizium-kontakt
WO1983002199A1 (fr) * 1981-12-14 1983-06-23 Ncr Co Dispositif de memoire non-volatile a semiconducteur et son procede de fabrication

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1951787A1 (de) * 1968-10-14 1970-04-30 Sperry Rand Corp Speicherelement
FR2111866A1 (fr) * 1970-10-27 1972-06-09 Yamazaki Shumpei
EP0006706A1 (fr) * 1978-06-14 1980-01-09 Fujitsu Limited Procédé pour la fabrication d'un dispositif semiconducteur, muni d'une couche isolante de dioxyde de silicium recouverte d'une couche d'oxynitrure de silicium
DE2832388A1 (de) * 1978-07-24 1980-02-14 Siemens Ag Verfahren zum herstellen einer integrierten mehrschichtisolator-speicherzelle in silizium-gate-technologie mit selbstjustierendem, ueberlappenden polysilizium-kontakt
WO1983002199A1 (fr) * 1981-12-14 1983-06-23 Ncr Co Dispositif de memoire non-volatile a semiconducteur et son procede de fabrication

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0617461A2 (fr) * 1993-03-24 1994-09-28 AT&T Corp. Procédé pour la formation de couches diélectriques oxynitrides lors de la fabrication de circuits intégrés
EP0617461A3 (fr) * 1993-03-24 1995-01-11 At & T Corp Procédé pour la formation de couches diélectriques oxynitrides lors de la fabrication de circuits intégrés.
US5397720A (en) * 1994-01-07 1995-03-14 The Regents Of The University Of Texas System Method of making MOS transistor having improved oxynitride dielectric
US5541436A (en) * 1994-01-07 1996-07-30 The Regents Of The University Of Texas System MOS transistor having improved oxynitride dielectric
US5478765A (en) * 1994-05-04 1995-12-26 Regents Of The University Of Texas System Method of making an ultra thin dielectric for electronic devices
EP0844647A2 (fr) * 1996-11-26 1998-05-27 Texas Instruments Incorporated Diélectrique composite à faible densité de défauts
EP0844647A3 (fr) * 1996-11-26 1998-06-03 Texas Instruments Incorporated Diélectrique composite à faible densité de défauts
US5969397A (en) * 1996-11-26 1999-10-19 Texas Instruments Incorporated Low defect density composite dielectric

Also Published As

Publication number Publication date
EP0118506A1 (fr) 1984-09-19

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