WO1982002977A1 - Cellule de memoire ayant plus de deux niveaux de tension - Google Patents

Cellule de memoire ayant plus de deux niveaux de tension Download PDF

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Publication number
WO1982002977A1
WO1982002977A1 PCT/US1982/000136 US8200136W WO8202977A1 WO 1982002977 A1 WO1982002977 A1 WO 1982002977A1 US 8200136 W US8200136 W US 8200136W WO 8202977 A1 WO8202977 A1 WO 8202977A1
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WO
WIPO (PCT)
Prior art keywords
field effect
effect transistor
memory
storage locations
transistor
Prior art date
Application number
PCT/US1982/000136
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English (en)
Inventor
Inc Motorola
Richard H Adlhoch
Original Assignee
Inc Motorola
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inc Motorola filed Critical Inc Motorola
Publication of WO1982002977A1 publication Critical patent/WO1982002977A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states

Definitions

  • Patent Applications Serial Numbers CR-81086 and CR-81087 are related copending applications by the same inventor, assigned to the same assignee, and filed on the same date as the present application.
  • This invention relates, in general, to memory cells and more particularly, to a memory cell having more than two voltage levels and a method for making same.
  • it has been customary for read-only memories using field effect transistors to have at most one transistor per bit. In such a case, if there was a transistor in the memory cell location, then a logic 1 was considered stored there. If no transistor existed in the memory storage location, then a logic 0 was considered to be stored in that location. Therefore, each storage location was only capable of storing one bit of information per storage cell location.
  • ROM read-only memory
  • These new ROM cells control the number of states stored by varying the gain of the transistor.
  • the gain can be preset by varying the size of the transistor or by changing the threshold of the transistor.
  • Such a ROM cell has been disclosed in patent application Serial No. 972,619 filed December 22, 1978, for Jerry D. Moench, and assigned to the same assignee as the present application.
  • Another object of the present invention is to provide a read-only memory array having a plurality of storage locations wherein each storage location contains a complete transistor.
  • Yet another object of the present invention is to provide a read-only memory array having a plurality of storage locations wherein each storage location has a field effect transistor of the same physical size, and wherein the memory cells are capable of storing more than two logic states.
  • a further object of the present invention is to provide a read-only memory array and method for making same wherein the memory array has a plurality of storage locations each having a field effect transistor connected in a source follower configuration and some of the field effect transistors have threshold voltages which are different from other of the field effect transistors.
  • a read-only memory array having a new and novel memory cell which is capable of storing more than two voltage levels.
  • the memory array has a first field effect transistor connected in a source follower configuration in a first storage location, and at least a second field effect transistor connected in a source follower configuration and located in another storage location.
  • the first and second field effect transistors are substantially the same physical size but yet have different threshold voltages. Since the transistors are connected in a source follower configuration, the voltage at the source of the transistor is the gate voltage minus the transistor's threshold voltage. Therefore, the threshold voltages of the transistors can be shifted in any suitable manner, such as by ion implantation or the like, so that the storage locations are capable of providing more than two choices of predetermined voltage levels.
  • FIG. 1 illustrates in schematic form a memory array using the present invention in one form thereof;
  • FIG. 2 illustrates an abbreviated form of the memory array of FIG. 1 with additional output circuitry;
  • FIG. 3 is a plan view of a portion of a memory chip showing programming mask locations.
  • FIG. 1 illustrates a portion of a read-only memory wherein only four storage locations are illustrated in order to keep the drawing from becoming overcrowded.
  • Each of the four storage locations contains a field effect transistor 10, 11, 12, and 13, respectively. Only two bit lines 16 and 17 and two row select lines 21 and 22 are illustrated. It will be understood that the memory array contains many bit lines and row-select lines in addition to many storage locations.
  • a difference between the memory array illustrated in FIG. 1 and the prior art memory arrays is that transistors 10/ 11, 12, and 13 can have different threshold voltages. Any convenient and well-known method of changing thresholds of field effect transistors can be used.
  • the threshold voltage of the transistors can be adjusted so that each memory location can have one of many different voltage levels to represent many different bits of information.
  • the optimum number of levels is four since having a memory location storing more than a four-state signal would increase the complexity of the sensing and readout circuitry of the memory.
  • a four-state cell would double the read-only memory bit capacity since each storage location would be capable of storing two bits of information instead of one bit of information. Accordingly, in a preferred embodiment, the illustrated memory array will be referred to as a four-state memory cell.
  • Transistor 10 has a drain electrode connected to a voltage terminal 14 and a source electrode connected to bit line 16. The gate electrode of transistor 10 is connected to row-select line 21. Row-select line 21 is also connected to the gate electrode of transistor 11.
  • Transistor 11 has its drain electrode connected to voltage terminal 14 and a source electrode connected to bit line 17.
  • Transistor 12 has its drain electrode connected to voltage terminal 14 and a source electrode connected to bit line 16.
  • Transistor 13 has its source electrode connected to bit line 17 and its drain electrode connected to voltage terminal 14. The gate electrodes of transistors 12 and 13 are connected to row-select line 22. Any suitable voltage source or signal can be connected to voltage terminal 14 keeping in mind that such voltage must be equal to or greater than the voltage applied to the gate electrode.
  • the transistors in the memory array illustrated in FIG. 1 are connected in a source follower configuration and therefore the voltage appearing on a bit sense line will be the voltage applied to the gate electrode of the transistor minus its threshold voltage. Therefore, as a matter of example, if the threshold voltage of transistor 10 is 6/10ths of a volt, and the threshold voltage of transistor 11 is 1.8 volts, and if a 5 volt signal is applied to row-select line 21/ then the voltage appearing on bit line 16 would be 4.4 volts and the voltage appearing on bit line 17 would be 3.2 volts. In such a case, the voltage appearing on bit line 16 could be considered to be a binary 00 and the voltage level appearing on bit line 17 could be considered to be a binary 01.
  • threshold of transistor 10 were adjusted to be 3.0 volts and the threshold voltage of transistor 11 were adjusted to be 4.2 volts, then when a 5 volt signal is applied to row-select line 21, the voltage level appearing on bit line 16 could be considered to be binary 10 and the voltage appearing oh bit line 17 could be considered to be binary 11.
  • transistor 11 might appear to be an open circuit.
  • the parasitic capacitance 18 associated with bit line 16 will be the same as the parasitic capacitor 19 associated with bit line 17.
  • the sensing and readout operation becomes easier to perform.
  • Bit line 16 is shown as coupled to a reference voltage illustrated as ground by transistor 23.
  • Bit line 17 is coupled to ground by transistor 24.
  • the gate electrodes of transistors 23 and 24 are connected to a pre-charge line. When a precharge signal enables transistors 23 and 24, then the bit sense lines of the memory array are all discharged to ground.
  • a transistor 29 couples bit sense line 16 to an output line 32. Output line 32 goes to a sense amplifier (not shown in FIG. 1).
  • Bit line 17 is coupled to output line 32 by a transistor 28.
  • Transistor 29 has its gate electrode connected to column-select line 30.
  • Transistor 28 has its gate electrode connected to column-select line 31.
  • Output line 32 is coupled to ground by transistor 25 which has its gate electrode connected to the precharge line.
  • Storage location 40 has a field effect transistor connected in a source follower configuration.
  • the drain electrode of the transistor in storage location 40 is connected to voltage terminal 41 and its source is connected to bit line 44. Its gate is connected to row-select line 42.
  • the source follower configured transistor in storage location 40' has its drain electrode connected to voltage terminal 41 and its source electrode connected to bit line 44.
  • the gate electrode of the transistor in storage location 40' is connected to row-select line 43.
  • Bit sense line 44 is connected to a sense amplifier 46. Sense amplifier 46 provides three outputs.
  • Decoder 47 receives the three outputs from sense amplifier 46 and decodes the three outputs to provide bit 1 on output 48 and bit 2 on output 49 of a two bit binary output.
  • a two bit binary signal is capable of four states.
  • bit lines 50 and 51 are metal
  • row select lines 52, 53, 54, 55 and 56 are polysilicon lines commonly called poly lines.
  • the source area of two adjacent transistors is located between lines 55', 56', 60' and 61'. Connection of this source area to bit line 50 is through preohmic 62.
  • the area between row lines 54 and 55 basically defines the drains for the transistors having gate electrodes connected to row lines 54 and 55. The drains located between the row lines are interconnected.
  • Area 61 and area 63 do not form electrodes for any of the transistors but serve as isolation regions between sources of the transistors located adjacent to these areas.
  • Areas 65, 66 , 67 and 68 represent programming mask areas that may be used to modify the threshold voltages of transistors within the areas 65 through 68. Each programming mask will not necessarily have openings as represented by areas 65 through 68. In addition, it will be understood that if a programming mask area is not needed that the adjacent areas will extend up to the unneeded area.
  • a space is illustrated between areas 65, 66, 67 and 68 only for purposes of clarity in the drawing. There are many more bit lines, row lines, and transistors in a memory array than those shown; however, the pattern repeats itself and therefore nothing is gained by illustrating an entire memory programming mask.
  • the programming mask does not have an opening over a memory location, it means that the transistor in that memory location will have a first threshold voltage.
  • a transistor located under an opening in the programming mask will have a second threshold voltage.
  • a second programming mask is required, If the second programming mask has an opening over a transistor that was not modified by the first programming mask then a third threshold voltage is obtained for that transistor. If an opening in the second programming mask is over a transistor that was modified by the first programming mask, then a fourth threshold voltage is obtained. This procedure of using two different programming masks provides a memory which can store four different states in a given memory cell location.
  • each memory location can have a transistor thereby providing equal capacitance on all the bit sense lines.
  • Process variations which affect parasitic capacitances will not disrupt the operation of the read-only memory array since all parasitic capacitances would be affected somewhat equally.
  • a transistor in each storage location there is no need to have a mask operation to provide complete transistors in one storage location while not providing complete transistors in yet other storage locations. Instead a mask operation can be used to shift the threshold voltage levels of preselected storage, locations. By using the same size transistors in all storage locations regardless of which voltage level is stored therein , the transistors can be made smaller thereby resulting in an overall smaller memory array.
  • the circuit By having the transistors smaller, the circuit will tend to operate faster. Also, by having the capacitance of the bit lines constant, the circuit speed will be more constant and easily predictable. Since memory devices can all be made of a minimum size, they will draw a minimum amount of current and hence result in a memory array which requires less operating power.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

Memoire morte matricielle ayant des cellules de stockage (10-13) capables de stocker plus de deux etats logiques. Les dimensions des dispositifs utilises dans les cellules de stockage (10-13) peuvent etre toutes identiques. Si les dispositifs sont connectes dans une configuration suivant la source, le niveau de tension associe a chaque cellule de stockage de la memoire peut etre commande en reglant selectivement la tension de seuil du dispositif. Dans une telle memoire matricielle, il est possible que tous les dispositifs aient la meme dimension et par consequent il est possible de les fabriquer avec une dimension minimum ce qui reduit la dimension totale de la memoire.
PCT/US1982/000136 1981-02-25 1982-02-01 Cellule de memoire ayant plus de deux niveaux de tension WO1982002977A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US23818381A 1981-02-25 1981-02-25
US238183810225 1981-02-25

Publications (1)

Publication Number Publication Date
WO1982002977A1 true WO1982002977A1 (fr) 1982-09-02

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EP (1) EP0072846A1 (fr)
IT (1) IT1186670B (fr)
WO (1) WO1982002977A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5122688A (en) * 1988-07-29 1992-06-16 International Business Machines Corporation Trinary check trit generator, latch, comparator and multiplexer

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151603A (en) * 1977-10-31 1979-04-24 International Business Machines Corporation Precharged FET ROS array
JPS54161853A (en) * 1978-06-12 1979-12-21 Seiko Epson Corp Read-only memory
US4192014A (en) * 1978-11-20 1980-03-04 Ncr Corporation ROM memory cell with 2n FET channel widths
US4272830A (en) * 1978-12-22 1981-06-09 Motorola, Inc. ROM Storage location having more than two states
US4287571A (en) * 1979-09-11 1981-09-01 International Business Machines Corporation High density transistor arrays

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151603A (en) * 1977-10-31 1979-04-24 International Business Machines Corporation Precharged FET ROS array
JPS54161853A (en) * 1978-06-12 1979-12-21 Seiko Epson Corp Read-only memory
US4192014A (en) * 1978-11-20 1980-03-04 Ncr Corporation ROM memory cell with 2n FET channel widths
US4272830A (en) * 1978-12-22 1981-06-09 Motorola, Inc. ROM Storage location having more than two states
US4287571A (en) * 1979-09-11 1981-09-01 International Business Machines Corporation High density transistor arrays

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin "Threshold Personalized PLA Device and Method of Fabrication", pp. 3302-3303, W.S. JOHNSON et al, Vol. 10, published March 1976. *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5122688A (en) * 1988-07-29 1992-06-16 International Business Machines Corporation Trinary check trit generator, latch, comparator and multiplexer

Also Published As

Publication number Publication date
EP0072846A1 (fr) 1983-03-02
IT1186670B (it) 1987-12-04
IT8247842A0 (it) 1982-02-22

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