Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4094—Bit-line management or control circuits

Definitions

• the present invention pertains to dynamic semiconductor memory circuits and in particular to the timing of the active pullup operation within such a circuit.
• each memory cell includes a storage capacitor which is charged to one of two voltage states which correspond to binary information.
• the charge on the storage capacitor has a short life time due to leakage within the cell.
• the charge must be periodically refreshed to maintain the data pattern stored in the memory.
• Reading the memory cell comprises connecting the storage capacitor to a digit line so that the charge stored on the capacitor is transferred to the digit line.
• the transfer of charge causes the voltage on the digit line to be changed by a few tenths of a volt / and this voltage change is detected by a sense amplifier which makes a comparison to the voltage on a complementary half of the digit line.
• the ability to correctly read the charge stored on the storage capacitor is dependent upon the voltage on the capacitor at the time that it is read.
• MOSFET metal oxide semiconductor field effect transistor
• a method for writing data into a memory cell of a dynamic semiconductor memory circuit comprising the steps of first driving a half digit line corresponding to the memory cell to at least a first voltage in response to an external command to write data into the memory cell.
• the first voltage is less than the supply voltage for the memory circuit.
• the next step comprises activating a pullup circuit after the half digit line has been driven to at least the first voltage to elevate the voltage on the half digit line to approximately the supply voltage.
• FIGURE 1 is a schematic diagram illustrating the various circuits in a dynamic semiconductor memory which are relevant to the method of the present invention.
• FIGURE 2 is an illustration of various timing and control signals utilized in the circuit shown in FIGURE 1.
• the present invention relates to the operation of a dynamic integrated circuit semiconductor memory fabricated using MOSFET technology.
• Memory circuit 10 has a plurality of memory cells for storing data therein.
• Memory cells 12 and 14 are representative of the plurality of memory cells included within the overall circuit.
• Memory cell 12 includes an access transistor 12a and a storage capacitor 12b.
• the gate terminal of transistor 12a is connected to a word line 16 and the drain terminal of transistor 12a is connected to a half digit line 18.
• the source terminal of transistor 12a is connected to a first terminal of the capacitor 12b and the second terminal of the capacito 12b is connected to ground.
• the memory cell 14 likewise has an access transistor 14a and a storage capacitor 14b.
• the gate terminal of transistor 14a is connected to a word line 20 and the drain terminal of transistor 14a is connected to a half digit line 22.
• a full digit line within circuit 10 comprises a complementary pair of half digit lines such as 18 and 22.
• Each digit line in circuit 10 is split into half digit lines, with each half digit line connected to one input of a sense amplifier, such as amplifier 24.
• Half digit line 18 is connected to amplifier 24 through a transistor 26, and half digit line 22 is connected to amplifier 24 through a transistor 28.
• the drain and source terminals of transistors 26 and 28 interconnect the half digit lines 18 and 22 to the sense amplifier 24.
• Sense amplifier 24 comprises a pair of transistors 30 and 32 which have the source terminals thereof connected together and joined to a latch node 34.
• the drain terminal of transistor 30 is connected to a node 36 which is also connected to transistor 26 and the gate terminal of transistor 32.
• the drain terminal of transistor 32 is co ⁇ cted to a node 38 which is connected to transistor 28 and to the gate terminal of transistor 30.
• Each of the half digit lines is connected to a column select transistor which is operated to selectively connect the half digit line to its respective input/output line.
• half digit line 18 can be connected through column select transistor 40 to an input/output line 42.
• Half digit line 22 can be connected through a column select transistor 44 to an input/output line 46.
• the column select transistors are activated by a column select signal which is produced by decoder circuits (not shown) in response to an address signal.
• Each of the half digit lines in circuit 10 is provided with a pullup circuit that corresponds to pullup circuit 48.
• Pullup circuit 48 includes a transistor 50 which has the source terminal thereof connected to half digit line 18 and the drain terminal thereof connected to a node 52.
• the gate terminal of transistor 50 is connected to receive a PQ signal which is shown in FIGURE 2.
• a transistor 54 has the source terminal thereof connected to node 52 and the drain terminal thereof connected to the +5 volt supply voltage.
• the gate terminal of transistor 54 is connected to receive the
• a transistor 56 has the gate terminal thereof connected to node 52 and the drain terminal thereof connected to receive signal P ⁇ which is
• the source terminal of transistor 56 is connected to the gate terminal of a transistor 58 which has the drain terminal thereof connected to the +5 volt voltage supply.
• the source terminal of transistor 58 is connected to the half digit line 18.
• Each of " the pullup circuits serves to monitor the voltage on the corresponding half digit line and elevate the voltage thereon if it is above a predetermined threshold.
• Circuit 10 comprises an array of digit lines and word lines and a second group of half digit lines are illustrated to indicate the repetitive layout of the circuit.
• Half digit lines 60 and 62 are connected to the inputs of a sense amplifier 64 which is structurally the same as amplifier 24 described above.
• Amplifier 64 includes a latch terminal which is connected to node 34.
• Half digit line 60 is connected through a column select transistor 64 to the input/output line 42 and half digit line ⁇ 62 is connected through a column select transistor 66 to the input/output line 46.
• each of the half digit lines, including 60 and 62 have connected thereto a pullup circuit such as circuit 48 described above.
• FIGURES 2A, 2B and 2C there are illustrated the various control and timing signals which are utilized in the circuit shown in FIGURE 1.
• the signals in FIGURES 2A, 2B and 2C are generated by circuitry not shown herein but widely implemented in the industry for producing these signals.
• FIGURE 1 there is shown a RAS (Row Address Strobe) signal 70, a word line signal 72, a latch signal 74 and an external write signal 76.
• RAS Row Address Strobe
• FIGURE 2B there are illustrated a group of pullup circuit timing signals as heretofore used in semiconductor memory circuits. These include a P signal 78, a P Q signal 80 and a P signal 82.
• FIGURE 2C there are illustrated a group of pull up circuit timing signals as utilized in the method of the present invention. These include a P signal 84, a P signal 86 and a P j signal 88.
• the operation of the semiconductor memory circuit is now described in reference to FIGURES 1, 2A, 2B and 2C.
• a typical read operation for circuit 10 proceeds as follows.
• the RAS signal 70 is externally supplied to the circuit 10 along with a row address.
• the RAS signal 10 causes the row address to be decoded and generate the word line signal 72 which is applied to one of the word lines within the memory circuit 10.
• the word line signal 72 can, for example, be applied to word line 16.
• the access transistor 12a When the word line signal transitions from the 0 to 5.0 volt level, the access transistor 12a will be turned on thereby coupling the storage capacitor 12b to the half digit line 18.
• the half digit lines 18 and 22 have been equilibrated to have very closely the same voltage on the two lines. This is generally about 2.0 volts. If the storage capactior
• the circuit 10 is constrained to operate in such a manner that only one memory cell is read out on a digit line at any one given time. Thus, when a memory cell is being read on half digit line 18, there will be no memory cell read on half digit line 22.
• the latch line signal 74 is applied to the latch node 34 to operate the sense amplifiers for each digit line. Referring to sense amplifier 24, the voltage at the source terminals of transistors 30 and 32 is pulled down at the negative transition of the latch signal 74.
• the immediate following step is the operation of the pull ⁇ up circuit 48 under the control of the signals shown in FIGURE 2B.
• Circuit 48 operates as follows in response to the signals shown in FIGURE 2B.
• transistor 54 Upon receipt of the P signal 78, transistor 54 is turned on to precharge node 52 to a 5.0 volt level. Node 52 is charged to the full supply voltage because the drive signal 78 on the gate terminal of transistor 54 is at a 7.0 volt level, at least one threshold voltage above the 5.0 volt supply.
• the P signal 78 makes a downward transition, it turns off transistor 54 and isolates node 52 with the 5.0 volt charge thereon. Following this action, P Q signal 80 is applied to the gate terminal of transistor 50. If the half digit line 18 is at a voltage of more than approximately 1.0 volts, the transistor 50 will not be turned on due to insufficient gate to source potential. When this occurs, the charge on node 52 is not affected by the signal 80.
• the P- ⁇ signal 82 makes the transition from low to high, transistor 56 is turned on due to both the residual charge left on node 52 and the capacitive coupling of signal 82 into node 52. Node 52 is elevated to approximately 9.0 volts due to the capacitive coupling between the channel of transistor 56 and its gate, node 52.
• the full 7.0 volt potential of signal 82 is applied to the gate terminal of transistor 58. This turns on transistor 58 and connects half digit line 18 to the full 5.0 volt supply voltage. In this manner, line 18 is charged to the full potential of the supply voltage of circuit 10.
• the preferred voltage on a half digit line to cause that line to be pulled to the full supply voltage is in the range of 1.0 to 4.0 volts. If, on the other hand, half digit line 18 were at ground potential after node 52 is precharged to 5.0 volts, transistor 50 will be turned on by the operation of P Q signal 80. When transistor- 50 is turned on, node 52 will be discharged through transistor 50 into line 18. Node 52 will thus be pulled to ground potential.
• the gate terminal of transistor 56 can not be elevated in potential due to capacitive coupling because node 52 is being held at ground. Due to the discharge of node 52 and the lack of capacitive coupling, transistor 56 will not be turned on by the operation of signal 82. Since no voltage is then transmitted to the gate terminal of transistor 58, it likewise will not be turned on and the supply voltage will not be connected to half digit line 18.
• the pullup circuit 48 serves to elevate the voltage on each half digit line if the voltage on that line is above a preset threshold, such as the 1.0 volt threshold described above, and does not affect the half digit line which is previously pulled to ground by operation of the sense amplifiers.
• the pullup timing is that shown in FIGUPE 2B where the half digit line is either elevated to the supply potential or not affected at the time immediate following the operation of the sense amplifier. If the external write signal 76 is not applied to circuit 10, the pullup operation will complete the memory cycle and restore the original charge to the storage capacitors in the memory cells due to the operation of the word line 72 which is elevated to a 7.0 volt level to fully couple the supply voltage or ground voltage as required into the storage capacitors.
• the memory cycle includes the step of writing a new state into the selected memory cell after the read operation has been completed.
• the read operation includes the pullup sequence. If the write operation should require a high voltage state on a half digit line that previously contained a low voltage, some means must be provided for driving the half digit line to a full 5.0 volts in order to have a full supply voltage provided to the selected storage capacitor.
• One method for doing this comprises applying a full supply voltage input signal, such as 5.0 volts, to the input/output lines 42 or 46 while at the same time providing an elevated voltage signal, such as 7.0 volts, to the gate terminal of the column select transistor connected to the desired half digit line.
• the present invention provides a method for resolving this difficulty without the need for additional circuitry or increasing the time period of the memory cycle. This is provided by substituting the timing sequence shown in FIGURE 2C for that shown in FIGURE 2B for the pullup operation. Basically, the pullup operation is delayed until after the external write sequence has been completed.
• the half digit lines are acted upon by the sense amplifiers during the sensing operation and may be subsequently charged to.nominal levels by the input/output circuitry during a write operation. These operations occur before the pullup operation is initiated.
• the pullup operation then charges the half digit lines at or above 2 volts to the full supply voltage.
• the pull up operation simultaneously elevates the voltages due to read operations as well as those due to newly supplied write operations.
• the method of the present invention is described below in reference to FIGURES 1, 2A and 2C.
• the portion of the read operation involving the sense amplifier function is the same as that described above.
• the write operation may occur in which case an input signal on the order of 2.0 or more volts is supplied through the input/output lines 42 or 46.
• This signal is transferred through the column select transistors by driving the gate terminals of these transistors with a 5.0 volt signal.
• an elevated gate terminal voltage on the column select transistors is not needed with the present invention.
• the half digit line connected thereto is charged to at least 2.0 volts if it is desired to store a high level signal in the corresponding memory cell.
• the pullup operation is initiated to elevate the voltages on the half digit lines having an initial voltage above approximately 2.0 volts.
• Each of these half digit lines is pulled up to the full supply voltage by operation of the pullup circuit in the manner described above.
• the circuit 10 then can also be operated in a page mode wherein a plurality of memory cells along a word line are read and/or written during a single extended period of the RAS signal 70. Once a word line has been activated, all of the memory cells along that line will be connected to the respective half digit lines..
• page mode operation has required that a word line, such as line 16, be held at an elevated voltage during each of the column select operations in order to write data into a cell.
• a word line such as line 16
• the process of driving the word line to an elevated voltage above that of the supply voltage can be accomplished for a short period of time but can be extremely difficult if it is necessary to hold the word line at the elevated potential for an extended period of time. If the write operation were carried out in the page mode under the pre-existing technique, it would be necessary to hold the word line at the elevated voltage for an extended period of time.
• the word line need be elevated to the 7.0 volt level for only a short period after the last of the write operations has been completed, as indicated by initiation of the inactive portion of the memory cycle as shown by the positive transition of the RAS input signal, 70. During this very short period, all the access transistors are turned on along a word line and the voltages on the half digit lines are transferred into the storage capacitors.
• a particular advantage with operation of the present invention is the speed at which the incoming data can be transferred into the half digit lines. If the half digit lines must be driven to the 5.0 volt supply level by the input lines, the input lines must be connected to the half digit lines for an extended period of time. This period of time is equal to several time constants for the resistive and capacitive combination of the column select transistor resistance and corresponding half digit line capacitance. But, if the half digit line need only be charged to approximately 2.0 volts still using a 5.0 volt supply, the transfer of data from the input lines to the half digit lines can be carried out in a period of time that is less than one time constant.
• the write operation is made extremely fast since charging the half digit lines to a 2.0 volt level is much faster than charging them to a 5.0 volt level.
• Page mode write operation is speeded up since only the basic step of activating the column select transistor is required for each memory cell, and a single pullup operation is utilized for the whole memory following a complete series of page mode write operations.
• a preferred range of operation for the incoming signals on the input/output lines is in the range of 2 to 4 volts and this voltage is transferred to the half digit lines.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Hardware Design (AREA)
• Dram (AREA)
• Read Only Memory (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (1)

Family

ID=22383603

Family Applications (1)

Country Status (8)

Cited By (1)

Families Citing this family (13)

Citations (4)

Family Cites Families (2)

• 1980
  • 1980-02-06 US US06/119,292 patent/US4291392A/en not_active Expired - Lifetime
  • 1980-05-05 WO PCT/US1980/000506 patent/WO1981002358A1/en active Application Filing
  • 1980-05-05 GB GB8127979A patent/GB2079557B/en not_active Expired
  • 1980-05-05 NL NL8020365A patent/NL8020365A/nl unknown
  • 1980-05-05 DE DE19803050253 patent/DE3050253C2/de not_active Expired
  • 1980-05-05 JP JP55502293A patent/JPH0146951B2/ja not_active Expired
• 1981
  • 1981-02-05 FR FR818102243A patent/FR2475269B1/fr not_active Expired - Lifetime
  • 1981-02-05 CA CA000370160A patent/CA1143838A/en not_active Expired

Patent Citations (4)

Also Published As

Similar Documents

Legal Events