WO1981002074A1 - Procede de fabrication d'un dispositif a semi-conducteurs - Google Patents

Procede de fabrication d'un dispositif a semi-conducteurs Download PDF

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Publication number
WO1981002074A1
WO1981002074A1 PCT/US1980/000508 US8000508W WO8102074A1 WO 1981002074 A1 WO1981002074 A1 WO 1981002074A1 US 8000508 W US8000508 W US 8000508W WO 8102074 A1 WO8102074 A1 WO 8102074A1
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WO
WIPO (PCT)
Prior art keywords
layer
forming
polysilicon
site
element site
Prior art date
Application number
PCT/US1980/000508
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English (en)
Inventor
C Johnson
T Chan
I Young
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Publication of WO1981002074A1 publication Critical patent/WO1981002074A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors

Definitions

  • This invention relates to a method for fabricating a semiconductor device, and more particularly to a capacitor and method for fabricating a capacitor having a high capacitance per unit area to increase packing densities on a semiconductor chip.
  • capacitor type devices for use in integrated circuits.
  • One such application is a switched-capacitor filter for simulatin capacitor and inductor elements in passive ladder filter for use in voice-band systems requiring precision high-order filters.
  • Such capacitors must be fabricated to approximate the operating characteristics of true metal double plate capacitors having low voltage coefficients.
  • the size of capacitors fabricated in semiconductor devices is a critical element in the design .considerations. Therefore, capacitors must have high capacitance per unit area to reduce the area necessary to fabricate such capacitors.
  • Previously developed fabrication techniques for fabricating capacitors have included an N-channel metal gate and CMOS processes in which a diffusion layer formed one plate of the capacitor, a metal layer formed the other plate and silicon dioxide (oxide) formed the dielectric.
  • Another previously developed capacitor fabrication technique using a silicon gate process utilized two levels of polysilicon sandwiched around an oxide layer such that the layers of polysilicon formed the plates of the capacitor and the oxide layer formed the dielectric.
  • the silicon gate process utilizin two levels of polysilicon suffers from the inability to form oxide grown on polysilicon that is low in defect density.
  • the configuration where polysilicon overlaps polysilicon creates poor yields in the fabrication of such capacitors and additionally, the process is more difficult to control.
  • a capacit and fabrication process is provided for fabrication of a capacitor in a semiconductor substrate which substantial eliminates the problems heretofore associated with the fabrication of capacitors including lov; capacitance per unit area and excessive size requirements.
  • a method for fabricating a semiconductor device comprises the ste of f rming an element site on a surface of a semiconduct substrate. The method further includes introducing a dopant in field areas adjacent the element site. A fiel oxide is grown above the field areas. A dopant is diffused into the semiconductor substrate at the element site. An oxide layer is formed over the element site.
  • a layer of polysilicon is then formed to cover a portion of the element site.
  • a layer of oxide is formed over th polysilicon layer and the doped portions of the substrat exposed at the element site.
  • a capacitor is provided.
  • the capacitor is formed on a semiconductor substrate having a surface defining a site for the capacitor.
  • a dopant area is disposed in the substrate immediately below the surface of the site.
  • An insulating layer is disposed on the surface of the substrate above the dopant area.
  • the capacitor of the present invention further includes a layer of polysilicon disposed on the insulating layer.
  • a method for forming a semiconductor device comprises the steps of forming first and second element sites on a surface of a semiconductor substrate. A dopant is implanted in field areas adjacent the element sites. Field oxide is grown above the field areas. A layer of polysilicon is formed to cover a portion of
  • the element formed at the first element site comprises a field-effect transistor and the element formed at the second element site comprises a capacitor.
  • FIGURES 1-24 are schematic sectional views illustrating portions of an integrated circuit device of the present invention at various stages in a process for making the device;
  • FIGURE 25 is an enlarged view of a representative portion of FIGURE 24;
  • FIGURE 26 is an enlarged view similar to the view of FIGURE 25 illustrating a succeeding step in the process.
  • FIGURE 27 is a schematic sectional view illustratin the device of the present invention at a ' final stage in the process.
  • FIGURE 1 there is shown a schematic cross-section of a portion of an integrated circuit device of the present invention, generally identified by the numeral 10, at an early stage in a manufacturing process.
  • the device 10 comprises a substrate-12 which is typically monocrystalline silicon of a conventional crystal orientation known in the art. Many features of the present invention are applicable to devices employing semiconductor materials other than silicon as will be appreciated by those skilled in the art.
  • the substrate 12 may be either P-type or N-type; however, for purposes of this illustrative embodiment, P-type conductivity is employed, a preferred resistivity being about 5 to 25 ohm-cm in the substrate 12.
  • Thermally grown on top surface 14 of the substrate 12 is a thermal oxide layer 16, having a preferred thickness of about 600 Angstroms.
  • the device 10 is then exposed to an oxidizing ambient preferably in steam between about 900°C to
  • the polyoxide layer 22 is about 2000 Angstroms thick, which is about twice the thickness of the original polysilicon top layer 20 due to growth during oxidation.
  • FIGURE 3 representative portions of device 10 are shown after several intermediate steps have been performed. While two distinct component segments or element sites 24 and 26 are explicitly illustrated in FIGURE 3, it is to be understood that they are representative of a great many similar sites (not shown) wherein similar elements are simultaneously produced in accordance with the description of the inventive process which follows.
  • element site 24 a capacitor is fabricated while at element site * 26, a transistor device is fabricated.
  • photoresist patterns 28 and 30 have been deposited on polyoxide layer 22 using standard photomasking technicrues, after which the unmasked portio of polyoxide layer 22 are etched away using an etchant which selectively attacks oxide thereby leaving polyoxid portions 32 and 34 as shown.
  • an ion implant step is performed in a known manner as indicated by the arrows, preferably using boron, to produce P+ regions 36, which penetrate to a depth of about 2000 Angstroms in the portions of the substrate 12 not covered by polyoxide portions 32 and 34, also referred to as the "field area" of the device 10.
  • the energy of the ions is selected so as to penetrate only through the portions of thermal oxi layer 16 and silicon nitride layer 18 not covered by photoresist patterns 28 and 30 and polyoxide portions 32 and 34.
  • An intensity of about 4.0 x 10 J boron ions/cm ⁇ is preferably used in accordance with known techni ⁇ ues a for example, by means of the techni ⁇ ues described in U.S Patent No. 3,898,105, hereinafter cited as Mai et al. It is preferred that P+ regions 36 have a resistivity of about one ohm-cm in the areas of highest impurity concen tration in the final device.
  • the photoresist patterns 28 and 30 are removed and the portions of the silicon nitride layer 18 not covered by the polyoxide portions 32 and 34 are selectively etched away using known techni ⁇ ues, thereby leaving nitride portions 38 and 40.
  • an oxidation is performed in steam for about 6 to 8 hours at approximately 1000°C, which results in the growth of a relatively thick "isoplanar field oxide" layer 42, preferably of about 14,000 Angstroms in thickness, in the portions of the substrate 12 not covered by nitride portions -3 * 8 and 40.
  • the isoplanar field oxide layer 42 penetrates into the substrate 12 to a depth of about 7000 Angstroms, the oxidation process driving the boron implant regions 36 to a greater depth therebelow.
  • the P+ regions 36 permit the use of a thinner isoplanar field oxide layer 42 by reducing the resistivity thereunder.
  • the polyoxide portions 32 and 34 are removed by etching using hydrofluoric acid in a known manner, which also slightly reduces the thickness of the isoplanar field oxide layer 42. Then, the nitride portions 38 and 40 and the remaining portions of thermal oxide layer 16 are removed using conventional techniques. Various surface "cleaning" steps are ordinarily used at this point to remove surface damage in the active area of the device. "Active area” means those portions of the device where no field oxide has been grown. It has been found, however, that merely cleaning by etching some of the substrate 12 along top surface 14 is inadequate to remove silicon nitride contamination which exists along edges 44 of the substrate 12 near the isoplanar field oxide layer 42.
  • nitride from nitride portions 38 and 40 are transported to the top surface 14 at the edges of the isoplanar field oxide layer 42 incident to the chemical process which produces the isoplanar field oxide layer 42. Accordingly, an oxidation step is performed, preferably in an ambient atmosphere of hydrogen chloride and oxygen, to produce oxide layers 46 and 48 as shown in FIGURE 7, thereby gathering the nitride impurities at edges 44 from the substrate 12 into the oxide as it grows.
  • a thickness of about 300 Angstroms is sufficient for oxide layers 46 and 48, with a preferred thickness being between 300 and 1000 Angstroms.
  • FIGURES 7 and 8 are effective to remove surface damage (generally occurring in the top 20 to 30 Angstroms of the substrate 12) as well as the silicon nitride contamination, thereby providing the clean, impurity-free top surface 14 shown in FIGURE 8.
  • the isoplanar field oxi layer 42 is somewhat reduced in thickness.
  • the field oxide has an overall thickness of about 10,000 Angstroms, with about 7000 Angstroms extending to a level below the level of top surface 14 and about 3000 Angstroms extending above the level of top surface 14.
  • thermal oxide layers 50 and 52 are grown to a thickness of about 900 Angstroms as shown in FIGURE 9.
  • a light dose boron ion implantation is then perform using known techniques as indicated by the arrows for purposes of threshold voltage adjustment of the field- effect elements which will be formed subsequently in element sites 24 and 26.
  • a first deposition of polysilicon is deposited to subsequently form the gate of a transistor to be subsequently described fabricated at element site 26.
  • Polysilicon layer 54 is deposited as shown over the entire device 10 to a thickness of about 5000 * Angstroms using known techniques.
  • Polyoxide layer 56 has a preferred thickness of about 1000 Angstroms, the formation of which causes a corresponding reduction in the thickness of polysilicon layer 54 to about 4500 Angstroms.
  • FIGURE 12 illustrates device 10 after masking and etching steps have been performed wherein photoresist pattern 60 is formed, and the portions of polyoxide layer 56 not covered by photoresist pattern 60 are etched away leaving polyoxide portion 64.
  • the photoresist pattern 60 has been removed leaving the polyoxide portion 64 as a mask for etching away portions of polysilicon layer 54.
  • a similar polyoxide mask also exists so that etching produces a plurality of separate poly- silicon layers in the device 10 of which polysilicon layer 68 is representative.
  • Polysilicon layer 68 overlies a center portion of thermal oxide layer 52 in the element site 26 as shown in FIGURE 13.
  • polyoxide portion 64 as a mask for etching the underlying polysilicon layer 54 produces a highly regular layer having a slower, more controllable etch rate.
  • Such properties of polyoxide enable a high degree of mask definition to be carried through from the photo ⁇ resist pattern (layer 60 in FIGURE 12) to the polyoxide portion (layer 64 in FIGURE 13).
  • the high degree of mask definition is further carried through in the formation of polysilicon layer 68.
  • the polysilicon layer 68 will be seen later in the process to further serve as a mask fo etching the underlying thermal oxide layer 52, thereby aligning itself over a channel region of a field-effect transistor.
  • an etch is performed to remove polyoxide portion 64, thermal oxide layer 50 and selective portions of thermal oxide layer 52.
  • Polysili layer 68 serves as a mask for etching thermal oxide lay 52,-leaving a portion 52a of thermal oxide layer 52.
  • an N-type dopant preferably phosphorus
  • thermal oxide layer portion 52a acts as a diffusion mask in producing N+ regions C, S and D in substrate 12, to a depth of about 15,000 Angstroms below top surface 14.
  • an ion implantation technique can be utilized to introduce the dopant into substrate 12 at element site 24 to produce region C.
  • the N-type dopant also dopes polysilicon layer 68 to become highly conductive.
  • the C region forms a first capacitor plate of the present capacitor fabricated at element site 24.
  • the D region forms the drain and the S region forms the source of the transistor device fabricated at element si 26.
  • an alternate embodiment using an N-type substrat a P-type diffusion, typically using boron, would be performed at this stage to produce the complementary conductivity-type structure of that shown herein.
  • Thermal oxide layer portion 52a remains at a thickness of about 900 Angstrom while uncovered thermal oxide portions 70 and 72 increas in thickness to about 200 to 500. ngstroms.
  • Thermal oxi portion 70 forms the capacitor dielectric for the capacitor fabricated in accordance with the present invention at element site 24.
  • thermal oxide portion 70 forms a dielectric that has a high capacitance per unit area to permit the present capacitor to be fabricated in a smaller area resulting in greater packing densities.
  • a new polysilicon layer 74 constituting a second deposition of polysilicon is now deposited over the device 10 as shown in FIGURE 16 using known deposition techniques in similar fashion to the deposition step of FIGURE 10.
  • the polysilicon layer 74 has a preferred thickness of about 4000 Angstroms.
  • an oxidation of polysilicon layer 74 is performed to produce a polyoxide layer 76 having a thickness of about 1000 Angstroms as shown in FIGURE 17.
  • the oxidation reduces polysilicon layer 74 to a thickness of about 3500 Angstroms.
  • the device 10 is shown after a photoresist pattern 78 has been used to mask polyoxide layer 76, which is etched away entirely at element site 26 and partially at element site 24.
  • the remaining polyoxide layer 76 overlies both a lower portion 80 and an upper portion 82 of polysilicon layer 74 at element site 24.
  • the photoresist pattern 78 has been rem.oved and the remaining polyoxide layer 76 has been used as a mask to etch polysilicon layer 74, thereby removing polysilicon layer 74 entirely from element site 26 and partially from element site 24 to produce the structure shov/n such that the remaining portion of polysilicon layer 74 forms the second plate of the capacitor fabricated using the present process.
  • the term "undoped” means "essentiall free of conductivity affecting impurities" such as phosphorus (N-type), boron (P-type) and their known functional equivalents.
  • polysilicon layer 74 enables capacitive elements of the type shown in element site 24 to be arranged in a dense manner in device 10.
  • the isoplanar field oxide layer 42 with polysilicon laye 74 interconnections between adjacent cells (not shown) are facilitated, and the formation of contacts in subsequent steps is not a limiting factor in choosing th amount of active top surface area 14 allocated to elemen site 24.
  • an etch is performed which selectively removes a portion of thermal oxide portion 7 to expose a portion of top surface 14 in the area of element site 24 not covered by polysilicon layer 74 and removes thermal oxide, portion 72 to expose portions of t surface 14 in the area of element site 26 not covered by polysilicon layer 68. Thereafter, phosphorus is diffuse into the top of polysilicon layer 74, as indicated by th stippling, which causes polysilicon layer 74 to be heavi doped N-type and thus highly conductive. In an alterna ⁇ tive embodiment using an N-type substrate, a P-type diffusion, typically using boron, would be performed at this stage to produce the complementary conductivity-typ structure of that shown herein.
  • the device 10 is placed in a furnace with dry oxygen or steam at about 90 °C to 1000°C so that oxide layers of about 2000 Angstroms are grown over the various polysilicon layers 68 and 74 as indicated by numerals 94, and over the various N+ region C, S and D in the substrate 12 as indicated by numerals 96.
  • an oxide layer 98 of "high temperature" undoped oxide is deposited, preferably using SiH 4 and C0 2 in a known manner, at a temperature between 600°C and 1000°C to a thickness of preferably about 6000 Angstroms.
  • a photoresist ma-si: 100 is then formed over deposited oxide layer 98.
  • contact windows 102 are opened by etching through the portions of oxide layer 98 not covered by photoresist mask 100, and continuing to etch down through the underlying polyoxide layer 94 and thermal oxide layer 96.
  • the photoresist mask 100 is removed, and a stabilization step is performed, preferably using a phosphorus diffusion, as indicated by the stippling along the exposed oxide surfaces.
  • a stabilization step is performed, preferably using a phosphorus diffusion, as indicated by the stippling along the exposed oxide surfaces.
  • the phosphorus stabilization has the effect of producing very thin oxide layers 104 on exposed silicon surfaces (explicitly shown by way of example in FIGURE 25) which are approximately 20 to 100 Angstroms thick.
  • stabilization it is convenient to getter the device 10 concurrently with stabilization, which may be achieved by covering all but the backside, the. bottom surface of the substrate 12 with oxide thereon (not shown) , v/ith photoresist after opening contact windows 102, then stripping the backside down to clean silicon. • Stabilization then proceeds as described in the preceding paragraph by removing the photoresist and exposing the device 10 to a phosphorus diffusion, which getters metallic impurities to the backside, thereby favorably reducing leakage current. After the phosphorus stabilization step, it is necessary to reopen contact windows 102 through oxide layers 104. A photoresist layer (not shown) is reapplied, using the same mask registration which produced photo- resist mask 100.
  • oxide layers 104 are etched through to the underlying silicon to reopen the contact windows 102, and the photoresist is removed to produce contact windows 102, typically illustrated by FIGURE 26.
  • the contact window opening 102 at top surface 14, shown in FIGURE 26, may be controlled to less than 5 microns in diameter.
  • a metallization process is used to form contacts 106, 108, 110, 112 and 114 in the contact windo 102 which yields the device structure 10 shown in FIGURE 27.
  • the contacts are preferably formed by vacuum deposition of aluminum, photomasking portions of the aluminum, and etching the unmasked portions with etchant which selectively attack the aluminum but not the under ⁇ lying oxide layer 98.
  • element site 24 serves as a capacitor and the element si 26 serves as a field-effect transistor.
  • element site 26 is an N-channel enhancement mode FET having a self-aligned silicon gate similar to that which is described in Mai et al., cited above, wherein contact 112 serves as a gate, contacting polysilicon layer 68 and contacts 110 and 114 contact regions S and D forming the source and drain of the FET.
  • the present invention may also be applied to make N-channel depletion mode FET as well as both modes of P-channel FETs by modification of the process steps specifically recited herein in accordance with the teachings of Mai et al.
  • Element site 24 is a capacitor wherein contact 106 serves as a top plate contact to polysilicon layer 74 and contact 108 serves as a bottom plate contact to diffused region C.
  • the operation of a capacitor such as the capacitor fabricated at element site 24 of FIGURE 28 is known in the art.
  • a capacitor is formed by thermal oxide portion 70 serving as a dielectric between the polysilicon layer 74 and N+ regio C.
  • the present process o manufacturing a low voltage coefficient capacitor in a semiconductor substrate provides for a capacitor having a high capacitance per unit area while simultaneously requiring a small area for fabrication.
  • the method of the present invention involves a process of minimal complexity to result in high yields in fabrication of the capacitor of the present invention. Since the dielectric element of the capacitor is fabricated directly on the semiconductor substrate and not on a layer of polysilicon, the dielectric layer is of good ⁇ uality and uniform in structure, such that a thinner dielectric layer can be utilized than with previously developed capacitor fabrication techniques to thereby achieve a capacitor having increased capacitance per unit area fabricated using the present invention.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Un procede de formation d'un dispositif a semi-conducteurs (10) comprend les etapes de formation d'un site a elements (24) sur une surface (14) d'un substrat a semi-conducteurs (12). Un dopant est introduit dans le substrat a semi-conducteurs (12) sur le site d'elements (24) pour former une region (C). Une couche d'oxyde (70) est formee sur le site d'elements (24). Une couche de polysilicium (74) est formee sur une partie du site d'elements (24). Une couche d'oxyde (98) est formee sur la couche de polysilicium (74) et la partie dopee (C) du substrat (12) expose au site d'elements (24).
PCT/US1980/000508 1980-01-11 1980-05-05 Procede de fabrication d'un dispositif a semi-conducteurs WO1981002074A1 (fr)

Applications Claiming Priority (2)

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US11127580A 1980-01-11 1980-01-11
US111275 1980-01-11

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WO1981002074A1 true WO1981002074A1 (fr) 1981-07-23

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2268829A (en) * 1992-07-06 1994-01-19 Ericsson Telefon Ab L M Mos capacitor

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3773566A (en) * 1970-02-09 1973-11-20 Hitachi Ltd Method for fabricating semiconductor device having semiconductor circuit element in isolated semiconductor region
US3899363A (en) * 1974-06-28 1975-08-12 Ibm Method and device for reducing sidewall conduction in recessed oxide pet arrays
US4167018A (en) * 1976-02-25 1979-09-04 Hitachi, Ltd. MIS capacitance element
JPS54136279A (en) * 1978-04-14 1979-10-23 Nec Corp Semiconductor device
US4182636A (en) * 1978-06-30 1980-01-08 International Business Machines Corporation Method of fabricating self-aligned contact vias
US4183040A (en) * 1976-02-09 1980-01-08 International Business Machines Corporation MOS RAM with implant forming peripheral depletion MOSFET channels and capacitor bottom electrodes

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3773566A (en) * 1970-02-09 1973-11-20 Hitachi Ltd Method for fabricating semiconductor device having semiconductor circuit element in isolated semiconductor region
US3899363A (en) * 1974-06-28 1975-08-12 Ibm Method and device for reducing sidewall conduction in recessed oxide pet arrays
US4183040A (en) * 1976-02-09 1980-01-08 International Business Machines Corporation MOS RAM with implant forming peripheral depletion MOSFET channels and capacitor bottom electrodes
US4167018A (en) * 1976-02-25 1979-09-04 Hitachi, Ltd. MIS capacitance element
JPS54136279A (en) * 1978-04-14 1979-10-23 Nec Corp Semiconductor device
US4182636A (en) * 1978-06-30 1980-01-08 International Business Machines Corporation Method of fabricating self-aligned contact vias

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2268829A (en) * 1992-07-06 1994-01-19 Ericsson Telefon Ab L M Mos capacitor
GB2268829B (en) * 1992-07-06 1995-02-01 Ericsson Telefon Ab L M Capacitor

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Publication number Publication date
EP0043372A1 (fr) 1982-01-13
CA1164107A (fr) 1984-03-20

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