WO1980002898A1

WO1980002898A1 - Digital to analogue converter

Info

Publication number: WO1980002898A1
Application number: PCT/JP1979/000149
Authority: WO
Inventors: Y Mitsuhashi
Original assignee: Y Mitsuhashi
Priority date: 1979-06-12
Filing date: 1979-06-12
Publication date: 1980-12-24
Also published as: DE2953702A1

Abstract

There are used a time axis D-A converter for converting digital inputs into corresponding pulse widths and an amplitude axis D-A converter for converting the digital inputs into corresponding amplitudes. Higher bits of the digital input signals may be converted at the time axis D-A converter, and the converted output and the remaining lower bits of the digital inputs may be converted at the amplitude axis converter. It will be possible to determine both the conversion velocity and precision of conversion by individually allotting the number of conversion bits to the time axis D-A converter and to the amplitude axis D-A converter respectively in accordance with purposes and uses.

Description

Clear

Invention title

D-A converter technical field

The present invention relates to a D-A converter that converts a digital signal into an analog signal.

Background technology

Conventionally, D-A converters are, for example, amplitude-axis type D-A converters such as ladder type D-A converters, and, for example, ^zero- width modulation type D-A converters. A time-based D-A converter is used. The ladder type D-A converter has a high conversion speed, but the device itself is very expensive. Conventional D-A converters of this kind meet a wide range of κ · requirements and are therefore used in various applications.

However, when the ladder type D-A converter is used in a limited number of cases, the performance of the device may exceed the required value. This is the case, for example, when handling signals in a relatively narrow local frequency band such as voice. Of course, when processing multiple audio signals at the same time, it is possible to reduce the redundancy by using a D-A converter with a fast conversion speed by time-division multiplexing. R. However, in the time-division multiplex system, signal leakage between adjacent channels is a problem, so an expensive sample termination hall is used for each channel. There are few cases where a drive circuit is required. When using a D-A converter in the field of signal processing, particularly in the field of electronic musical instruments integrated into semiconductor circuits that rely on the digital and digital methods, a commercially available expensive D-A converter is externally connected. It is not a wise way to use it. So usually, D - de A converter I, the structure was sealed in with Selector Selector Le circuit LS I c ⁰ Tsu Ke one di also of is used. Almost all D-A converters used there are resistors, and they are voltage-dividing type that utilize the fact that they divide the voltage. This resistance division type: D-A converter is excellent in that the converted output is monotonically increasing, but it is about 8 bits (the minimum number of bits required to generate a musical waveform). When I try to make a D-A converter in J.), the J? Therefore, the D-A converter occupies most of the LSI package, and there is a difficulty in manufacturing the device.

Disclosure of the invention

The purpose of this invention is to provide a D-A converter that can be made compact.

Another object of the present invention is to provide a D-A converter which is effective even when processing signals of a multiculturalism.

Still another object of the present invention is to provide a D-A converter with high conversion speed.

Still another object of the present invention is to provide a D-A converter capable of controlling conversion speed and conversion accuracy according to the purpose of use and the purpose of use and enabling efficient conversion. ..

According to this invention, the digital input is adapted to the value.

, ΟΜΗ W1PO A time-axis DA converter that converts the pulse width to a pulse width and an amplitude-axis DA converter that converts the digital input to an amplitude corresponding to the value are used. For example, the upper bit of the digital input signal is converted by the time axis type DA converter, and the converted output and the remaining lower bits of the digital input signal are the amplitude axis. Converted by type DA converter.

If the number of required conversion clocks does not match the number of clocks of the conversion cycle of the time-base DA converter, the required number of conversion clocks and the digital input signal And are multiplied by a multiplier, the upper bits of the multiplication calculation power are supplied to the time axis type DA conversion unit, and the converted output and the lower bits of the remainder of the multiplication calculation power]? It is supplied to the above-mentioned amplitude axis type DA converter.

Brief description of the drawings

Figure 1 shows a ladder type D-A converter and a resistance voltage division type

Figure 2 shows the relationship between the output of the D-A converter and the input and output of the digital input. Fig. 3 shows the relationship between the input and output voltage of the pulse width modulation type D-A converter digital circuit. Figure 4 shows the relationship between the digital input and output voltage of the D-A converter due to the combination of the pulse width modulation type and the ladder type (or resistance voltage division type). C of the D-A converter of the embodiment of the invention of FIG. Fig. 5 is a diagram showing a portion corresponding to the pulse width modulation type, and Fig. 5 is a diagram showing ^ minutes of a resistance voltage division type decoder of the D-A converter of the embodiment of the invention, Fig. 6 Is a resistance voltage division type DA converter analog switch and resistance voltage division.

_Ο ΡΙ W WIIPPOO -.V Fig. 7 (a) to (ti) is a circuit diagram showing the portion, and Fig. 8 is a diagram showing the relationship between the digital input and the output voltage level of the D-A converter of the embodiment of the present invention. The figure shows the time transition diagram of each signal and output voltage level corresponding to the digital input "00 1 0000 1", and Fig. 9 shows the case where the number of clocks required for conversion is not a power of 2. Conversion output diagram, FIG. 10 is a diagram showing the configuration of the multiplier according to the embodiment of the present invention, FIG. 11 is a circuit diagram for obtaining the conversion output of FIG. 9, and FIG. 12 is a conversion required clock. The conversion output diagram obtained when D-A conversion is performed for each section by dividing the number of clips, and Fig. 13 shows the circuit diagram for obtaining the conversion output of Fig. 12 and Fig. 14 The figure shows the conversion output diagram obtained when the unit area to be formed is filled along the amplitude axis, and Fig. 15 shows the circuit of another embodiment of the invention for obtaining the conversion output of Fig. 14. Fig. 16 is a diagram showing the structure of a decoder used in another embodiment of the present invention, and Fig. 17 is a diagram showing the number of clocks required for conversion divided into D-A for each segment. The conversion output diagram obtained when conversion is performed, and Fig. 18 is a circuit diagram for obtaining the conversion output of Fig. 17.

BEST MODE FOR CARRYING OUT THE INVENTION

No.! ~ Figures 3 show the explanatory diagrams of the functions of various D-A converters. ' Figure 1 shows the relationship between the digital input I d and the output voltage V of the ladder type D – A converter or the voltage dividing type D – A converter using a resistor. This type of D-A converter directly converts digital quantities into amplitude values (voltage), so the principle is simple and presently available on the market.

O PI

WIPO _ ^ Most of the D-A converters on the market are of this kind © oo

On the other hand, the c shown in Fig. 2 is used. The pulse width modulation type D-A converter does not directly convert the digital amount I d into the amplitude value, but keeps the width value constant and changes the digital amount. C along the time axis. Convert proportionally to the width of the rule. By smoothing the converted output with a low-pass filter? , Which is equivalent to the ladder type D-A converter is obtained.

The characteristic of these two types of D-A converters is that the ladder type obtains an amount proportional to the amount of data in the amplitude axis direction. The pulse width modulation type obtains an amount proportional to the amount of digital in the time axis direction. As is clear from Figs. 1 and 2, for the same digital input, the conversion amounts have equal areas in the two-dimensional space of the time axis and the width axis. There is. -.-Fig. 3 shows the relationship between the digital input and output (voltage) of the D-… A converter according to the present invention. In the conventional D-A converter shown in Figs. 1 and 2, either the amplitude axis or the time axis shift is quantized, while the one shown in Fig. 3 does not. , Let's say that the'both sides' of the amplitude axis and the time axis are changed. In this case, the conversion area occupied by the two-dimensional domain whose time axis is the amplitude axis is equal to the area _ of the corresponding digital input in Figures 1 and 2. Therefore, by smoothing this with a low-pass filter, [9] and the equivalent D of those in Figs. 1 and 2 -A converter is obtained.

Here, in order to further illustrate the features of the D-A converter according to the present invention, a ladder type D-A converter, a resistance voltage division type D-A converter, and a c. The advantages and disadvantages of the pulse width modulation type D-A converter will be explained in some detail.

The advantage of the ladder type D-A converter is that its conversion speed is fast. That is, the conversion speed is usually 1 MHz at the slowest, and the conversion time is 1 sec. However, this advantage may lead to redundancy in some cases. For example, when handling audio signals such as musical tones and voices containing frequency components of 15 kHz or less in a digital manner, use the sampling theorem]? The processing speed of the sample value is 2X15 kHz = 30 kiiz. Therefore, the D-A conversion should be performed with the same 30 kHz conversion mode. In this usage state, the redundancy reaches 1 MHz Z30 kHz Φ 30. Of course, if there are multiple audio signals to handle, the time division multiplexing method should be used! ? However, it is possible to reduce the redundancy, but in this case, since multiple channels are handled in a time-sharing manner, signal leakage between adjacent channels poses a problem.] ?, In order to solve this, a samp for each channel. A rule-and-hold circuit is required.

Other disadvantages of this type of D-A converter are firstly that the manufacturing cost is high, and secondly that MOS (Metal Oxide) is used.

Semiconductor) hSI (Large Scale Integrated

OMPI For devices that are suitable for circuit :), it is difficult to manufacture because the size of the resistors and the characteristics of the switches used for the ladder are small. Recently, the signal processing circuit has tended to move in the direction of the LSI circuit.] 9 D-A converter can be installed in the same package as the logic circuit. Since it directly affects the manufacturing cost of the system used, whether or not LSI can be implemented is an important issue.

The advantage of the resistance-voltage division type D-A converter is that, firstly, when the number of bits of the digital input is small, the door becomes very simple. It is a point that can be made with MOS. On the other hand, the disadvantage is that when the number of bits of the digital input exceeds 1 bit, the hardware is almost doubled, so the minimum required 8-bit -A converter is usually required. It is quite difficult to manufacture.

Ha. The advantages of the pulse width modulation type D-A converter are firstly that the manufacturing cost is low, and secondly because it can be manufactured by using MOS. ° It can be installed in the package. The disadvantage is that the output changes in the direction of the time axis, so that the conversion speed decreases by the power of 2 when the number of bits of the digital input increases. For example, 8 bit ha. A pulse width modulation type D-A converter has a force that takes 2 ⁸ = 2 5 6 types of widths in the time axis direction; the operating clock of the D-A converter is 1 MHz. Then, the time required for conversion is 2 5 6 X 1 M sec = 2 5 6 ； ”sec. The frequency of this conversion is from ~ 4 kHz, and the audio signal that can be handled is up to 2 kHz. Therefore, to handle the audio signal up to 15 kHz, 7.5 It is necessary to operate at a clock of MHz S.], and it is possible to operate at such a high speed with a TTL (Transistor-Transistor Logic :) circuit, but it is not possible with an M0S circuit. Therefore, it can be embedded in MOS-LSI.To handle signals up to 15 kHz, the conversion speed of the D-A converter requires 30 kHz. If this is converted into a conversion time, it will be approximately 33 seconds, so if a 1-MHz operation clock is used, a 5-bit D-A converter (conversion time of 32 seconds) will be used. It can be realized with a pulse width modulation type.

The D-A converter of this invention retains the advantages of the conventional type, and removes its disadvantages]). In the D-A converter of the present invention, both the amplitude axis and the time axis are converted according to the input digital signal.) Expand to. A ladder type D-A converter or a resistance voltage division type D-A converter is used for the conversion of the amplitude axis. Use a pulse width modulation type D-A converter. The example shown in Fig. 3 uses two bits for the former and two bits for the latter, and shows the conversion operation of an effective 4-bit D-A converter.

Next, the specific configuration of the D-A converter according to the present invention will be explained. Reveal Figure 4 shows the portion corresponding to the pulse width modulation type D-A conversion section as the time axis type D-A conversion section.Figures 5 and 6 show the amplitude axis type D-A conversion section, respectively. This is a part corresponding to a resistance voltage division type D-A converter as a converter.

Of course, the circuits in Fig. 5 and Fig. 6 can be replaced by a ladder type D-A converter.

In the D-A converter of this embodiment, the portion of the pulse width modulation type D--A converter is 5 bits, and the portion of the resistance voltage division type D--A converter is (3 + X,) (This t is in the direction of the amplitude axis.

It is intended to give 9 levels of resolution, but will be omitted hereafter to avoid complications), and a total of 8 bits of digital input are converted. In this example, it is assumed that the clock operates at 1 MHz. Although it is not necessarily 1 MHz, this operation speed was selected on the assumption that MOS-LS I conversion can be easily realized.

Ha. Since the pulse width modulation type D-A conversion unit has 5 bits, the number of conversion quantization in the time axis direction, that is, the number of clocks within the maximum output width is 2 ⁵ = 3 2. , Conversion time is 3 2

sec.

The digital input of the D-A converter of this embodiment (AM (0,…, 7) and AM 0 in Fig. 4 are the highest bits) and the output voltage level (Fig. ⁶⁾ . The relationship of output terminals ₇ )) is as shown in Fig. 7 (a) to (u). In this D-A converter, an 8-bit digital input (S i gn

Magn i tu de), treat it as

OMPI

/ IPO-, The sign is a sign 'bit, and a value of "0" represents a positive number, and a value of "1" represents a negative number. It is assumed that the 7 bits of the remaining [?] Following the sign bit are absolute values indicating the magnitude] ?, and that there is a decimal point immediately after the sign bit. So, for example, "0 0 0 0 0 1 0 1" (the leftmost sign is the sign bit) means +5/128. , Fig. 7 (~ (u) shows the output according to the time axis when the digital input sign bit is "0"]? Upper part, "1" means lower part And the absolute value is multiplied by 4 X 3 2 = 1 2 8 to form the number of unit areas corresponding to the number obtained on the plane of the time axis-amplitude axis. It is the maximum number of unit areas that occupy the top or bottom.For example, the digital input in Fig. 7 (ί) is "0 00 0 0 1 01" and the top bit is "0". , And the unit area number of _'is 5 × 128 × 128 = 5, so as shown in the figure, it occupies an area of 5 units in the positive direction (upward). Then, the digital input in Fig. 7 (q) is "1 0 0 0 1 0 0 1", the sign bit is "1" and it is a negative number, and the unit area number is 9 Since / 128 X 128 = 9, the area occupies 9 units in the negative direction (downward) as shown in the figure.

The individual components of the embodiment of the D-A converter of the present invention shown in FIGS. 4 to 6 will be described below. First of all, the five-pitched binary thruster 1 shown in Fig. 4 is c. 32 width masters required for the pulse width modulation plastic D-A converter, one clock MCLK each time it is counted. Outputs the shift key to the RC terminal. This ripple'carrier signal is used to timing the start of the D-A conversion operation, i.e. used to determine the i? Conversion period, and the NAND circuit. 4-2 to set the flip-flop 4 degrees, and at the same time set the upper 5 bits of the absolute value of the digital input signal to 5 bits AM (1, ..., 5). Load the binary counter 1 of the In this case, the 1-complement is loaded by using the -3-1, 3 -2-3 -5.

The ripple 'carry LSD of the counter 2 is 1 clock obtained by counting the number of terminals by the number of terminals based on the loaded digital input signal. With a signal that is only "1" for this minute, do you want to reset this?] 'Flip' Flop 4. Therefore, the output MSD of the flip-flop 4 will be rippled from the RC terminal force of the counter 2 after the data is loaded onto the counter 2. Hold the "1" level until the carrier LSD appears. The number of clocks included in this "1" level is the unit area formed corresponding to the digital input signal, as is clear from Fig. 7. Equivalent to the quotient of dividing the number by 4. This is also the 7-bit portion that corresponds to the absolute value of the digital input signal.

It can be argued that AM (1,…, 7) is regarded as an integer and is equivalent to the quotient obtained by dividing it by 4. The output MSD available at the Q terminal of flip'flop 4 is used to D-A convert the upper bits of the digital input signal, and the count of one OMH / ,,, IPO The output LSD available at the RC pin of the data register 2 is used to D-A convert the lower bits. In this specification, the signal marked with * indicates the negation of the original signal.

. *

Since, for example, MCLK = MCLK is displayed. AM0, AM6 and AM7 are used as MSB, SLSB and LSB, respectively. Thus, the MSD, LSD, MSB, SLSB and LSB obtained in the circuit of Fig. 4 are the input signals to the decoder 1 of Fig. 5, respectively.

Figure 5 shows a part of the decoder of the resistance voltage division type D-A converter. This decoder is given the input of the circuit shown in Fig. 4]? MSB, SLSB, LSB, MSD and LSD, and only one of the output terminals D 0 to D 8 is input. The logical value of the signal is configured as "1"; T depending on the way of giving. This decoder circuit consists of an amplifier, a data block N-1, N-2 ... N-5, an analog gate A-1, A-2-A -13 and an analog gate 0-1. The logical expression of the output is as follows o

(1)

C? I D 7 = LSD · SLSB · LSB · MSB

D 8 = MSD · MSB

Figure 6 shows the analog switch and resistance part of the resistance-voltage division type D-A conversion part. In this circuit, the output terminals D 0 to D 8 of the decoder shown in Fig. 5 are connected to the input terminals as they are. As described above, only one of these input terminals D 0 to D 8 corresponds to the digital input signal, and the logical value of that signal becomes "1". Select only one of the corresponding switch groups 5 -1, 5 -2 ... 5-9 and turn it "ON". Analog 'Switch group 5-1, 5 -2…

One of the terminals 5-9 is connected in common to derive the output terminal 7, and the other terminal has a series resistance 6-1, 6 -2 ...

It is connected to 6-8 adjacent resistor connection points, and the divided voltage corresponding to each position is obtained. Therefore, if the decoder of Fig. 5—one output MSB, MSD, LSD, SLSB and LSB is applied to the input of the circuit shown in FIG. The corresponding analog switch will be conducted and the corresponding voltage will be available at output terminal 7. The above operation will be specifically described with an example.

For example, when the digital input signal is "0 01 0 0 00 1" (bit left ifi AM0), the relationship between the output voltage and time is as follows. The data of 5 bits written to the counter 2 in Fig. 4 is AMI = "0", AM 2 =

It is the one's complement of "1", AM3 = "0", AM4 = "0", AM5 = "0" * (EDCBA) = "1 0 1 1 1". Thus power

O PI _ · πο Riff from the RC terminal of Unit-1 2. The number of clocks until the rury LSD comes out is 8 from (EDCBA) to "1 1 1 1 1" to "1 1 1 1 1". That is, the data is exported to the counter 1, and the state of MSD = "1" is maintained for 8 clocks. Then LSD becomes "1" for one clock. In this state, (EDCBA)

It becomes "0 00 0 0". In this case, MSB = AM0 = "0", SLSB = AM6 = "0" and LSB = reference = "1"] ?, and the output of the decoder that inputs these is as follows. That is, according to the above equation (1)]) When MSD = "1" and D8 = "1", and 8 clocks, 1 V is output from terminal 7 in Fig. 6. , Next, when LSD is "1", AM6 = "0" and AM7 = «1" are decoded and D5 = "1" is output from J9 terminal 7! "V is output and MSD =" 0 ". When LSD is 0 and is D 4 = "1"]? If each output value of the decoder is determined in this way, the voltage level of output terminal 7 of the circuit in Fig. 6 is also determined. The interrelationship of the above values is shown in Fig. 8.

In the examples given above, the quantification number in the time axis direction was considered to be a power of 2. Ha if you choose this. It is convenient in correspondence with the number of bits of the pulse width modulation type D-A converter. In the above embodiment, the number of quantizations in the time axis direction is ²⁵ = 3 2 j ?, which means that when the amount of digital data undergoing D-A conversion is input every 3 2 clocks. Can be applied as is, but otherwise it is applicable

-REACT

OMPI

0-, I can't do it. In this case, perform the correction operation as described below.

If this correction operation is performed, the digital input signal that undergoes D-A conversion can be applied to an arbitrary number of clock intervals, in which case the number of clocks will be different for each input. It can be anything that changes. Here, as an example, we will explain the case where 1 4 2 is given as the number of clocks required for conversion. Thus, if the number of clocks required for conversion is relatively large, the accuracy of D-A conversion can be improved. In this case, since 1 42 X 4 = 5 6 8 unit areas can be formed above and below the time axis, respectively, the accuracy can be set to about 10 bits. For example, if the digital input signal is "0 1 0 0 0 1 1 1 0 0", the sign bit (leftmost bit); ^ "0" is a positive number. [5] The number of unit areas to be formed in the upward direction of the time axis is as shown in Eq. (2).

If the digital input signal "0 1 0 0 0 1 1 1 0 0" is expressed as shown in equation (2), the maximum amplitude value of "4" is 7 8 and then the amplitude is shown. If one of the values "3" is formed two-dimensionally, the D-A transformation output as shown in Fig. 9 can be obtained.

An example of a circuit for obtaining such a D-A conversion output is shown in FIGS. 10 and 11. As shown in Fig. 11 It ’s Ha. This is the portion corresponding to the pulse width modulation type D-A conversion section]), and the one shown in Fig. 10 is a circuit diagram showing the configuration of the multiplier used in the circuit shown in Fig. 11 1. . In this case, the one equivalent to the resistance voltage division type D-A converter can be used as it is as shown in Figs. 5 and 6.

The multiplier shown in Fig. 10 is a typical shift-and-add type (Shift and Add) type. In this case, the multiplicand is a positive fraction B (1, ..., 9) with 9 bits after the decimal point, and the multiplier is a positive integer A (0, ..., 7) with 8 bits. The number P (0,…, 9 :) obtained at the output end of the latch circuit 2 1 as a result of multiplication is 10 bits, and the upper 8 bits are the integer part]) The lower 2 bits are The fractional part is displayed. In this case, the multiplication factor is 8 bits, so the shift-and-add operation is performed 8 steps (8 times).] The multiplication is completed. Become . This multiplier employs serial type operation and adds "0" to the most significant bit of the multiplicand, so it is possible to add 10 bits to each addition (multiplier driving the multiplier). It is necessary to have 10 master clocks (MCLK).

The 4-bit binary counter 8 in Fig. 10 has a mouth at MCD rising edge 9 when AB CD = "01 1 0" ETCK = "1". It forms a 10-ary counter with the NAD circuit 9 and outputs a ripple carrier CRY 1 to its RC terminal every 10 bits' time. This Lip One OMPI IPO One shift and add operation is performed in synchronization with the rule carrier CRY 1. The first step is until the first ripple 'carrier CRY 1 comes out, and then the second ripple' carrier until the second ripple 'carrier comes out. Let's call it ・・・,.

The multiplication in this case starts in synchronization with the ETCK signal. This ETCK signal Ru Ha ⁰ le scan signal der to be out at the beginning of each stearyl class tap of the above-mentioned. As described above, the power pointer 8 loads the data AB CD = "0 1 1 0" at the rising edge of the clock MCLK when the ETCK signal is "1". The counter 10 is a 3-bit binary counter] 9 Cleared by the ETCKT signal, and the counter 8 ripple carrier CRY 1 When 7 are counted, the ripple 'carry CRY 2 is output in synchronization with the 8th CRY 1. In other words, the logical value of the ripple 'carry CRY 2 becomes "1" in the last 1 clock of the 8th ~ step. The output of the NOR circuit 1 2 is such that when the ETCK = "1" and the logic value of the ripple carrier of the counter 8 is "1" every 10 bit 'time. Then, it is a signal with a logic value "0"]) 0 R It is input to the circuit 1 3. 0 The output of the R circuit 1 3 has a logical value "0" in synchronization with the master clock-MCLK when the logical value of the ETCK signal or the ripple carrier CRY 1 is "1". It is a signal that becomes "1" from force. This signal is used as the clock of the 8-bit shift register 1-14. Therefore, the shift register 1 4 first uses the ET CK signal for the multiplier A (0,…, 7). 1

Will be loaded, and one bit will be shifted at the end of the calculation of each step.

On the other hand, the multiplicand B (1, ..., 9) is set to shift register 15 at the rising edge of the master clock MCLK when ETCK signal = "1". Will be At this time, the highest bit of the shift register 15 is simultaneously loaded with "0". Since the output terminal S 0 of the shift register 1 15 is fed back to the input terminal SI, the shift register 1 1 is returned every time the master clock MCLK comes thereafter. 5 becomes a cyclic shift with a cycle of 10 bit '. The signal at the output terminal S 0 of the shift register 15 is the signal at the output SO terminal of the shift register 1 4 for each step, and the AND circuit 1 6 is used. It is controlled by using. This output is used as input to a cumulative adder consisting of a flip-flop 17 and an adder 18 and a 10-bit shift register 19. Given . Therefore, partial sums are generated for each step in the shift register 1-19. This partial sum is output back from the 9th bit, so the partial sum is effectively shifted 1 bit to the right. As a result of this shift, the lowest bit of the previous step is fed back to the 10th pit time, so this input is connected to the AND circuit 20 0. Prohibit with. When this shift and add operation is performed eight times, the multiplication is completed and the output data is latched to the latch circuit 2 1. This latch operation is performed by the ripple key CRY 2 of the counter 10.

O PI

, / WiPo " Fly: 7 ° 'Float: 7. It is performed at the falling edge of the signal delayed by 1 bit time with 2 2. The output P (0,…, 9) of the latch circuit 2 1 is interpreted as the upper 8 bits being an integer and the lower 2 bits being a decimal.

Figure 11 shows the D-A converter c to obtain the converted output shown in Figure 9. FIG. 3 is a circuit diagram of a portion corresponding to a loose width modulation type D-A conversion unit. The multiplier shown in Fig. 10 is used as the multiplier in this figure. Further, as the resistance voltage division type D-A converter, it is possible to use the one shown in Figs. 5 and 6. Here, generally, the number of clocks required for conversion is X (0,…, 7) and the absolute value of the digital input signal that receives the conversion is AM (1,…, 9). The output P (0,… 9) of the latch circuit 2 1 of the multiplier 3 1 is inverted and loaded by the 8-bit counter 33 and the output of the counter 3 1 2. R.

According to the output P (0,-, 9) of this loaded latch circuit, the master clock MCLK counts up to the specified value, and the RC pin of the counter 1 3 3 The logical value of the ripple carrier is "1".

On the other hand, the flip-flop 35 is set by the ETCK signal, and the logic value of the signal at its Q terminal is "1". The logical value of the signal at the Q terminal of this flip-flop; ° 35 is that the logical value of the signal at the ripple carrier of the RC terminal of the counter 33 is "1". Then, the logical value shifts from "1" to "0". In this case, it is shown in Fig. 9. In order to obtain the converted output, the number of clocks with the maximum amplitude value “4” (7 8: in Fig. 9) and the amplitude value at the subsequent clock (in Fig. 9) 3) is required. These are determined by the integer part and the fractional part obtained when multiplying X (0,…, 7) and AM (1, ····, 9) as is clear from the equation. That is, the integer part gives the number of clocks with the maximum amplitude value of 4, and the decimal part determines the amplitude value at the next clock.

Multiplier 3 1 in Fig. 11 1 © The A input is X (0,…, 7) and the B input is AM (1, ····, 9). As described above, the integer part P (0, ..., 7) of the output of the multiplier 3 1 depends on the inverter 3 2]? It is inverted and is an 8-bit binary count. It is used as the input for the terminal 3 3. The ETCK signal that is the input of the counter 1 3 3 and the NAND circuit 3 4 is the DA conversion start signal as described above] ?, and the logical value of this signal is "1". The rising edge of master clock MCLK] 9, the output of the counter 3 2 is loaded into the counter 1 3 3 and the flip-flop 3 5 Is set through the NAND circuit 3 4 and MSD = "1". The counter 33 starts counting with the load of the data, and counts P (0, ..., 7) master clocks MCLK. Then, the logical value of the carrier key LSD is set to "1". This LSD is a signal with a logical value of "1" for the amount of 1 • clock. When MSD = "1", LSD is reset by NAD circuit 36]? Flip 'Float: ° 3.5 is reset and MSD = "0". Therefore MSD

OMPI 0 Has a logical value of "1" for P (0,…, 7) clocks, and LSD has a logical value of "1" for the next one clock. Ruru.

The amplitude value of the conversion can be obtained by setting one of the analog switch groups 5 -1, 5-2 ... 5 -9 in Fig. 6 to " ^M ON". "ON" determines whether MSD gives the number of clocks with maximum width 4 and LSD which has logical value "1" and the SLSB, LSB and time axis which determine the amplitude value at that time. It depends on the MSB that decides the top and bottom of?

The conversion method shown in Fig. 9 requires a low-pass wave circuit that has a relatively low cutoff frequency for smoothing. To increase the cutoff frequency, the method shown in Fig. 12 is used. This divides the given number of transformation-required clocks 1 4 2 into 5 intervals such as 3 2, 3, 2 3, 3 2, 3 2, and 1 4, and performs D-A conversion for each interval. Is the way to go. Fig. 12 shows the case where the digital input is "0 1 0 0 0 1 1 1". Figure 13 shows an example of the circuit used in this case. The circuit of this embodiment has a combination of the circuit shown in FIG. 4 and the circuit shown in FIG. In the circuit of this embodiment, the circuit of FIG. 4 operates in the section where the number of conversion required clocks is 32, and the circuit of FIG. 11 operates in the last section.

In this case, let X be the total number of required π ck (corresponding to 1 4 2 in Fig. 12). X / 32 quotient M And let] 3 be XF, that is, X- 3 2 M + XF (M = 4 and XF = 1 4 in Fig. 12). In the first M sections with the required number of clocks of 32, the digital and digital input signals AM (1, ..., 5) and AM (6, 7) are used, and the last section is used. Then according to the multiplier 25]? The integer part P (3 ", 7) and the decimal part P (8, of the product of the obtained XF (0,…, 4) and AM (1, ..., 7) 9 :) is used .. AM (1,…, 5) and P (3,…, 7) are input to the A input terminal and B input terminal of the selector 1 26, respectively. ΑΜ (6, 7) and P (8, 9 :) are input to the B and A input terminals of the selector 1 27, respectively.

The ETCK signal is a signal whose logical value becomes "1" when D-A conversion is started as described above. The 5-bit binary counter 23 is cleared when the ETCK signal = "1". After that, every 32 clocks, that is, at the end of the M sections, the logic value of the ripple 'carrier CRY 1 of the RC terminal of the counter 23 is set to "1". The 4-bit binary counter 2 4 is loaded with —M (the 2's complement of M) from the ETCK signal at the start of the D-A conversion. This M is determined by the fact that the given number of required conversion π π-clocks X and the number of conversion period clock D CK of the time axis type D A conversion unit M are given, and this is set in advance. The counter 1 2 4 counts the ripple carrier CRY 1 and is the last clock of the Mth section, and the counter 2 4 is the riff. RUKARY — Set the logical value of CRY 2 to "1". The SEL signal is

Λ rr Its logical value is "1" in M sections? Its logical value is "0" in the last section. The 5-bit binary counter -29 outputs data at the start of D-A conversion and each time the ripple carrier CRY 1 = "1" of the counter 1 23. Speak.

For the first M intervals, the input at the A end of the selector 1 26 is inverted at the inverter 2 8 to P — and to the last interval. Then, the input of the B end is also reversed by the inverter 28 and is loaded. Therefore, the LSD, which is the ripple carrier of the counter 1 29, and the MSD, which is the output of the flip 'flop 30, are the conversion required clocks in the first M intervals. The number of clocks is 32, and the last interval is the number of clocks required for conversion XF. One

— The one-side selector 27 selects AM6 and AM7 in the first M sections and P8 and P9 in the last section to be S LSB and LSB, respectively. AM0 is used as it is as MS B. Even when the number of clocks required for conversion is different, the corresponding MSDs, LSDs, MSBs, SLSBs, and LSBs can be created, respectively. The circuit in the figure is driven to complete the desired D-A conversion.

In the above explanation, the unit area was filled from left to right on the time axis to create a unit area of a number proportional to the amount of digital as the input signal. This invention

OMPI IPO Four

Not limited to this embodiment, the point is to create a given number of unit areas. For example, in order to obtain the same number of unit areas as in Fig. 9, it is possible to fill the unit area along the direction of the amplitude axis as shown in Fig. 14.

The example shown in Fig. 14 corresponds to the case of digital input signal strength "" 0 1 0 0 0 1 1 1 0 0 ", which is the same as in Fig. 9. Fig. 14 shows that the number of clocks is 0 to 31 and the amplitude value is "3", and that the number of clocks is 3 2 to: 1 4 2 and the amplitude value is "2 J". In order to obtain the converted output as shown in Fig. 4, two amplitude values "2" and "3" and the place where the amplitude value changes (3 1 in the number of clocks;) should be specified. .. In this case, the following operation should be performed. The number of unit areas to be formed here is as shown in equation (3).

In the formula (3), it means that the number sandwiched by "<<" j is a binary number '. Eq. (3) J9 Clearly, 2 bits following the digital input signal sign bit are amplitude values.

“2” is determined, and the subsequent lower bits specify the location where the amplitude value changes. '

No.! Figures 15 and 16 show examples of the D-A converter that obtains the conversion output shown in Figure 4. The multiplier used in the circuit shown in Fig. 15 is that shown in Fig. 10.

R £ A

O PI WIFO Can be used as is. It is assumed that the circuit of Figure 6 is connected to the output of the circuit of Figure 16.

Figure 15 is a circuit for designating the place where the amplitude changes, and it is the circuit for designating 3 1 of the second term in the last line of equation (3). That is, the fly is 7 °. The output R of the floppy 4 2 is "1" only by the amount of 3 1 clocks. In other cases, it is "0".

Create a signal. In general, let the number of required clocks for D-A conversion be Χ (0, ..., 7). Also, the ETCK signal becomes "1" for one clock at the start of D-A conversion as described above.

Sync signal. The multiplier 3 7 has 8 bits of X (0,…, 7) as the A input, and 10 bits of the B input as the lower 7 bits of the digit and tally inputs. Bits AM (3, ..., 9) are given respectively. Output obtained as a result of multiplication

The integer part P (0, ..., 9) of P (0, ..., 9) obviously corresponds to the integer part of the second term in the last line of Eq. (3).

This output is inverted [9] by the inverter 38 and becomes the input signal of the 8-bit binary counter 39. The timing of the data 1 of the counter 1 39 is the same as that of the master clock MCLK when the ETCK signal is "1". It will be done in a timely manner. After that, set the master block MCLK to P

(0, ..., 7) When counting, the counter 1 39 outputs the ripple carrier CRY. On the other hand, the flip-flop 4 2 is synchronized with the NAND circuit 4 ◦]) The ETCK signal clock “1” and the rising edge of the master clock MCLK. Set

OMPI

WIPO Has been done. The output CRY of the counter 1 39 is fric: ° · Flo: 7 ° 4 2 The output CRY is fric through the NAND circuit 4 1 at the time of “1”; 7 °. · Reset Flop 42. That is, 3 R is a signal such that it is "1" for P (0, '", 7) clocks, and is" 0 "for others.

The width value of Fig. 14 depends on whether any one of the analog switch groups 5 -1, 5 -2 ... 5-9 of Fig. 6 is in the "ON" state. It is obtained. This amplitude value is related to R in Fig. 15 and, as can be seen from the first term in the last line of Eq. ( ³ ), the digital input AM (0, ...,-, 9) It is also related to the upper two bits after the decimal point, that is, AMI and AM2. In addition, this amplitude value is also related to the sign bit AM0 that determines the vertical direction of the time axis. Therefore, which one of the analog switch groups 5-1, 5-2 ... 5-S in Fig. 6 is set to the "ON" state is uniquely determined by AM0, AMI, AM2 and R. Be done. The relationship between these values and D 0 to D 8 is given by equation (4).

OMPI_

WIPO " The decoder shown in Fig. 16 realizes Eq. ( ⁴ ). This is the imperator N-6, N- 7-N-9, and the gates A-14, A-15. '"It is composed of A-29 and the targets 0-2, 0-3, 0-4.? When the input signals AM0, AMI, AM2 and R are given, the output end R 0 ~! The logical value of one of the signals is "1" D, and the corresponding analog switch group 5 -1, 5-2-5 -9 shown in Fig. 6 corresponds to "". Set to "ON" to obtain the converted output at output 7.

Finally, the number of required transform clocks X is divided into M + 1 intervals, the first M intervals contain 32 clocks, and the last interval contains XF (XF <3 2 ) Clocks, the unit area of the number to be formed is shown in Fig. 14 when the D-A transformation is performed individually in each interval. Explain the case of filling along the direction of. -Conversion when the number of clocks required for conversion is X = 1 4 2 and digital input A (0, '..., 7) = "0 1 0 0 0 1 1 1" Figure 17 shows an example of the output. Figure 18 shows an example of a concrete circuit that realizes this conversion operation. This circuit is ha. The part corresponding to the pulse width modulation type D-A converter] ?, and the part corresponding to the resistance voltage division type D-A converter is the same as in the case of Fig. 15 The circuits shown in Fig. 16 and Fig. 6 can be used as they are.

— As shown in Eq. (3) and Fig. 15, it is the number of clocks required for conversion that gives the place where the amplitude value changes. This is the integer part of the product of 3 2 in this interval, XF in the last interval, and the digital input AM (3,…, 7) (the decimal point immediately before AM 3).

As the multiplier 4 3 in Fig. 18, the one shown in Fig. 10 can be used as it is, and XF (0,…, 4) can be used as A input and B input as B input. M (3,…, 7) are given respectively. Here the output P (3,…, 7) is the integer part of the product]? It is given to the B input of the selector 1 4 4. If the number of transformation-required clocks is 3 2, the product of 3 2 and AM (3,…, 7) can be obtained by simply shifting the decimal point position 5 bits to the right. , This value is the A input of the selector 1 4 o

Either one of the A or B input data of the selector 4 4 is selected and inverted by the interpreter 4 5 and then the 5 bit binary counter 4 6 is selected. Given to the input. In this case, the data to be selected is instructed by the ripple 'carrier CRY 2 of the counter 48, but in the first M section, the A input data is In the last section, B input data is selected. The 5 bit binary counter 4 7 is cleared when the ET CK signal is "1". The ET CK signal is a signal that becomes "1" only for one clock at the start of D-A conversion as described above. The counter 1 4 7 then outputs a ripple 'carrier CRY 1 every 32 clocks. This ripple carrier CRY 1 is synchronized to each section.

It is a signal. The 4-bit binary counter 48 is synchronized with the ETCK signal and loads 1 M (0, ..., ..., 2) to turn on the ripple carrier CRY 1. Output the ripple carrier signal CTRY2 corresponding to the last one mouth of the Mth section, and apply this to the selector terminal of the selector 1 4 4. It is used as a signal.

Since the counter 1 46 loads the data in synchronization with the ETCK signal and the ripple carrier CRY 1, the data used for the first M section is the selector. The A input of 4 4 is inverted by the amplifier 45, and the B input of the selector 4 4 is inverted by the inverter 4 5 in the last interval. You will be asked to speak. Therefore, the counter 4 6 is AM (3,…, 7) counts after the data 1 was loaded in the first M section, and P (3,…,…, in the last section. 7) When counting the count, output the ripple carrier CRY from the RC terminal. This ripple carrier CRY controls the flip flocks; 7 ° 4-9-to generate the R signal corresponding to each section. This R signal drives the decoder shown in Fig. 16 along with AM0, AMI, and AM2, which in turn causes the analog switch group 5 — 1, 5 -2… 5— shown in Fig. 6. Any one of 9 can be turned "ON" and desired converted output can be obtained at output 7.

As described in detail above, the present invention is basically applied to the amplitude axis type D-A converter (that is, ladder type D-A converter) and the time axis type D-A converter that are conventionally used. Container Speaking of ha. A two-dimensional quantization is performed on the amplitude axis and the time axis using a combination of pulse width modulation type D-A converters). 13 conversion speed and accuracy are controlled according to the purpose. It is a new type of D-A converter that is efficient and possible. -

Industrial availability

As explained above, the D-A converter of the present invention can be downsized and can operate at high speed, and can add multiple signals.], The conversion according to the purpose and application It can be operated at speed and conversion accuracy. For this reason, it is ideal for various signal processing applications such as the electronic musical instrument field.

First of all, the D-A converter of the present invention having such a structure does not require an extremely fast conversion speed. It is possible to improve the accuracy by the number of bits of the pulse width modulation type D-A converter. For example, in the case of D-to-A conversion of a radio signal up to 15 kHz with a 30 kHz speed, a ladder type D-A operating at 1 MHz with 8-bit precision is used. With a converter, this and 5 bit c. A combination of a loose width type D-A converter]], the conversion speed

It is possible to obtain a D-A converter with 1 MHz / 32 to 30 kHz and an accuracy of 8 + 5 = 13 bits.

Second, it solves the problem of crosstalk between adjacent channels that occurs when a ladder D-A converter is used by time division multiplexing, and the conversion speed is slow. When it's good, it's one \ νι? Ο For this reason, it is possible to increase the quantization number in the time axis direction and increase the conversion accuracy (the number of bits). Therefore, if you want to process multiple signals at the same time, add them first and then perform D-A conversion. It is possible to remove the expensive sample-and-hold circuit that does not affect the power supply and accuracy.

O PI

W WIIPPOO .Λ

Claims

The scope of the claims

(1) a de I 'Kuta Le input signal corresponding to the value c ⁰ c with Le-width. A time-axis DA converter that converts the signal to a pulse signal and a c that has an amplitude corresponding to the value of the digital input signal. Input a grip-width type DA converter for converting to a pulse signal and a predetermined upper bit of the digital input signal to one of the time axis type DA converter or the amplitude type DA converter. And the upper bit of the converted output from the converter and the remaining lower bits of the digital input signal to the time base DA converter or the amplitude. D-A converter having means for inputting to the other of the type DA converter.

(2) It further includes a multiplier for multiplying the digital input signal and the number of clocks required for conversion, and the upper bit in the output of the multiplier "" is sent to the time axis DA converter. The D-A converter according to claim 1, characterized in that the converted output and the lower bit of the output of the multiplier are supplied to the amplitude axis type DA converter. ..

(3) The first conversion required click Lock the click number by it]) in also has a small second conversion 'required click D click number χ ₂ percentage? The upper bit of the digital input signal is converted by the integer part Μ of the value, and converted by the inter-axis D Δ conversion part, and the converted output and the digital input are converted. Means for repeating the conversion of the lower bit of the signal by the amplitude axis type DA converter, the fractional part in the value damaged by X i X ₂ and the digital input

OMFI

//. V / IPO A multiplier for multiplying the signal and the upper bit in the output of the multiplier is converted by the time axis DA converter, and the converted output and the lower bit in the output of the multiplier are converted. The D-A converter according to claim 1, further comprising: a means for converting and in the amplitude axis type DA converter.

(4) A multiplier that multiplies the lower bit of the digital input signal and the number of clocks required for conversion, and the integer part of the multiplier calculation force of the multiplier to the time axis DA. A means for supplying and converting the converted output and the upper bit of the converted output and the rest of the input signal] 9 to the amplitude / time-axis DA converting section. D-A converter in the first section of the range.

(5) and the fractional part content in the split Tsu value "" in the first conversion required click π click number Χ the second conversion required click not small even by it ι lock the number of X _2, said de I 'di A multiplier that multiplies the lower bit of the digital input signal with the lower bit of the digital input signal as the number of clocks required for the second conversion X ₂ The conversion unit converts the converted output and the upper bits of the remaining digital input signal to the amplitude time axis DA conversion unit, and X i is converted to X ₂ . A means for repeating the number M of the integer parts in the divided value, and an integer part in the multiplication calculation power of the multiplier are converted by the time axis type DA conversion unit, and the conversion output and the digit and tar A D-A converter according to claim 1, further comprising: a means for converting the upper-order bit of the input signal] 9 in the amplitude-time axis DA conversion section.