UST955008I4 - Flip chip structure including a silicon semiconductor element bonded to an Si3 N4 base substrate - Google Patents

Flip chip structure including a silicon semiconductor element bonded to an Si3 N4 base substrate Download PDF

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Publication number
UST955008I4
UST955008I4 US05/693,385 US69338576A UST955008I4 US T955008 I4 UST955008 I4 US T955008I4 US 69338576 A US69338576 A US 69338576A US T955008 I4 UST955008 I4 US T955008I4
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US
United States
Prior art keywords
semiconductor element
base substrate
structure including
flip chip
silicon semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US05/693,385
Inventor
Lawrence V. Gregor
Robert G. Shepheard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US05/693,385 priority Critical patent/UST955008I4/en
Application granted granted Critical
Publication of UST955008I4 publication Critical patent/UST955008I4/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/692—Ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying

Landscapes

  • Wire Bonding (AREA)

Abstract

A semiconductor device and carrier assembly package having a silicon integrated circuit semiconductor device provided with at least three raised electrical contacts on a first surface, a device support substrate of Si3 N4 provided with a conductive metallurgy pattern on at least one surface, the conductive pattern including an electrical contact configuration matching the raised electrical contacts on the device, metallurgical bonds between the raised electrical contacts on the device and the electrical contact pattern on the support substrate, and an electrically conductive means for electrically connecting elements of the conductive metallurgy pattern to coacting elements off the support substrate.
US05/693,385 1974-08-19 1976-06-07 Flip chip structure including a silicon semiconductor element bonded to an Si3 N4 base substrate Pending UST955008I4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US05/693,385 UST955008I4 (en) 1974-08-19 1976-06-07 Flip chip structure including a silicon semiconductor element bonded to an Si3 N4 base substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US49848774A 1974-08-19 1974-08-19
US05/693,385 UST955008I4 (en) 1974-08-19 1976-06-07 Flip chip structure including a silicon semiconductor element bonded to an Si3 N4 base substrate

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US49848774A Continuation 1974-08-19 1974-08-19

Publications (1)

Publication Number Publication Date
UST955008I4 true UST955008I4 (en) 1977-02-01

Family

ID=27052844

Family Applications (1)

Application Number Title Priority Date Filing Date
US05/693,385 Pending UST955008I4 (en) 1974-08-19 1976-06-07 Flip chip structure including a silicon semiconductor element bonded to an Si3 N4 base substrate

Country Status (1)

Country Link
US (1) UST955008I4 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4225900A (en) 1978-10-25 1980-09-30 Raytheon Company Integrated circuit device package interconnect means
US4367513A (en) 1979-12-26 1983-01-04 Lockheed Corporation Quick attach/detach instrument panel and method
US4493146A (en) 1979-12-26 1985-01-15 Lockheed Corporation Quick attach detach instrument panel method
US4661192A (en) 1985-08-22 1987-04-28 Motorola, Inc. Low cost integrated circuit bonding process
US4774630A (en) * 1985-09-30 1988-09-27 Microelectronics Center Of North Carolina Apparatus for mounting a semiconductor chip and making electrical connections thereto
US5368217A (en) * 1993-08-25 1994-11-29 Microelectronics And Computer Technology Corporation High force compression flip chip bonding method and system
US5379191A (en) * 1991-02-26 1995-01-03 Microelectronics And Computer Technology Corporation Compact adapter package providing peripheral to area translation for an integrated circuit chip
US5679977A (en) * 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5682061A (en) * 1990-09-24 1997-10-28 Tessera, Inc. Component for connecting a semiconductor chip to a substrate
US6133627A (en) * 1990-09-24 2000-10-17 Tessera, Inc. Semiconductor chip package with center contacts
US20010030370A1 (en) * 1990-09-24 2001-10-18 Khandros Igor Y. Microelectronic assembly having encapsulated wire bonding leads
US20020155728A1 (en) * 1990-09-24 2002-10-24 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US20050045697A1 (en) * 2003-08-26 2005-03-03 Lacap Efren M. Wafer-level chip scale package

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4225900A (en) 1978-10-25 1980-09-30 Raytheon Company Integrated circuit device package interconnect means
US4367513A (en) 1979-12-26 1983-01-04 Lockheed Corporation Quick attach/detach instrument panel and method
US4493146A (en) 1979-12-26 1985-01-15 Lockheed Corporation Quick attach detach instrument panel method
US4661192A (en) 1985-08-22 1987-04-28 Motorola, Inc. Low cost integrated circuit bonding process
US4774630A (en) * 1985-09-30 1988-09-27 Microelectronics Center Of North Carolina Apparatus for mounting a semiconductor chip and making electrical connections thereto
EP0218438A3 (en) * 1985-09-30 1989-03-01 Mcnc Apparatus for mounting a semiconductor chip and making electrical connections thereto
US6465893B1 (en) 1990-09-24 2002-10-15 Tessera, Inc. Stacked chip assembly
US6433419B2 (en) 1990-09-24 2002-08-13 Tessera, Inc. Face-up semiconductor chip assemblies
US7291910B2 (en) 1990-09-24 2007-11-06 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5679977A (en) * 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5682061A (en) * 1990-09-24 1997-10-28 Tessera, Inc. Component for connecting a semiconductor chip to a substrate
US5685885A (en) * 1990-09-24 1997-11-11 Tessera, Inc. Wafer-scale techniques for fabrication of semiconductor chip assemblies
US5848467A (en) * 1990-09-24 1998-12-15 Tessera, Inc. Methods of making semiconductor chip assemblies
US5950304A (en) * 1990-09-24 1999-09-14 Tessera, Inc. Methods of making semiconductor chip assemblies
US6133627A (en) * 1990-09-24 2000-10-17 Tessera, Inc. Semiconductor chip package with center contacts
US20010030370A1 (en) * 1990-09-24 2001-10-18 Khandros Igor Y. Microelectronic assembly having encapsulated wire bonding leads
US6372527B1 (en) 1990-09-24 2002-04-16 Tessera, Inc. Methods of making semiconductor chip assemblies
US7198969B1 (en) 1990-09-24 2007-04-03 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US20050218495A1 (en) * 1990-09-24 2005-10-06 Tessera, Inc. Microelectronic assembly having encapsulated wire bonding leads
US20020155728A1 (en) * 1990-09-24 2002-10-24 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US20050087855A1 (en) * 1990-09-24 2005-04-28 Tessera, Inc. Microelectronic component and assembly having leads with offset portions
US5379191A (en) * 1991-02-26 1995-01-03 Microelectronics And Computer Technology Corporation Compact adapter package providing peripheral to area translation for an integrated circuit chip
US5368217A (en) * 1993-08-25 1994-11-29 Microelectronics And Computer Technology Corporation High force compression flip chip bonding method and system
US5462217A (en) * 1993-08-25 1995-10-31 Microelectronics And Computer Technology Corporation High force compression flip chip bonding system
US20050045697A1 (en) * 2003-08-26 2005-03-03 Lacap Efren M. Wafer-level chip scale package
US8106516B1 (en) 2003-08-26 2012-01-31 Volterra Semiconductor Corporation Wafer-level chip scale package
US8710664B2 (en) 2003-08-26 2014-04-29 Volterra Semiconductor Corporation Wafer-level chip scale package

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