UST101804I4 - Integrated circuit layout utilizing separated active circuit and wiring regions - Google Patents
Integrated circuit layout utilizing separated active circuit and wiring regions Download PDFInfo
- Publication number
- UST101804I4 UST101804I4 US06146909H US101804DH UST101804I4 US T101804 I4 UST101804 I4 US T101804I4 US 06146909 H US06146909 H US 06146909H US 101804D H US101804D H US 101804DH US T101804 I4 UST101804 I4 US T101804I4
- Authority
- US
- United States
- Prior art keywords
- conductors
- logic cells
- elongated
- wiring regions
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H10W20/43—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/901—Masterslice integrated circuits comprising bipolar technology
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
An LSI masterslice wiring technique, employing an array of elongated logic cells. A first level of metallization includes a first set of elongated, generally parallel conductors, orthogonal to the elongated logic cells and selectively contacting the cells. A second level of metal conductors, overlying and insulated from the first set, extends orthogonal to the first set, and thus parallel to the elongated logic cells. The second set includes both conductors passing over the areas of the logic cells and conductors lying between the logic cells. Conductors of the second set are selectively connected to conductors of the first set. This application has the same disclosure as that of Defensive Publication T100,501, published Apr. 7, 1981, but the abstracts are in conflict.
Publications (1)
| Publication Number | Publication Date |
|---|---|
| UST101804I4 true UST101804I4 (en) | 1982-05-04 |
Family
ID=2171280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US06146909H Pending UST101804I4 (en) | 1980-05-05 | Integrated circuit layout utilizing separated active circuit and wiring regions |
Country Status (1)
| Country | Link |
|---|---|
| US (1) | UST101804I4 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4623911A (en) | 1983-12-16 | 1986-11-18 | Rca Corporation | High circuit density ICs |
| US4775942A (en) | 1985-12-09 | 1988-10-04 | International Business Machines Corporation | Seed and stitch approach to embedded arrays |
| US4855803A (en) | 1985-09-02 | 1989-08-08 | Ricoh Company, Ltd. | Selectively definable semiconductor device |
| US5517040A (en) * | 1987-04-30 | 1996-05-14 | International Business Machines Corporation | Personalizable semiconductor chips for analog and analog/digital circuits |
| US5949098A (en) * | 1995-06-15 | 1999-09-07 | Oki Electric Industry Co., Ltd. | Semiconductor integrated circuit having an improved arrangement of power supply lines to reduce noise occurring therein |
-
1980
- 1980-05-05 US US06146909H patent/UST101804I4/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4623911A (en) | 1983-12-16 | 1986-11-18 | Rca Corporation | High circuit density ICs |
| US4855803A (en) | 1985-09-02 | 1989-08-08 | Ricoh Company, Ltd. | Selectively definable semiconductor device |
| US4775942A (en) | 1985-12-09 | 1988-10-04 | International Business Machines Corporation | Seed and stitch approach to embedded arrays |
| US5517040A (en) * | 1987-04-30 | 1996-05-14 | International Business Machines Corporation | Personalizable semiconductor chips for analog and analog/digital circuits |
| US5949098A (en) * | 1995-06-15 | 1999-09-07 | Oki Electric Industry Co., Ltd. | Semiconductor integrated circuit having an improved arrangement of power supply lines to reduce noise occurring therein |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| STPP | Information on status: patent application and granting procedure in general |
Free format text: DEFENSIVE PUBLICATION OR SIR FILE |