USRE47240E1 - Semiconductor storage device - Google Patents

Semiconductor storage device Download PDF

Info

Publication number
USRE47240E1
USRE47240E1 US14/152,259 US201414152259A USRE47240E US RE47240 E1 USRE47240 E1 US RE47240E1 US 201414152259 A US201414152259 A US 201414152259A US RE47240 E USRE47240 E US RE47240E
Authority
US
United States
Prior art keywords
storage node
node contact
contacts
active regions
contact pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US14/152,259
Inventor
Eiji Hasunuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Longitude Licensing Ltd
Original Assignee
Longitude Licensing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Longitude Licensing Ltd filed Critical Longitude Licensing Ltd
Priority to US14/152,259 priority Critical patent/USRE47240E1/en
Assigned to LONGITUDE SEMICONDUCTOR S.A.R.L. reassignment LONGITUDE SEMICONDUCTOR S.A.R.L. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: PS5 LUXCO S.A.R.L.
Assigned to PS5 LUXCO S.A.R.L. reassignment PS5 LUXCO S.A.R.L. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PS4 LUXCO S.A.R.L.
Assigned to LONGITUDE LICENSING LIMITED reassignment LONGITUDE LICENSING LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LONGITUDE SEMICONDUCTOR S.A.R.L.
Application granted granted Critical
Publication of USRE47240E1 publication Critical patent/USRE47240E1/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H01L27/10814—
    • H01L27/10855—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor storage device, and particularly relates to a DRAM (Dynamic Random Access Memory) memory cell layout.
  • DRAM Dynamic Random Access Memory
  • DRAM which is one type of semiconductor storage device
  • a memory cell composed of a single transistor and a single capacitor is disposed at the intersection of a word line and a bit line that intersect with each other.
  • Layout systems in DRAM memory cells are classified as folded bit line systems and open bit line systems (see Japanese Laid-open Patent Application No. 2004-80009).
  • a folded bit line system two bit lines that are connected to a single sense amplifier are folded at the sense amplifier so as to be wired in the same direction, and the minimum theoretical area of the memory cell is 8F 2 (4F ⁇ 2F), wherein “F” is the minimum feature size (half the pitch of the word lines).
  • an open bit line system two bit lines that are connected to a single sense amplifier are wired so as to extend in opposite directions on the sides of the sense amplifier, and the minimum theoretical area of the memory cell is 6F 2 (2F ⁇ 3F).
  • FIG. 23A through 23F shows an example of the layout of conventional DRAM having a cell area of 6F 2 .
  • a plurality of active regions 13 is formed symmetrically about a line ( FIG. 23A ), and word lines 14 are wired in the Y direction at intervals of 1F ( FIG. 23B ).
  • Cell contacts 18 are formed in the center portions and end portions of the active regions 13 ( FIG. 23C ).
  • Bit line contacts (not shown) are formed directly above the cell contacts 18 of the central portions, and bit lines are wired so as to extend in the X direction in meandering fashion over the bit line contacts so as to avoid the cell contacts 18 of the end portions ( FIG. 23D ).
  • Storage node contacts 24 are formed above the cell contacts 18 disposed at the end portions of the active regions 13 ( FIG.
  • the center positions of the storage node contacts 24 are offset from the center positions of the cell contacts 18 , whereby the storage node contacts 24 are arranged at equal intervals in the X direction.
  • Storage capacitors 28 are also formed directly above the storage node contacts 24 ( FIG. 23F ).
  • Japanese Laid-open Patent Application No. 2004-80009 discloses a structure of an integrated circuit memory element in which a landing pad is formed between a contact plug and a storage capacitor.
  • This integrated circuit memory element comprises an interlayer insulating film that is formed on a substrate and has numerous storage node contact holes arranged linearly in one direction; storage node contacts that are embedded in the storage node contact holes; an insulating film that is formed on an interlayer insulating film and has numerous landing pad holes that are arranged nonlinearly in one direction and that expose the storage node contacts; landing pads that are embedded in the landing pad holes and connected to the storage node contacts; and storage capacitors connected to the landing pads.
  • the storage capacitors can be arranged in a zigzag pattern in a plane even when the contact plugs are aligned in the transverse and longitudinal directions of the plane.
  • the layout of conventional DRAM having the memory cell area of 6F 2 shown in FIGS. 23A through 23F has a region in which the storage capacitors are not arranged in zigzag fashion on the plane, and the storage capacitors cannot be placed in a perfectly zigzag arrangement. Therefore, the storage capacitors cannot be packed at maximum density.
  • the storage capacitors can be arranged in zigzag fashion and packed at maximum density merely by being arranged in zigzag fashion so as to be offset from each other.
  • HSG-Si Hemi-Sphericai Grained poly-Si
  • a semiconductor storage device comprising a semiconductor substrate; a plurality of active regions formed in the shape of a band in the semiconductor substrate; a plurality of word lines arranged at equal intervals so as to intersect the active regions; a plurality of cell contacts that includes first cell contacts formed in the active regions in the center portions in the longitudinal direction thereof, and second cell contacts formed at each end portion at both ends in the longitudinal direction; bit line contacts formed on the first cell contacts; bit lines wired so as to pass over the bit line contacts; storage node contacts formed on the second cell contacts; storage node contact pads formed on the storage node contacts; and storage capacitors formed on the storage node contact pads, wherein the center positions of the storage node contacts are offset in a prescribed direction from the center positions of the second cell contacts, and the center positions of the storage node contact pads are offset in a prescribed direction from the center positions of the storage node contacts.
  • the storage capacitors it is possible to arrange the storage capacitors at high density and adequately ensure the HSG blockage margin in a DRAM or other semiconductor storage device that has a 6F 2 cell layout.
  • the plurality of active regions is preferably aligned with a straight line that forms a prescribed angle with the X direction intersecting the word lines, and is aligned with the Y direction parallel to the word lines, and the prescribed angle is preferably approximately 18 degrees.
  • the distance between the center positions of two cell contacts can be set to 4F in the X direction and 4/3F in the Y direction, and the optimum cell contact layout can be achieved in a 6F 2 layout when the cell contacts are formed at both end portions of the active regions.
  • the center positions of the storage node contacts are preferably offset toward the corresponding bit line contacts in relation to the center positions of the second cell contacts, and are preferably offset so as to be at equal intervals in the X direction in relation to the center positions of the second cell contacts. All of the storage node contact pads can thereby be offset by the same amount, and it is easy to ultimately create a high-precision, high-density layout of the storage capacitors when the storage node contact pads are laid out at maximum density.
  • a first pad layout in which the positions of the storage node contact pads are offset in the direction towards the center portions of the corresponding active regions, and a second pad layout in which the positions of the storage node contact pads are offset in the direction away from the center portions of the corresponding active regions are preferably employed in alternating fashion for the plurality of active regions arranged in the Y direction.
  • the first and second pad layouts are also preferably employed in alternating fashion for the plurality of active regions arranged on the straight line.
  • the amount of offset of the storage node contact pads is preferably 3/4F in the X direction and 1/3F in the Y direction. Offsetting the storage node contact pads in the manner described above makes it possible to arrange the storage node contact pads in a uniform zigzag pattern, and to easily achieve a high-precision, high-density layout of the storage capacitors.
  • FIG. 1 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming active regions 13 ) according to a preferred embodiment of the present invention
  • FIG. 2 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming word lines 14 ) according to a preferred embodiment of the present invention
  • FIG. 3 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming side walls 15 and silicon epitaxial layers 16 ) according to a preferred embodiment of the present invention
  • FIG. 4 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming cell contacts 18 ) according to a preferred embodiment of the present invention
  • FIG. 5 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming bit line contacts 20 ) according to a preferred embodiment of the present invention
  • FIG. 6 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming bit lines 22 ) according to a preferred embodiment of the present invention
  • FIG. 7 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming storage node contacts 24 ) according to a preferred embodiment of the present invention
  • FIG. 8 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming storage node contact pads 26 ) according to a preferred embodiment of the present invention
  • FIG. 9 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming storage capacitors 28 ) according to a preferred embodiment of the present invention.
  • FIG. 10 is a schematic sectional view along line P-P in FIG. 1 ;
  • FIG. 11 is a schematic sectional view along line P-P in FIG. 2 ;
  • FIG. 12 is a schematic sectional view along line P-P in FIG. 3 ;
  • FIG. 13 is a schematic sectional view along line P-P in FIG. 4 ;
  • FIG. 14 is a schematic sectional view along line P-P in FIG. 5 ;
  • FIG. 15 is a schematic sectional view along line P-P in FIG. 6 ;
  • FIG. 16 is a schematic sectional view along line P-P in FIG. 7 ;
  • FIG. 17 is a schematic sectional view along line P-P in FIG. 8 ;
  • FIG. 18 is a schematic sectional view along line P-P in FIG. 9 ;
  • FIG. 19 is a schematic plan view showing details of the layout shown in FIG. 8 ;
  • FIG. 20 is a schematic plan view showing details of the layout shown in FIG. 8 ;
  • FIG. 21 is a schematic plan view showing details of the layout shown in FIG. 8 ;
  • FIG. 22 is a schematic plan view showing details of the layout shown in FIG. 8 ;
  • FIG. 23A is a schematic plan view showing an example of the layout of conventional DRAM having a cell area of 6F 2 ;
  • FIG. 23B is a schematic plan view showing an example of the layout of conventional DRAM having a cell area of 6F 2 ;
  • FIG. 23C is a schematic plan view showing an example of the layout of conventional DRAM having a cell area of 6F 2 ;
  • FIG. 23D is a schematic plan view showing an example of the layout of conventional DRAM having a cell area of 6F 2 ;
  • FIG. 23E is a schematic plan view showing an example of the layout of conventional DRAM having a cell area of 6F 2 ;
  • FIG. 23F is a schematic plan view showing an example of the layout of conventional DRAM having a cell area of 6F 2 .
  • FIGS. 1 through 9 are schematic plan views showing the layout in the sequence of the manufacturing process of the DRAM 10 as an embodiment of the semiconductor storage device of the present invention.
  • FIGS. 10 through 18 are schematic sectional views along line P-P in FIGS. 1 through 9 , respectively.
  • a field oxide film (element separation region) 12 is first formed by STI (Shallow Trench Isolation) or another method on a silicon substrate 11 as shown in FIGS. 1 and 10 , whereby a plurality of active regions 13 is formed.
  • the active regions 13 are substantially band-shaped regions having a prescribed length, and the plurality of active regions 13 is formed in a straight line in the longitudinal direction thereof.
  • the longitudinal direction of the active regions 13 is angled approximately 18 degrees from the X direction, wherein the X direction is the direction orthogonal to the wiring direction of the word lines described hereinafter.
  • the X direction component of the distance between the center positions of two cell contacts formed at end portions on both ends of the active regions can be set to 4F
  • the Y direction component can be set to 4/3F in the formation of the cell contacts described hereinafter.
  • the optimum cell contact layout can therefore be achieved in a 6F 2 layout.
  • the wiring direction of the word lines is the Y direction
  • the active regions 13 are arranged at equal intervals in the Y direction.
  • the width of the active regions 13 is about 1F (wherein F is the minimum feature size), and the length is about 5.1F.
  • the distance between the centers of active regions 13 that are adjacent in the Y direction is set to 2F.
  • a plurality of word lines 14 is then formed on the silicon substrate 11 in which the active regions 13 are formed.
  • the word lines 14 are wired in the Y direction, and the width of the word lines 14 and the space between adjacent word lines 14 , 14 are both set to 1F.
  • Two word lines 14 L, 14 R intersect in a single active region 13 .
  • One word line 14 L passes between the center portion and one end portion of the active region 13
  • the other word line 14 R passes between the center portion and the other end portion of the active region 13 .
  • One of three word lines 14 does not intersect with the active region 13 , and is a dummy word line 14 D that does not actually function as a word line.
  • gate oxide films 14 a are first formed on the entire surface of the active region 13 , after which conducting films 14 b formed by layering a polysilicon film, a tungsten silicide film, a tungsten nitride film, and a tungsten film in sequence are formed on the gate oxide films 14 a, and gate cap insulating films 14 c composed of silicon nitride are then formed.
  • the word lines 14 are then formed by patterning the multilayer film in linear fashion.
  • side walls 15 are then formed on both sides of the word lines 14 , and silicon epitaxial layers 16 are formed in the exposed portions of the active regions 13 .
  • the side walls 15 are formed by a process in which a silicon nitride film having a thickness of about 26 nm is formed on the entire surface of the substrate, and the silicon nitride film is then etched back.
  • the end portions and the center portions of the active regions 13 which are the exposed portions, are then grown epitaxially, and the silicon epitaxial layers 16 are formed.
  • the width of the silicon epitaxial layers 16 is preferably about 60 nm, the width thereof in the Y direction is preferably about 168 nm, and the separation margin between silicon epitaxial layers 16 , 16 that are adjacent in the Y direction is preferably about 30 nm.
  • cell contacts 18 are formed above the center portions and the portions at both ends of the active regions 13 .
  • the cell contacts 18 are formed by a process in which an interlayer insulating film 17 composed of BPSG (Boro-Phospho Silicate Glass) having a prescribed thickness is formed on the entire surface of the substrate, contact holes that pass through the interlayer insulating film 17 are formed in the center portions and the portions at both ends of the active regions 13 , and DOPOS (Doped Poly-Silicon) or another conductive material is filled into the contact holes.
  • the contact holes are formed by photolithography and etching using a resist mask.
  • the cell contacts 18 are formed by a process in which DOPOS is deposited on the entire surface of the substrate, including the interior of the contact holes, and the DOPOS is then polished by CMP so as to remain only in the interior of the contact holes.
  • the X direction component of the distance between the center portions of the cell contacts 18 b, 18 b formed at the portions at both ends of the active regions 13 is set to 4F, and the Y direction component is set to 4/3F.
  • the cell contacts 18 a formed in the center portions of the active regions 13 are provided in the middle position between the cell contacts 18 b, 18 b of the portions at both ends.
  • the distance between the centers of cell contacts 18 , 18 that are adjacent in the Y direction is 2F.
  • the top diameter of the cell contacts 18 is preferably about 140 nm, and the bottom diameter is preferably about 93 nm.
  • bit line contacts 20 are formed above the cell contacts (hereinafter referred to as first cell contacts) formed in the center portions of each of the active regions 13 .
  • the bit line contacts 20 are formed by a process in which an interlayer insulating film 19 composed of BPSG having a prescribed thickness is formed on the entire surface of the substrate, and contact holes that pass through the interlayer insulating film 19 are formed above the first cell contacts 18 a, after which tungsten or another conductive material is filled into the contact holes.
  • the center positions of the bit line contacts 20 coincide with the center positions of the first cell contacts 18 a.
  • the contact holes are formed by photolithography and etching using a resist mask.
  • the bit line contacts 20 are formed by a process in which tungsten is deposited on the entire surface of the substrate, including the interior of the contact holes, and the tungsten is then polished by CMP so as to remain only in the interior of the contact holes.
  • the distance between the centers of two bit line contacts 20 , 20 that are adjacent in the Y direction is 2F.
  • the top diameter (diameter) of the bit line contacts 20 is preferably about 120 nm, and the bottom diameter (diameter) is preferably about 93 nm.
  • bit lines 22 is then wired in the X direction, as shown in FIGS. 6 and 15 .
  • the bit lines 22 pass through over the bit line contacts 20 , and are wired in meandering fashion so as not to be above the cell contacts (hereinafter referred to as second cell contacts) 18 b formed in the portions at both ends of the active regions 13 .
  • the bit lines 22 are formed by a process in which a tungsten nitride film 22 a and a tungsten film 22 b are deposited in sequence on the entire surface of the substrate by sputtering, after which the films are etched using a silicon nitride film or other hard mask.
  • Bit lines 22 having a line width that is adequately smaller than the minimum feature size F can thereby be formed, and a margin of deviation with respect to the bit line contacts 20 can be adequately maintained.
  • the widest distance between bit lines 22 that are adjacent in the Y direction is 2F, and the narrowest distance is 1.9F.
  • the meandering width of the bit lines 22 is set to 2/3F, and the fold angle for meandering is set to approximately 18 degrees, so as to be the same as the tilt of the active regions 13 . Accordingly, the bit lines 22 have a portion that extends parallel to the active regions 13 .
  • storage node contacts 24 are formed above the second cell contacts 18 b.
  • an interlayer insulating film 23 composed of a silicon oxide film having a prescribed thickness is formed on the entire surface of the substrate, and elliptical contact holes are formed so as to pass through the interlayer insulating film 23 above the second cell contacts 18 b.
  • the storage node contacts 24 are then formed by a process in which DOPOS or another conductive material is deposited on the entire surface of the substrate, including the interior of the contact holes, and the conducting material is then polished by CMP so as to remain only in the interior of the contact holes.
  • the center positions of the storage node contacts 24 do not coincide with the center positions of the second cell contacts 18 b, but are offset 0.5F in the X direction towards the center portions of the corresponding active regions 13 .
  • the storage node contacts 24 are arranged at equal intervals in the X direction.
  • the distance between the centers of two storage node contacts 24 , 24 that are adjacent in the Y direction is 2.0F, and the other distance between the centers of two storage node contacts 24 , 24 that are adjacent in the tilted direction is about 3.07F.
  • the minor axis and major axis of the bottom diameter of the storage node contacts 24 are preferably 70 nm and 120 nm, respectively, and the minor axis and major axis of the top diameter are preferably 97 nm and 138 nm, respectively.
  • elliptical storage node contact pads 26 are formed above the storage node contacts 24 .
  • the storage node contact pads 26 are formed by depositing DOPOS or another conductive material on the interlayer insulating film 23 and the storage node contacts 24 , and then etching the conductive material by using a resist mask.
  • the storage node contact pads 26 and the storage node contacts 24 may be formed simultaneously by a process in which contact holes that pass through the interlayer insulating film 23 are formed, DOPOS is formed on the entire surface so as to fill the contact holes, and etching is then performed using a resist mask composed of a pattern for the storage node contact pads.
  • the area of the storage node contact pads 26 is wider than the area of the storage node contacts 24 , and the lengths of the minor axis and major axis thereof are set to 135 nm and 170 nm, respectively.
  • the center positions of the storage node contact pads 26 do not coincide with the center positions of the storage node contacts 24 , and are offset further to the inside (in the direction that approaches the center portions of the corresponding active regions 13 ) or further to the outside (in the direction away from the center portions of the corresponding active regions 13 ) than the center positions of the storage node contacts 24 .
  • the layout of the storage node contact pads 26 is a combination of a first pad layout in which two storage node contact pads 26 that correspond to the same active region are offset (to the inside) in the direction that approaches the center portions of the active regions 13 , and a second pad layout in which two storage node contact pads 26 that correspond to the same active region are offset (to the outside) in the direction away from the center portions of the active regions 13 .
  • the first pad layout and the second pad layout are employed in alternating fashion for the plurality of active regions 13 arranged in the Y direction. For example, in the first, second, and third active regions 13 A through 13 C in FIG.
  • the storage node contact pads 26 , 26 based on the first active region 13 A have the first pad layout that is offset to the inside;
  • the storage node contact pads 26 , 26 based on the second active region 13 B have the second pad layout that is offset to the outside;
  • the storage node contact pads 26 , 26 based on the third active region 13 C have the first pad layout that is offset to the inside.
  • the center positions of the storage node contact pads 26 are offset in a tilted direction.
  • the offset direction has both an X direction component and a Y direction component.
  • the center positions of the storage node contact pads 26 are offset 3/4F in the direction that approaches the center portions of the corresponding active regions with respect to the X direction, and are offset 1/3F in the direction away from the center portions of the corresponding active regions 13 with respect to the Y direction.
  • the center positions of the storage node contact pads 26 are offset 3/4F in the direction away from the center portions of the corresponding active regions 13 with respect to the X direction, and are offset 1/3F in the direction away from the center portions of the corresponding active regions 13 with respect to the Y direction.
  • the distance between the centers of two storage node contact pads 26 that are adjacent in the X direction is thereby set to 3F, and the interval at which the storage node contact pads 26 are arranged in the Y direction is set to 2F. At this time, the distance between the centers of two storage node contact pads 26 that are adjacent in the tilted direction is 2.5F.
  • FIGS. 19 through 22 are schematic plan views showing details of the layout shown in FIG. 8 .
  • the positional relationship between the first storage node contact pad 26 a formed at one end portion of the active region 13 A and the second storage node contact pad 26 b formed at one end of the active region 13 B is equivalent to the positional relationship between the third and fourth storage node contact pads 26 c and 26 d formed at the respective end portions of the active region 13 C.
  • the positional relationship between the first storage node contact pad 26 a and the third storage node contact pad 26 c is also equivalent to the positional relationship between the second storage node contact pad 26 b and the fourth storage node contact pad 26 d.
  • the distance L 11 between the center positions of the first and second storage node contact pads 26 a, 26 b; the distance L 12 between the center positions of the second and fourth storage node contact pads 26 b, 26 d; the distance L 13 between the center positions of the fourth and third storage node contact pads 26 d, 26 c; and the distance L 14 between the center positions of the third and first storage node contact pads 26 c, 26 a are all set so as to be equal, and the line that continuously connects these center position points forms a diamond shape.
  • the line segment that connects the center position of the second storage node contact pad 26 b and the center position of the third storage node contact pad 26 c in the X direction, and the line segment that connects the center position of the first storage node contact pad 26 a and the center position of the fourth storage node contact pad 26 d in the Y direction are orthogonal to each other, and one line segment passes through the center point of the other line segment.
  • the positional relationship between the first storage node contact pad 26 e formed at one end of the active region 13 F, and the second storage node contact pad 26 f formed at one end of the active region 13 G is equivalent to the positional relationship between the third storage node contact pad 26 b formed at one end of the active region 13 B, and the fourth storage node contact pad 26 g formed at one end of the active region 13 H.
  • the positional relationship between the first storage node contact pad 26 e and the third storage node contact pad 26 b is also equivalent to the positional relationship between the second storage node contact pad 26 f and the fourth storage node contact pad 26 g.
  • the distance L 21 between the center positions of the first and second storage node contact pads 26 e, 26 f; the distance L 22 between the center positions of the second and fourth storage node contact pads 26 f, 26 g; the distance L 23 between the center positions of the fourth and third storage node contact pads 26 g, 26 b; and the distance L 24 between the center positions of the third and first storage node contact pads 2 Gb, 26 e are all set so as to be equal, and the line that continuously connects these center position points forms the same diamond shape as the one shown in FIG.
  • the line segment that connects the center position of the second storage node contact pad 26 b and the center position of the third storage node contact pad 26 f in the X direction, and the line segment that connects the center position of the first storage node contact pad 26 e and the center position of the fourth storage node contact pad 26 g in the Y direction are orthogonal to each other, and one line segment passes through the center point of the other line segment.
  • the positional relationship between the first storage node contact pad 26 c formed at one end of the active region 13 C, and the second storage node contact pad 26 d formed at the other end of the active region 13 C is equivalent to the positional relationship between the third storage node contact pad 26 b formed at one end of the active region 13 B, and the fourth storage node contact pad 26 g formed at one end of the active region 13 H.
  • the positional relationship between the first storage node contact pad 26 c and the third storage node contact pad 26 b is also equivalent to the positional relationship between the second storage node contact pad 26 d and the fourth storage node contact pad 26 g.
  • the distance L 34 between the center positions of the first and second storage node contact pads 26 c, 26 d, and the distance L 32 between the center positions of the third and fourth storage node contact pads 26 b, 26 g are set so as to be equal; and the distance L 31 between the center positions of the first and third storage node contact pads 26 c, 26 b, and the distance L 33 between the center positions of the second and fourth storage node contact pads 26 d, 26 g are set so as to be equal.
  • the line that continuously connects these center position points forms a parallelogram shape.
  • the positional relationship between the first storage node contact pad 26 a formed at one end of the active region 13 A, and the second storage node contact pad 26 b formed at one end of the active region 13 B is equivalent to the positional relationship between the third storage node contact pad 26 e formed at one end of the active region 13 F, and the fourth storage node contact pad 26 f formed at one end of the active region 13 G.
  • the positional relationship between the first storage node contact pad 26 a and the third storage node contact pad 26 e is also equivalent to the positional relationship between the second storage node contact pad 26 b and the fourth storage node contact pad 26 f.
  • the distance L 44 between the center positions of the first and second storage node contact pads 26 a, 26 d, and the distance L 42 between the center positions of the third and fourth storage node contact pads 26 e, 26 g are set so as to be equal; and the distance L 41 between the center positions of the first and third storage node contact pads 26 a, 26 e, and the distance L 43 between the center positions of the second and fourth storage node contact pads 26 b, 26 f are set so as to be equal.
  • the line that continuously connects these center position points forms the same parallelogram shape as the one shown in FIG. 21 .
  • the storage node contact pads 26 are laid out as described above, the storage node contact pads 26 are in a zigzag pattern that is uniform over the entire surface of the substrate.
  • Storage capacitors 28 are then formed above the storage node contact pads 26 , as shown in FIGS. 9 and 18 .
  • the storage capacitors 28 are formed by a process in which an interlayer insulating film 27 is formed on the entire surface of the substrate, and cylinder holes that pass through the interlayer insulating film 27 are formed above the storage node contact pads 26 , after which a lower electrode, a capacitor insulating film, and an upper electrode are deposited in sequence in the cylinder holes.
  • the lower electrodes in the storage capacitors 28 are preferably composed of HSG-Si. The use of HSG-Si enables a significant enhancement of refresh characteristics due to increased surface area of the electrode.
  • the minor axis and major axis of the bottom diameter of the cylinder holes are preferably 86 nm and 124 nm, respectively, and the minor axis and major axis of the top diameter are preferably 143 nm and 181 nm, respectively.
  • arrangement of the storage capacitors at maximum density is made possible by offsetting the center positions of the storage node contacts from the center positions of the cell contacts to create an equally spaced zigzag layout of the storage node contacts, and then also offsetting the center positions of the storage node contact pads from the center positions of the storage node contacts to create an equally spaced zigzag layout of the storage node contact pads. Further, since the pitch of the storage node capacitors in the miner axis is longer than the conventional layout, it is possible to increase the capacity of the storage capacitor and enlarge the HSG blockage margin.
  • the storage capacitors 28 were cylindrical in the abovementioned embodiment, but the shape of the storage capacitors is not limited to a cylindrical shape, and may be a columnar shape, a crown shape, or other shape.
  • bit lines 21 were also formed by etching using a silicon nitride film or other hard mask in the abovementioned embodiment, but bit lines 21 that have an adequately small trench width can be formed using a damascene process or other ultrafine machining technique.
  • an MIS capacitor that used HSG-Si in the lower electrode was described in the above-mentioned embodiment, but the present invention may also be applied to a MIM (Metal Insulator Metal) capacitor.
  • MIM Metal Insulator Metal
  • an even greater capacity than that of an MIS capacitor that uses HSG-Si can be obtained by forming the lower electrode by a CVD method using titanium nitride or another metal material, and forming an insulating film by an ALD method using aluminum oxide or hafnium oxide.
  • the lower electrode formed from titanium nitride or the like may be formed at the same time as the storage node contacts and storage node contact pads, and storage node contact pads composed of titanium nitride may be formed after the storage node contacts are formed by embedding of silicon.
  • titanium silicide must be formed in the interface between the titanium nitride and the silicon under the titanium nitride.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

a semiconductor storage device is provided with a plurality of active regions formed in the shape of a band in a semiconductor substrate; a plurality of word lines arranged at equal intervals so as to intersect the active regions; a plurality of cell contacts that includes first cell contacts formed in the active regions in the center portions in the longitudinal direction thereof, and second cell contacts formed at each end portion at both ends in the longitudinal direction; bit line contacts formed on the first cell contacts; bit lines wired so as to pass over the bit line contacts; storage node contacts formed on the second cell contacts; storage node contact pads formed on the storage node contacts; and storage capacitors formed on the storage node contact pads. The center positions of the storage node contacts are offset in a prescribed direction from the center positions of the second cell contacts. The center positions of the storage node contact pads are offset in a prescribed direction from the center positions of the storage node contacts.

Description

TECHNICAL FIELD
The present invention relates to a semiconductor storage device, and particularly relates to a DRAM (Dynamic Random Access Memory) memory cell layout.
BACKGROUND OF THE INVENTION
In DRAM, which is one type of semiconductor storage device, a memory cell composed of a single transistor and a single capacitor is disposed at the intersection of a word line and a bit line that intersect with each other. Layout systems in DRAM memory cells are classified as folded bit line systems and open bit line systems (see Japanese Laid-open Patent Application No. 2004-80009). In a folded bit line system, two bit lines that are connected to a single sense amplifier are folded at the sense amplifier so as to be wired in the same direction, and the minimum theoretical area of the memory cell is 8F2 (4F×2F), wherein “F” is the minimum feature size (half the pitch of the word lines). In an open bit line system, two bit lines that are connected to a single sense amplifier are wired so as to extend in opposite directions on the sides of the sense amplifier, and the minimum theoretical area of the memory cell is 6F2 (2F×3F).
FIG. 23A through 23F shows an example of the layout of conventional DRAM having a cell area of 6F2. A plurality of active regions 13 is formed symmetrically about a line (FIG. 23A), and word lines 14 are wired in the Y direction at intervals of 1F (FIG. 23B). Cell contacts 18 are formed in the center portions and end portions of the active regions 13 (FIG. 23C). Bit line contacts (not shown) are formed directly above the cell contacts 18 of the central portions, and bit lines are wired so as to extend in the X direction in meandering fashion over the bit line contacts so as to avoid the cell contacts 18 of the end portions (FIG. 23D). Storage node contacts 24 are formed above the cell contacts 18 disposed at the end portions of the active regions 13 (FIG. 23E). The center positions of the storage node contacts 24 are offset from the center positions of the cell contacts 18, whereby the storage node contacts 24 are arranged at equal intervals in the X direction. Storage capacitors 28 are also formed directly above the storage node contacts 24 (FIG. 23F).
Japanese Laid-open Patent Application No. 2004-80009 discloses a structure of an integrated circuit memory element in which a landing pad is formed between a contact plug and a storage capacitor. This integrated circuit memory element comprises an interlayer insulating film that is formed on a substrate and has numerous storage node contact holes arranged linearly in one direction; storage node contacts that are embedded in the storage node contact holes; an insulating film that is formed on an interlayer insulating film and has numerous landing pad holes that are arranged nonlinearly in one direction and that expose the storage node contacts; landing pads that are embedded in the landing pad holes and connected to the storage node contacts; and storage capacitors connected to the landing pads. In this structure, since landing pads are formed between the contact plugs and the storage capacitors, the storage capacitors can be arranged in a zigzag pattern in a plane even when the contact plugs are aligned in the transverse and longitudinal directions of the plane.
The layout of conventional DRAM having the memory cell area of 6F2 shown in FIGS. 23A through 23F has a region in which the storage capacitors are not arranged in zigzag fashion on the plane, and the storage capacitors cannot be placed in a perfectly zigzag arrangement. Therefore, the storage capacitors cannot be packed at maximum density.
In the structure disclosed in Japanese Laid-open Patent Application No. 2004-80009, when the contact plugs are aligned in the transverse and longitudinal directions on a plane, the storage capacitors can be arranged in zigzag fashion and packed at maximum density merely by being arranged in zigzag fashion so as to be offset from each other. However, in such a case as when the contact plugs are originally arranged in zigzag fashion in the transverse and longitudinal directions, it is difficult to pack the storage capacitors at maximum density. Since the elliptical storage capacitors have an inadequate diameter in the minor axis direction, it is impossible to increase the capacity of the capacitors. Furthermore, when the lower electrode of an MIS (Metal Insulator Silicon) capacitor is composed of HSG-Si (Hemi-Sphericai Grained poly-Si), the HSG blockage margin cannot be adequately ensured, and the cylinder holes used by the storage capacitors become blocked with HSG-Si.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor storage device in which the storage capacitors can be arranged with maximum density in a 6F2 layout, and the HSG blockage margin can be adequately ensured.
The above and other objects of the present invention can be accomplished by a semiconductor storage device comprising a semiconductor substrate; a plurality of active regions formed in the shape of a band in the semiconductor substrate; a plurality of word lines arranged at equal intervals so as to intersect the active regions; a plurality of cell contacts that includes first cell contacts formed in the active regions in the center portions in the longitudinal direction thereof, and second cell contacts formed at each end portion at both ends in the longitudinal direction; bit line contacts formed on the first cell contacts; bit lines wired so as to pass over the bit line contacts; storage node contacts formed on the second cell contacts; storage node contact pads formed on the storage node contacts; and storage capacitors formed on the storage node contact pads, wherein the center positions of the storage node contacts are offset in a prescribed direction from the center positions of the second cell contacts, and the center positions of the storage node contact pads are offset in a prescribed direction from the center positions of the storage node contacts.
According to the present invention, it is possible to arrange the storage capacitors at high density and adequately ensure the HSG blockage margin in a DRAM or other semiconductor storage device that has a 6F2 cell layout.
In the present invention, the plurality of active regions is preferably aligned with a straight line that forms a prescribed angle with the X direction intersecting the word lines, and is aligned with the Y direction parallel to the word lines, and the prescribed angle is preferably approximately 18 degrees. When the active regions are aligned with a straight line that is angled approximately 18 degrees from the X direction, the distance between the center positions of two cell contacts can be set to 4F in the X direction and 4/3F in the Y direction, and the optimum cell contact layout can be achieved in a 6F2 layout when the cell contacts are formed at both end portions of the active regions.
In the present invention, the center positions of the storage node contacts are preferably offset toward the corresponding bit line contacts in relation to the center positions of the second cell contacts, and are preferably offset so as to be at equal intervals in the X direction in relation to the center positions of the second cell contacts. All of the storage node contact pads can thereby be offset by the same amount, and it is easy to ultimately create a high-precision, high-density layout of the storage capacitors when the storage node contact pads are laid out at maximum density.
In the present invention, a first pad layout in which the positions of the storage node contact pads are offset in the direction towards the center portions of the corresponding active regions, and a second pad layout in which the positions of the storage node contact pads are offset in the direction away from the center portions of the corresponding active regions are preferably employed in alternating fashion for the plurality of active regions arranged in the Y direction. The first and second pad layouts are also preferably employed in alternating fashion for the plurality of active regions arranged on the straight line. In this case, the amount of offset of the storage node contact pads is preferably 3/4F in the X direction and 1/3F in the Y direction. Offsetting the storage node contact pads in the manner described above makes it possible to arrange the storage node contact pads in a uniform zigzag pattern, and to easily achieve a high-precision, high-density layout of the storage capacitors.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features and advantages of this invention will become more apparent by reference to the following detailed description of the invention taken in conjunction with the accompanying drawings, wherein:
FIG. 1 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming active regions 13) according to a preferred embodiment of the present invention;
FIG. 2 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming word lines 14) according to a preferred embodiment of the present invention;
FIG. 3 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming side walls 15 and silicon epitaxial layers 16) according to a preferred embodiment of the present invention;
FIG. 4 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming cell contacts 18) according to a preferred embodiment of the present invention;
FIG. 5 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming bit line contacts 20) according to a preferred embodiment of the present invention;
FIG. 6 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming bit lines 22) according to a preferred embodiment of the present invention;
FIG. 7 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming storage node contacts 24) according to a preferred embodiment of the present invention;
FIG. 8 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming storage node contact pads 26) according to a preferred embodiment of the present invention;
FIG. 9 is a schematic plan view showing the layout in the sequence of the manufacturing process of the DRAM 10 (specifically forming storage capacitors 28) according to a preferred embodiment of the present invention;
FIG. 10 is a schematic sectional view along line P-P in FIG. 1;
FIG. 11 is a schematic sectional view along line P-P in FIG. 2;
FIG. 12 is a schematic sectional view along line P-P in FIG. 3;
FIG. 13 is a schematic sectional view along line P-P in FIG. 4;
FIG. 14 is a schematic sectional view along line P-P in FIG. 5;
FIG. 15 is a schematic sectional view along line P-P in FIG. 6;
FIG. 16 is a schematic sectional view along line P-P in FIG. 7;
FIG. 17 is a schematic sectional view along line P-P in FIG. 8;
FIG. 18 is a schematic sectional view along line P-P in FIG. 9;
FIG. 19 is a schematic plan view showing details of the layout shown in FIG. 8;
FIG. 20 is a schematic plan view showing details of the layout shown in FIG. 8;
FIG. 21 is a schematic plan view showing details of the layout shown in FIG. 8;
FIG. 22 is a schematic plan view showing details of the layout shown in FIG. 8; and
FIG. 23A is a schematic plan view showing an example of the layout of conventional DRAM having a cell area of 6F2;
FIG. 23B is a schematic plan view showing an example of the layout of conventional DRAM having a cell area of 6F2;
FIG. 23C is a schematic plan view showing an example of the layout of conventional DRAM having a cell area of 6F2;
FIG. 23D is a schematic plan view showing an example of the layout of conventional DRAM having a cell area of 6F2;
FIG. 23E is a schematic plan view showing an example of the layout of conventional DRAM having a cell area of 6F2; and
FIG. 23F is a schematic plan view showing an example of the layout of conventional DRAM having a cell area of 6F2.
 DESCRIPTION OF THE PREFERRED EMBODIMENTS
Preferred embodiments of the present invention will now be described in detail hereinafter with reference to the accompanying drawings.
FIGS. 1 through 9 are schematic plan views showing the layout in the sequence of the manufacturing process of the DRAM 10 as an embodiment of the semiconductor storage device of the present invention. FIGS. 10 through 18 are schematic sectional views along line P-P in FIGS. 1 through 9, respectively.
In the manufacture of the semiconductor storage device 10, a field oxide film (element separation region) 12 is first formed by STI (Shallow Trench Isolation) or another method on a silicon substrate 11 as shown in FIGS. 1 and 10, whereby a plurality of active regions 13 is formed. The active regions 13 are substantially band-shaped regions having a prescribed length, and the plurality of active regions 13 is formed in a straight line in the longitudinal direction thereof. The longitudinal direction of the active regions 13 is angled approximately 18 degrees from the X direction, wherein the X direction is the direction orthogonal to the wiring direction of the word lines described hereinafter. When the active regions are aligned with a straight line that is at an angle of approximately 18 degrees from the X direction, the X direction component of the distance between the center positions of two cell contacts formed at end portions on both ends of the active regions can be set to 4F, and the Y direction component can be set to 4/3F in the formation of the cell contacts described hereinafter. The optimum cell contact layout can therefore be achieved in a 6F2 layout. When the wiring direction of the word lines is the Y direction, the active regions 13 are arranged at equal intervals in the Y direction. The width of the active regions 13 is about 1F (wherein F is the minimum feature size), and the length is about 5.1F. The distance between the centers of active regions 13 that are adjacent in the Y direction is set to 2F.
As shown in FIGS. 2 and 11, a plurality of word lines 14 is then formed on the silicon substrate 11 in which the active regions 13 are formed. The word lines 14 are wired in the Y direction, and the width of the word lines 14 and the space between adjacent word lines 14, 14 are both set to 1F. Two word lines 14L, 14R intersect in a single active region 13. One word line 14L passes between the center portion and one end portion of the active region 13, and the other word line 14R passes between the center portion and the other end portion of the active region 13. One of three word lines 14 does not intersect with the active region 13, and is a dummy word line 14D that does not actually function as a word line. In the formation of the word lines 14, gate oxide films 14a are first formed on the entire surface of the active region 13, after which conducting films 14b formed by layering a polysilicon film, a tungsten silicide film, a tungsten nitride film, and a tungsten film in sequence are formed on the gate oxide films 14a, and gate cap insulating films 14c composed of silicon nitride are then formed. The word lines 14 are then formed by patterning the multilayer film in linear fashion.
As shown in FIGS. 3 and 12, side walls 15 are then formed on both sides of the word lines 14, and silicon epitaxial layers 16 are formed in the exposed portions of the active regions 13. The side walls 15 are formed by a process in which a silicon nitride film having a thickness of about 26 nm is formed on the entire surface of the substrate, and the silicon nitride film is then etched back. The end portions and the center portions of the active regions 13, which are the exposed portions, are then grown epitaxially, and the silicon epitaxial layers 16 are formed. The width of the silicon epitaxial layers 16 is preferably about 60 nm, the width thereof in the Y direction is preferably about 168 nm, and the separation margin between silicon epitaxial layers 16, 16 that are adjacent in the Y direction is preferably about 30 nm.
As shown in FIGS. 4 and 13, cell contacts 18 are formed above the center portions and the portions at both ends of the active regions 13. The cell contacts 18 are formed by a process in which an interlayer insulating film 17 composed of BPSG (Boro-Phospho Silicate Glass) having a prescribed thickness is formed on the entire surface of the substrate, contact holes that pass through the interlayer insulating film 17 are formed in the center portions and the portions at both ends of the active regions 13, and DOPOS (Doped Poly-Silicon) or another conductive material is filled into the contact holes. The contact holes are formed by photolithography and etching using a resist mask. The cell contacts 18 are formed by a process in which DOPOS is deposited on the entire surface of the substrate, including the interior of the contact holes, and the DOPOS is then polished by CMP so as to remain only in the interior of the contact holes.
The X direction component of the distance between the center portions of the cell contacts 18b, 18b formed at the portions at both ends of the active regions 13 is set to 4F, and the Y direction component is set to 4/3F. The cell contacts 18a formed in the center portions of the active regions 13 are provided in the middle position between the cell contacts 18b, 18b of the portions at both ends. The distance between the centers of cell contacts 18, 18 that are adjacent in the Y direction is 2F. The top diameter of the cell contacts 18 is preferably about 140 nm, and the bottom diameter is preferably about 93 nm.
As shown in FIGS. 5 and 14, bit line contacts 20 are formed above the cell contacts (hereinafter referred to as first cell contacts) formed in the center portions of each of the active regions 13. The bit line contacts 20 are formed by a process in which an interlayer insulating film 19 composed of BPSG having a prescribed thickness is formed on the entire surface of the substrate, and contact holes that pass through the interlayer insulating film 19 are formed above the first cell contacts 18a, after which tungsten or another conductive material is filled into the contact holes. The center positions of the bit line contacts 20 coincide with the center positions of the first cell contacts 18a. The contact holes are formed by photolithography and etching using a resist mask. The bit line contacts 20 are formed by a process in which tungsten is deposited on the entire surface of the substrate, including the interior of the contact holes, and the tungsten is then polished by CMP so as to remain only in the interior of the contact holes.
Since the center positions of the bit line contacts 20 coincide herein with the center positions of the first cell contacts 18a, the distance between the centers of two bit line contacts 20, 20 that are adjacent in the Y direction is 2F. The top diameter (diameter) of the bit line contacts 20 is preferably about 120 nm, and the bottom diameter (diameter) is preferably about 93 nm.
A plurality of bit lines 22 is then wired in the X direction, as shown in FIGS. 6 and 15. The bit lines 22 pass through over the bit line contacts 20, and are wired in meandering fashion so as not to be above the cell contacts (hereinafter referred to as second cell contacts) 18b formed in the portions at both ends of the active regions 13. The bit lines 22 are formed by a process in which a tungsten nitride film 22a and a tungsten film 22b are deposited in sequence on the entire surface of the substrate by sputtering, after which the films are etched using a silicon nitride film or other hard mask. Bit lines 22 having a line width that is adequately smaller than the minimum feature size F can thereby be formed, and a margin of deviation with respect to the bit line contacts 20 can be adequately maintained. The widest distance between bit lines 22 that are adjacent in the Y direction is 2F, and the narrowest distance is 1.9F. The meandering width of the bit lines 22 is set to 2/3F, and the fold angle for meandering is set to approximately 18 degrees, so as to be the same as the tilt of the active regions 13. Accordingly, the bit lines 22 have a portion that extends parallel to the active regions 13.
As shown in FIGS. 7 and 16, storage node contacts 24 are formed above the second cell contacts 18b. In the formation of the storage node contacts 24, an interlayer insulating film 23 composed of a silicon oxide film having a prescribed thickness is formed on the entire surface of the substrate, and elliptical contact holes are formed so as to pass through the interlayer insulating film 23 above the second cell contacts 18b. The storage node contacts 24 are then formed by a process in which DOPOS or another conductive material is deposited on the entire surface of the substrate, including the interior of the contact holes, and the conducting material is then polished by CMP so as to remain only in the interior of the contact holes. The center positions of the storage node contacts 24 do not coincide with the center positions of the second cell contacts 18b, but are offset 0.5F in the X direction towards the center portions of the corresponding active regions 13. As a result, the storage node contacts 24 are arranged at equal intervals in the X direction. The distance between the centers of two storage node contacts 24, 24 that are adjacent in the Y direction is 2.0F, and the other distance between the centers of two storage node contacts 24, 24 that are adjacent in the tilted direction is about 3.07F. The minor axis and major axis of the bottom diameter of the storage node contacts 24 are preferably 70 nm and 120 nm, respectively, and the minor axis and major axis of the top diameter are preferably 97 nm and 138 nm, respectively.
As shown in FIGS. 8 and 17, elliptical storage node contact pads 26 are formed above the storage node contacts 24. The storage node contact pads 26 are formed by depositing DOPOS or another conductive material on the interlayer insulating film 23 and the storage node contacts 24, and then etching the conductive material by using a resist mask. In the stage shown in FIGS. 7 and 16, the storage node contact pads 26 and the storage node contacts 24 may be formed simultaneously by a process in which contact holes that pass through the interlayer insulating film 23 are formed, DOPOS is formed on the entire surface so as to fill the contact holes, and etching is then performed using a resist mask composed of a pattern for the storage node contact pads. The area of the storage node contact pads 26 is wider than the area of the storage node contacts 24, and the lengths of the minor axis and major axis thereof are set to 135 nm and 170 nm, respectively. At this time, the center positions of the storage node contact pads 26 do not coincide with the center positions of the storage node contacts 24, and are offset further to the inside (in the direction that approaches the center portions of the corresponding active regions 13) or further to the outside (in the direction away from the center portions of the corresponding active regions 13) than the center positions of the storage node contacts 24.
The layout of the storage node contact pads 26 is a combination of a first pad layout in which two storage node contact pads 26 that correspond to the same active region are offset (to the inside) in the direction that approaches the center portions of the active regions 13, and a second pad layout in which two storage node contact pads 26 that correspond to the same active region are offset (to the outside) in the direction away from the center portions of the active regions 13. The first pad layout and the second pad layout are employed in alternating fashion for the plurality of active regions 13 arranged in the Y direction. For example, in the first, second, and third active regions 13A through 13C in FIG. 8 that are continuous in the Y direction, the storage node contact pads 26, 26 based on the first active region 13A have the first pad layout that is offset to the inside; the storage node contact pads 26, 26 based on the second active region 13B have the second pad layout that is offset to the outside; and the storage node contact pads 26, 26 based on the third active region 13C have the first pad layout that is offset to the inside.
In the first and second pad layouts described above, the center positions of the storage node contact pads 26 are offset in a tilted direction. In other words, the offset direction has both an X direction component and a Y direction component. In the case of the first pad layout, the center positions of the storage node contact pads 26 are offset 3/4F in the direction that approaches the center portions of the corresponding active regions with respect to the X direction, and are offset 1/3F in the direction away from the center portions of the corresponding active regions 13 with respect to the Y direction. In the case of the second pad layout, the center positions of the storage node contact pads 26 are offset 3/4F in the direction away from the center portions of the corresponding active regions 13 with respect to the X direction, and are offset 1/3F in the direction away from the center portions of the corresponding active regions 13 with respect to the Y direction. The distance between the centers of two storage node contact pads 26 that are adjacent in the X direction is thereby set to 3F, and the interval at which the storage node contact pads 26 are arranged in the Y direction is set to 2F. At this time, the distance between the centers of two storage node contact pads 26 that are adjacent in the tilted direction is 2.5F.
FIGS. 19 through 22 are schematic plan views showing details of the layout shown in FIG. 8.
As shown in FIG. 19, in the active regions 13A through 13C that are continuous in the Y direction, the positional relationship between the first storage node contact pad 26a formed at one end portion of the active region 13A and the second storage node contact pad 26b formed at one end of the active region 13B is equivalent to the positional relationship between the third and fourth storage node contact pads 26c and 26d formed at the respective end portions of the active region 13C. The positional relationship between the first storage node contact pad 26a and the third storage node contact pad 26c is also equivalent to the positional relationship between the second storage node contact pad 26b and the fourth storage node contact pad 26d. Specifically, the distance L11 between the center positions of the first and second storage node contact pads 26a, 26b; the distance L12 between the center positions of the second and fourth storage node contact pads 26b, 26d; the distance L13 between the center positions of the fourth and third storage node contact pads 26d, 26c; and the distance L14 between the center positions of the third and first storage node contact pads 26c, 26a are all set so as to be equal, and the line that continuously connects these center position points forms a diamond shape. From another perspective, the line segment that connects the center position of the second storage node contact pad 26b and the center position of the third storage node contact pad 26c in the X direction, and the line segment that connects the center position of the first storage node contact pad 26a and the center position of the fourth storage node contact pad 26d in the Y direction are orthogonal to each other, and one line segment passes through the center point of the other line segment.
As shown in FIG. 20, in the active regions 13F through 13H that are continuous in the Y direction, and in the active region 13B that is adjacent in the longitudinal direction to the active region 13G, the positional relationship between the first storage node contact pad 26e formed at one end of the active region 13F, and the second storage node contact pad 26f formed at one end of the active region 13G is equivalent to the positional relationship between the third storage node contact pad 26b formed at one end of the active region 13B, and the fourth storage node contact pad 26g formed at one end of the active region 13H. The positional relationship between the first storage node contact pad 26e and the third storage node contact pad 26b is also equivalent to the positional relationship between the second storage node contact pad 26f and the fourth storage node contact pad 26g. Specifically, the distance L21 between the center positions of the first and second storage node contact pads 26e, 26f; the distance L22 between the center positions of the second and fourth storage node contact pads 26f, 26g; the distance L23 between the center positions of the fourth and third storage node contact pads 26g, 26b; and the distance L24 between the center positions of the third and first storage node contact pads 2 Gb, 26e are all set so as to be equal, and the line that continuously connects these center position points forms the same diamond shape as the one shown in FIG. 19. From another perspective, the line segment that connects the center position of the second storage node contact pad 26b and the center position of the third storage node contact pad 26f in the X direction, and the line segment that connects the center position of the first storage node contact pad 26e and the center position of the fourth storage node contact pad 26g in the Y direction are orthogonal to each other, and one line segment passes through the center point of the other line segment.
As shown in FIG. 21, in the active regions 13B and 13C that are continuous in the Y direction, and in the active region 13H that is adjacent in the longitudinal direction to the active region 13C, the positional relationship between the first storage node contact pad 26c formed at one end of the active region 13C, and the second storage node contact pad 26d formed at the other end of the active region 13C is equivalent to the positional relationship between the third storage node contact pad 26b formed at one end of the active region 13B, and the fourth storage node contact pad 26g formed at one end of the active region 13H. The positional relationship between the first storage node contact pad 26c and the third storage node contact pad 26b is also equivalent to the positional relationship between the second storage node contact pad 26d and the fourth storage node contact pad 26g. Specifically, the distance L34 between the center positions of the first and second storage node contact pads 26c, 26d, and the distance L32 between the center positions of the third and fourth storage node contact pads 26b, 26g are set so as to be equal; and the distance L31 between the center positions of the first and third storage node contact pads 26c, 26b, and the distance L33 between the center positions of the second and fourth storage node contact pads 26d, 26g are set so as to be equal. The line that continuously connects these center position points forms a parallelogram shape.
As shown in FIG. 22, in the active regions 13A and 13B that are continuous in the Y direction, in the active region 13F that is adjacent in the longitudinal direction to the active region 13A, and in the active region 13G that is adjacent in the Y direction to the active region 13F and adjacent in the longitudinal direction to the active region 13B, the positional relationship between the first storage node contact pad 26a formed at one end of the active region 13A, and the second storage node contact pad 26b formed at one end of the active region 13B is equivalent to the positional relationship between the third storage node contact pad 26e formed at one end of the active region 13F, and the fourth storage node contact pad 26f formed at one end of the active region 13G. The positional relationship between the first storage node contact pad 26a and the third storage node contact pad 26e is also equivalent to the positional relationship between the second storage node contact pad 26b and the fourth storage node contact pad 26f. Specifically, the distance L44 between the center positions of the first and second storage node contact pads 26a, 26d, and the distance L42 between the center positions of the third and fourth storage node contact pads 26e, 26g are set so as to be equal; and the distance L41 between the center positions of the first and third storage node contact pads 26a, 26e, and the distance L43 between the center positions of the second and fourth storage node contact pads 26b, 26f are set so as to be equal. The line that continuously connects these center position points forms the same parallelogram shape as the one shown in FIG. 21.
When the storage node contact pads 26 are laid out as described above, the storage node contact pads 26 are in a zigzag pattern that is uniform over the entire surface of the substrate.
Storage capacitors 28 are then formed above the storage node contact pads 26, as shown in FIGS. 9 and 18. The storage capacitors 28 are formed by a process in which an interlayer insulating film 27 is formed on the entire surface of the substrate, and cylinder holes that pass through the interlayer insulating film 27 are formed above the storage node contact pads 26, after which a lower electrode, a capacitor insulating film, and an upper electrode are deposited in sequence in the cylinder holes. In the present embodiment, the lower electrodes in the storage capacitors 28 are preferably composed of HSG-Si. The use of HSG-Si enables a significant enhancement of refresh characteristics due to increased surface area of the electrode. Since the center positions of the storage capacitors 28 coincide with the center positions of the storage node contact pads 26, the distance between the centers of two storage capacitors 28 (and storage node contact pads 26) that are adjacent in the X direction is 3.0F, and the other distance between the centers of two cylinder- type storage capacitors 28, 28 that are adjacent in the tilted direction is 2.5F. The minor axis and major axis of the bottom diameter of the cylinder holes are preferably 86 nm and 124 nm, respectively, and the minor axis and major axis of the top diameter are preferably 143 nm and 181 nm, respectively.
According to the present embodiment as described above, arrangement of the storage capacitors at maximum density is made possible by offsetting the center positions of the storage node contacts from the center positions of the cell contacts to create an equally spaced zigzag layout of the storage node contacts, and then also offsetting the center positions of the storage node contact pads from the center positions of the storage node contacts to create an equally spaced zigzag layout of the storage node contact pads. Further, since the pitch of the storage node capacitors in the miner axis is longer than the conventional layout, it is possible to increase the capacity of the storage capacitor and enlarge the HSG blockage margin.
Preferred embodiment of the present invention has been explained above, but the present invention is not limited thereto. A variety of modifications are possible within the scope of the main points of the present invention, and it shall be apparent that these modifications are also included within the scope of the present invention.
For example, the storage capacitors 28 were cylindrical in the abovementioned embodiment, but the shape of the storage capacitors is not limited to a cylindrical shape, and may be a columnar shape, a crown shape, or other shape.
The bit lines 21 were also formed by etching using a silicon nitride film or other hard mask in the abovementioned embodiment, but bit lines 21 that have an adequately small trench width can be formed using a damascene process or other ultrafine machining technique.
An example of an MIS capacitor that used HSG-Si in the lower electrode was described in the above-mentioned embodiment, but the present invention may also be applied to a MIM (Metal Insulator Metal) capacitor. In the case of an MIM capacitor, an even greater capacity than that of an MIS capacitor that uses HSG-Si can be obtained by forming the lower electrode by a CVD method using titanium nitride or another metal material, and forming an insulating film by an ALD method using aluminum oxide or hafnium oxide. The lower electrode formed from titanium nitride or the like may be formed at the same time as the storage node contacts and storage node contact pads, and storage node contact pads composed of titanium nitride may be formed after the storage node contacts are formed by embedding of silicon. However, in any case, titanium silicide must be formed in the interface between the titanium nitride and the silicon under the titanium nitride.

Claims (26)

What is claimed is:
1. A semiconductor storage device, comprising:
a semiconductor substrate;
a plurality of active regions formed in the shape of a band in the semiconductor substrate;
a plurality of word lines arranged at equal intervals so as to intersect the active regions;
a plurality of cell contacts that includes first cell contacts formed in the active regions in the center portions in the longitudinal direction thereof, and second cell contacts formed at each end portion at both ends in the longitudinal direction;
bit line contacts formed on the first cell contacts;
bit lines wired so as to pass over the bit line contacts;
storage node contacts formed on the second cell contacts;
storage node contact pads formed on the storage node contacts; and
storage capacitors formed on the storage node contact pads,
wherein the center positions of the storage node contacts are offset in a prescribed X direction from the center positions of the second cell contacts, and the center positions of the storage node contact pads are offset in a different prescribed direction from the center positions of the storage node contacts that is not parallel to the X direction,
wherein the plurality of active regions is preferably aligned with a straight line that forms a prescribed angle with the X direction intersecting the word lines, and is aligned with the Y direction parallel to the word lines.
2. The semiconductor device as claimed in claim 1, wherein the prescribed angle is preferably approximately 18 degrees.
3. The semiconductor device as claimed in claim 1, wherein the center positions of the storage node contacts are offset toward the corresponding bit line contacts in relation to the center positions of the second cell contacts.
4. The semiconductor device as claimed in claim 3, wherein the center positions of the storage node contacts are offset in the X direction in relation to the center positions of the second cell contacts.
5. The semiconductor device as claimed in claim 4, wherein the center positions of the storage node contacts are offset so as to be at equal intervals in the X direction.
6. The semiconductor device as claimed in claim 1, wherein a first pad layout in which the positions of the storage node contact pads are offset in the direction towards the center portions of the corresponding active regions, and a second pad layout in which the positions of the storage node contact pads are offset in the direction away from the center portions of the corresponding active regions are employed in alternating fashion for the plurality of active regions arranged in the Y direction.
7. The semiconductor device as claimed in claim 1, wherein a first pad layout in which the positions of the storage node contact pads are offset in the direction towards the center portions of the corresponding active regions, and a second pad layout in which the positions of the storage node contact pads are offset in the direction away from the center portions of the corresponding active regions are employed in alternating fashion for the plurality of active regions arranged on the straight line.
8. The semiconductor device as claimed in claim 1, wherein the amount of offset of the storage node contact pads is 3/4F in the X direction and 1/3F in the Y direction.
9. The semiconductor device as claimed in claim 1, the distance between the centers of two storage node contact pads that are adjacent in the X direction is set to 3F, and the interval at which the storage node contact pads are arranged in the Y direction is set to 2F.
10. The semiconductor device as claimed in claim 1, wherein the active regions includes the first, second and third active regions that are continuous in the Y direction, and
the positional relationship between the first storage node contact pad formed at one end portion of the first active region and the second storage node contact pad formed at one end of the second active region is equivalent to the positional relationship between the third and fourth storage node contact pads formed at the respective end portions of the third active region.
11. The semiconductor device as claimed in claim 10, wherein the positional relationship between the first storage node contact pad and the third storage node contact pad is equivalent to the positional relationship between the second storage node contact pad and the fourth storage node contact pad.
12. The semiconductor device as claimed in claim 1, wherein the active regions includes the first, second and third active regions that are continuous in the Y direction, and the fourth active region that is adjacent in the longitudinal direction to the second active region, and
the positional relationship between the first storage node contact pad formed at one end of the first active region, and the second storage node contact pad formed at one end of the fourth active region is equivalent to the positional relationship between the third storage node contact pad formed at one end of the second active region, and the fourth storage node contact pad formed at one end of the third active region.
13. The semiconductor device as claimed in claim 12, wherein the positional relationship between the first storage node contact pad and the second storage node contact pad is equivalent to the positional relationship between the third storage node contact pad and the fourth storage node contact pad.
14. The semiconductor device as claimed in claim 10, wherein the distance between the center positions of the first and second storage node contact pads, the distance between the center positions of the second and fourth storage node contact pads, the distance between the center positions of the fourth and third storage node contact pads, and the distance between the center positions of the third and first storage node contact pads are all set so as to be equal.
15. The semiconductor device as claimed in claim 10, wherein the line that continuously connects the center position point of the first, second, third and fourth storage node contact pads forms a diamond shape.
16. The semiconductor device as claimed in claim 1, wherein the active regions includes the first and second active regions that are continuous in the Y direction, and the third active region that is adjacent in the longitudinal direction to the first active region, and
the positional relationship between the first and second storage node contact pads formed at both ends of the first active region is equivalent to the positional relationship between the third storage node contact pad formed at one end of the second active region, and the fourth storage node contact pad formed at one end of the third active region.
17. The semiconductor device as claimed in claim 16, wherein the positional relationship between the first storage node contact pad and the third storage node contact pad is equivalent to the positional relationship between the second storage node contact pad and the fourth storage node contact pad.
18. The semiconductor device as claimed in claim 1, wherein the active regions includes the first and second active regions that are continuous in the Y direction, the third active region that is adjacent in the longitudinal direction to the first active region, and the fourth active region that is adjacent in the longitudinal direction to the second active region and in the Y direction to the third active region, and
the positional relationship between the first storage node contact pad formed at one end of the first active region, and the second storage node contact pad formed at one end of the second active region is equivalent to the positional relationship between the third storage node contact pad formed at one end of the third active region, and the fourth storage node contact pad formed at one end of the fourth active region.
19. The semiconductor device as claimed in claim 18, wherein the positional relationship between the first storage node contact pad and the third storage node contact pad is equivalent to the positional relationship between the second storage node contact pad and the fourth storage node contact pad.
20. The semiconductor device as claimed in claim 16, wherein the line that continuously connects these center position points of the first, second, third and fourth storage node contact pads forms a parallelogram shape.
21. The semiconductor device as claimed in claim 2, wherein the bit lines have a portion that extends parallel to the straight line.
22. A semiconductor storage device, comprising:
a semiconductor substrate;
a plurality of active regions arranged in a prescribed direction;
a plurality of word lines wired in the prescribed direction so as to intersect the active regions;
a plurality of cell contacts that includes first cell contacts formed in the active regions in the center portions in the longitudinal direction thereof, and second cell contacts formed at each end portion at both ends in the longitudinal direction;
bit line contacts formed on the first cell contacts;
bit lines wired so as to pass over the bit line contacts;
storage node contacts formed on the second cell contacts;
storage node contact pads formed on the storage node contacts; and
storage capacitors formed on the storage node contact pads,
wherein a first pad layout in which the positions of the storage node contact pads are offset in the direction towards the center portions of the corresponding active regions, and a second pad layout in which the positions of the storage node contact pads are offset in the direction away from the center portions of the corresponding active regions are employed in alternating fashion for the plurality of active regions arranged in the prescribed direction.
23. The semiconductor device as claimed in claim 22, wherein the longitudinal direction of the active regions is angled the prescribed degrees from the direction orthogonal to the prescribed direction.
24. The semiconductor device as claimed in claim 23, wherein the prescribed angle is approximately 18 degrees.
25. A semiconductor storage device, comprising:
a semiconductor substrate;
a plurality of active regions formed in the shape of a band in the semiconductor substrate;
a plurality of word lines arranged at equal intervals so as to intersect the active regions;
a plurality of cell contacts that includes first cell contacts formed in the active regions in the center portions in the longitudinal direction thereof, and second cell contacts formed at each end portion at both ends in the longitudinal direction;
bit line contacts formed on the first cell contacts;
bit lines wired so as to pass over the bit line contacts;
storage node contacts formed on the second cell contacts;
storage node contact pads formed on the storage node contacts; and
storage capacitors formed on the storage node contact pads,
wherein the center positions of the storage node contacts are offset in a prescribed X direction from the center positions of the second cell contacts, and the center positions of the storage node contact pads are offset in a different prescribed direction from the center positions of the storage node contacts that is not parallel to the X direction,
wherein the plurality of active regions is preferably aligned with a straight line that forms a prescribed angle with the X direction intersecting the word lines, the prescribed angle being greater than 0° and less than 90°.
26. The semiconductor device as claimed in claim 1, wherein the prescribed angle is greater than 0° and less than 90°.
US14/152,259 2006-04-13 2014-01-10 Semiconductor storage device Active 2030-09-19 USRE47240E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/152,259 USRE47240E1 (en) 2006-04-13 2014-01-10 Semiconductor storage device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2006111009A JP5694625B2 (en) 2006-04-13 2006-04-13 Semiconductor memory device
JP2006-111009 2006-04-13
US11/686,885 US8093724B2 (en) 2006-04-13 2007-03-15 Semiconductor storage device
US14/152,259 USRE47240E1 (en) 2006-04-13 2014-01-10 Semiconductor storage device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/686,885 Reissue US8093724B2 (en) 2006-04-13 2007-03-15 Semiconductor storage device

Publications (1)

Publication Number Publication Date
USRE47240E1 true USRE47240E1 (en) 2019-02-12

Family

ID=38604028

Family Applications (3)

Application Number Title Priority Date Filing Date
US11/686,885 Ceased US8093724B2 (en) 2006-04-13 2007-03-15 Semiconductor storage device
US13/311,720 Active US8378499B2 (en) 2006-04-13 2011-12-06 Semiconductor storage device
US14/152,259 Active 2030-09-19 USRE47240E1 (en) 2006-04-13 2014-01-10 Semiconductor storage device

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US11/686,885 Ceased US8093724B2 (en) 2006-04-13 2007-03-15 Semiconductor storage device
US13/311,720 Active US8378499B2 (en) 2006-04-13 2011-12-06 Semiconductor storage device

Country Status (4)

Country Link
US (3) US8093724B2 (en)
JP (1) JP5694625B2 (en)
CN (1) CN101055871B (en)
TW (1) TWI355736B (en)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100649313B1 (en) * 2005-12-29 2006-11-24 동부일렉트로닉스 주식회사 Dual metal line structure in semiconductor device and method of fabricating the same
TWI340435B (en) * 2007-07-11 2011-04-11 Nanya Technology Corp Dynamic random access memory with electrostatic discharge structure and method for manufacturing the same
JPWO2009125805A1 (en) 2008-04-09 2011-08-04 株式会社ニコン Surface inspection method and surface inspection apparatus
JP5693809B2 (en) 2008-07-04 2015-04-01 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Semiconductor device and manufacturing method thereof
JP2010123664A (en) 2008-11-18 2010-06-03 Elpida Memory Inc Nonvolatile memory device
JP5679628B2 (en) 2008-12-16 2015-03-04 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Semiconductor device and manufacturing method thereof
JP2010161173A (en) * 2009-01-07 2010-07-22 Renesas Electronics Corp Semiconductor storage device
KR101565797B1 (en) * 2009-02-16 2015-11-05 삼성전자주식회사 Semiconductor device having contact plug
JP2010232408A (en) 2009-03-27 2010-10-14 Elpida Memory Inc Semiconductor device and method of manufacturing the same
KR101616044B1 (en) * 2009-07-03 2016-04-28 삼성전자주식회사 Semiconductor device comprising landing pad formed by electroless plating
KR101179265B1 (en) * 2009-09-14 2012-09-03 에스케이하이닉스 주식회사 Method for fabricating storage node electrode in semiconductor device
CN102024809B (en) * 2009-09-15 2013-05-08 中芯国际集成电路制造(上海)有限公司 Integrated circuit device with capacitor structure and manufacturing method thereof
CN102456396A (en) * 2010-10-26 2012-05-16 中国科学院上海微系统与信息技术研究所 Bit line structure of phase change memory array
JP5621541B2 (en) * 2010-11-19 2014-11-12 ソニー株式会社 Storage device
KR101168391B1 (en) 2010-12-17 2012-07-25 에스케이하이닉스 주식회사 Semiconductor device
JP2012234964A (en) 2011-04-28 2012-11-29 Elpida Memory Inc Semiconductor device and manufacturing method of the same
JP2012248686A (en) * 2011-05-27 2012-12-13 Elpida Memory Inc Semiconductor device and manufacturing method of the same
KR101883294B1 (en) 2012-03-28 2018-07-30 삼성전자주식회사 Method for forming fine patterns of semiconductor device
JP2014022388A (en) 2012-07-12 2014-02-03 Ps4 Luxco S A R L Semiconductor device and method for manufacturing the same
TWI488288B (en) * 2012-11-07 2015-06-11 Inotera Memories Inc Semiconductor layout structure
KR102071528B1 (en) * 2013-08-12 2020-03-02 삼성전자주식회사 Semiconductor device comprising one-body type support
KR102079283B1 (en) * 2013-10-15 2020-02-19 삼성전자 주식회사 Integrated circuit device having through-silicon via structure and method of manufacturing the same
KR102185661B1 (en) 2014-02-07 2020-12-02 삼성전자주식회사 Semiconductor device having a bit line structure and a storage contact plug
JP2015211108A (en) * 2014-04-25 2015-11-24 ルネサスエレクトロニクス株式会社 Semiconductor device
KR102214506B1 (en) 2014-08-21 2021-02-09 삼성전자 주식회사 Semiconductor device having contact plugs and method for manufacturing the same
US9704871B2 (en) 2014-09-18 2017-07-11 Micron Technology, Inc. Semiconductor device having a memory cell and method of forming the same
JP2016066775A (en) 2014-09-18 2016-04-28 マイクロン テクノロジー， インク． Semiconductor device and manufacturing method thereof
CN105720059B (en) * 2014-12-02 2018-09-14 华邦电子股份有限公司 Dynamic random access memory
JP6664155B2 (en) * 2015-06-11 2020-03-13 株式会社ミツトヨ Optical encoder
CN106783743B (en) * 2015-11-23 2019-07-26 华邦电子股份有限公司 Memory device and its manufacturing method
CN107093604A (en) * 2017-04-27 2017-08-25 睿力集成电路有限公司 Dynamic random access memory and its manufacture method
US10217748B2 (en) * 2017-05-25 2019-02-26 Winbond Electronics Corp. Dynamic random access memory and method of manufacturing the same
KR102411071B1 (en) 2017-05-29 2022-06-21 삼성전자주식회사 Semiconductor device
CN107706180A (en) * 2017-10-20 2018-02-16 睿力集成电路有限公司 Memory and preparation method thereof, semiconductor devices
CN109698193B (en) * 2017-10-24 2024-02-09 长鑫存储技术有限公司 Array structure of semiconductor memory
CN107845633B (en) * 2017-10-30 2023-05-12 长鑫存储技术有限公司 Memory and manufacturing method thereof
US10692872B2 (en) * 2017-12-12 2020-06-23 Varian Semiconductor Equipment Associates, Inc. Device structure for forming semiconductor device having angled contacts
CN108831884A (en) * 2018-06-08 2018-11-16 长鑫存储技术有限公司 Memory construction and preparation method thereof
KR102581399B1 (en) 2018-11-02 2023-09-22 삼성전자주식회사 Semiconductor memory device
CN111446236B (en) * 2019-01-16 2023-08-08 中芯国际集成电路制造(上海)有限公司 Ribbon cell layout and memory layout, ribbon cell structure and memory
US11107785B2 (en) * 2019-09-25 2021-08-31 Nanya Technology Corporation Semiconductor device with a plurality of landing pads and method for fabricating the same
KR20210047125A (en) 2019-10-21 2021-04-29 삼성전자주식회사 Semiconductor memory devices
CN114141773A (en) * 2020-05-28 2022-03-04 福建省晋华集成电路有限公司 Dynamic random access memory structure
CN111900169A (en) * 2020-08-06 2020-11-06 无锡拍字节科技有限公司 Memory with elliptical capacitor cell array and manufacturing method thereof
CN113540094A (en) * 2021-07-15 2021-10-22 芯盟科技有限公司 Semiconductor structure and forming method thereof

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11297954A (en) 1998-04-09 1999-10-29 Nec Corp Semiconductor storage device
US6211544B1 (en) * 1999-03-18 2001-04-03 Infineon Technologies North America Corp. Memory cell layout for reduced interaction between storage nodes and transistors
JP2001185701A (en) 1999-12-27 2001-07-06 Hitachi Ltd Semiconductor integrated circuit device and method of manufacturing it
US6396096B1 (en) * 2000-06-21 2002-05-28 International Business Machines Corporation Design layout for a dense memory cell structure
US20030235946A1 (en) * 2002-06-21 2003-12-25 Kyu-Hyun Lee Methods of forming integrated circuit memory devices that include a plurality of landing pad holes that are arranged in a staggered pattern and integrated circuit memory devices formed thereby
US20040004257A1 (en) * 2002-07-08 2004-01-08 Sang-Hyeon Lee Dynamic random access memory cells having laterally offset storage nodes, and fabrication methods thereof
JP2004193608A (en) 2002-12-10 2004-07-08 Samsung Electronics Co Ltd Method for manufacturing semiconductor device including contact expanded in direction of bit line to enhance contact area with storage electrode
US20040229428A1 (en) 2003-05-15 2004-11-18 Cho Chang-Hyun Semiconductor memory device including storage nodes and resistors and method of manufacturing the same
JP2005293759A (en) 2004-04-02 2005-10-20 Hitachi Ltd Semiconductor memory apparatus
US7183603B2 (en) * 2004-03-31 2007-02-27 Samsung Electronics Co., Ltd. Semiconductor device including square type storage node and method of manufacturing the same
US7547936B2 (en) * 2004-10-08 2009-06-16 Samsung Electronics Co., Ltd. Semiconductor memory devices including offset active regions

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2792211B2 (en) * 1990-07-06 1998-09-03 日本電気株式会社 Semiconductor storage device
JP4150154B2 (en) * 2000-08-21 2008-09-17 株式会社ルネサステクノロジ Semiconductor integrated circuit device
JP4653426B2 (en) * 2004-06-25 2011-03-16 セイコーエプソン株式会社 Semiconductor device

Patent Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11297954A (en) 1998-04-09 1999-10-29 Nec Corp Semiconductor storage device
US6211544B1 (en) * 1999-03-18 2001-04-03 Infineon Technologies North America Corp. Memory cell layout for reduced interaction between storage nodes and transistors
JP2001185701A (en) 1999-12-27 2001-07-06 Hitachi Ltd Semiconductor integrated circuit device and method of manufacturing it
US6396096B1 (en) * 2000-06-21 2002-05-28 International Business Machines Corporation Design layout for a dense memory cell structure
US6890841B2 (en) * 2002-06-21 2005-05-10 Samsung Electronics Co., Ltd. Methods of forming integrated circuit memory devices that include a plurality of landing pad holes that are arranged in a staggered pattern and integrated circuit memory devices formed thereby
US20030235946A1 (en) * 2002-06-21 2003-12-25 Kyu-Hyun Lee Methods of forming integrated circuit memory devices that include a plurality of landing pad holes that are arranged in a staggered pattern and integrated circuit memory devices formed thereby
JP2004080009A (en) 2002-06-21 2004-03-11 Samsung Electronics Co Ltd Semiconductor memory device and method of manufacturing the same
US20040004257A1 (en) * 2002-07-08 2004-01-08 Sang-Hyeon Lee Dynamic random access memory cells having laterally offset storage nodes, and fabrication methods thereof
CN1495906A (en) 2002-07-08 2004-05-12 ���ǵ�����ʽ���� Dynamic random access emory unit with lateral deviation sotrage node and its makin method
US7119389B2 (en) * 2002-07-08 2006-10-10 Samsung Electronics Co., Ltd. Dynamic random access memory cells having laterally offset storage nodes
JP2004193608A (en) 2002-12-10 2004-07-08 Samsung Electronics Co Ltd Method for manufacturing semiconductor device including contact expanded in direction of bit line to enhance contact area with storage electrode
KR20040098691A (en) 2003-05-15 2004-11-26 삼성전자주식회사 Semiconductor memory device comprising storage nodes and resistors and manufacturing method for the same
US7074667B2 (en) * 2003-05-15 2006-07-11 Samsung Electronics Co., Ltd. Semiconductor memory device including storage nodes and resistors and method of manufacturing the same
US20060211192A1 (en) * 2003-05-15 2006-09-21 Samsung Electronics Co., Ltd. Semiconductor memory device including storage nodes and resistors and method of manfacturing the same
US20040229428A1 (en) 2003-05-15 2004-11-18 Cho Chang-Hyun Semiconductor memory device including storage nodes and resistors and method of manufacturing the same
US7183603B2 (en) * 2004-03-31 2007-02-27 Samsung Electronics Co., Ltd. Semiconductor device including square type storage node and method of manufacturing the same
JP2005293759A (en) 2004-04-02 2005-10-20 Hitachi Ltd Semiconductor memory apparatus
US20050232044A1 (en) 2004-04-02 2005-10-20 Hitachi, Ltd. Semiconductor memory device
US7547936B2 (en) * 2004-10-08 2009-06-16 Samsung Electronics Co., Ltd. Semiconductor memory devices including offset active regions

Also Published As

Publication number Publication date
US8378499B2 (en) 2013-02-19
JP5694625B2 (en) 2015-04-01
CN101055871A (en) 2007-10-17
US20070241380A1 (en) 2007-10-18
JP2007287794A (en) 2007-11-01
US8093724B2 (en) 2012-01-10
TW200802810A (en) 2008-01-01
CN101055871B (en) 2011-06-15
TWI355736B (en) 2012-01-01
US20120132972A1 (en) 2012-05-31

Similar Documents

Publication Publication Date Title
USRE47240E1 (en) Semiconductor storage device
US7582925B2 (en) Integrated circuit devices including insulating support layers
US7183603B2 (en) Semiconductor device including square type storage node and method of manufacturing the same
US8507980B2 (en) Semiconductor devices having bit line interconnections with increased width and reduced distance from corresponding bit line contacts and methods of fabricating such devices
US6979614B2 (en) Semiconductor memory device and method of manufacturing the same
US7476585B2 (en) Semiconductor device including storage node and method of manufacturing the same
US20060211192A1 (en) Semiconductor memory device including storage nodes and resistors and method of manfacturing the same
US7078292B2 (en) Storage node contact forming method and structure for use in semiconductor memory
US20060202250A1 (en) Storage capacitor, array of storage capacitors and memory cell array
KR100756290B1 (en) Storage capacitor and method of manufacturing a storage capacitor
US8263456B2 (en) Methods of manufacturing capacitor and semiconductor device including the same
US9362421B2 (en) Semiconductor device including a support structure
US20110012184A1 (en) Semiconductor memory device
US7145195B2 (en) Semiconductor memory device and method of manufacturing the same
US20220406791A1 (en) Semiconductor memory device
TWI506766B (en) Semiconductor device and manufacturing method therefor
US20160027743A1 (en) Semiconductor device
JP2015035619A (en) Semiconductor device
WO2022198953A1 (en) Semiconductor storage apparatus and manufacturing method therefor
KR20040011993A (en) Manufacturing method of semiconductor memory device

Legal Events

Date Code Title Description
AS Assignment

Owner name: LONGITUDE SEMICONDUCTOR S.A.R.L., LUXEMBOURG

Free format text: CHANGE OF NAME;ASSIGNOR:PS5 LUXCO S.A.R.L.;REEL/FRAME:039793/0880

Effective date: 20131112

Owner name: PS5 LUXCO S.A.R.L., LUXEMBOURG

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PS4 LUXCO S.A.R.L.;REEL/FRAME:039818/0506

Effective date: 20130829

AS Assignment

Owner name: LONGITUDE LICENSING LIMITED, IRELAND

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LONGITUDE SEMICONDUCTOR S.A.R.L.;REEL/FRAME:046864/0001

Effective date: 20180731

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12