USRE43539E1 - Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit - Google Patents
Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit Download PDFInfo
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- USRE43539E1 USRE43539E1 US11/798,773 US79877307A USRE43539E US RE43539 E1 USRE43539 E1 US RE43539E1 US 79877307 A US79877307 A US 79877307A US RE43539 E USRE43539 E US RE43539E
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- 239000004065 semiconductor Substances 0.000 title claims description 28
- 239000003990 capacitor Substances 0.000 claims description 9
- 230000001934 delay Effects 0.000 claims description 5
- 230000000694 effects Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 12
- 230000015654 memory Effects 0.000 description 12
- 238000012544 monitoring process Methods 0.000 description 8
- 238000004088 simulation Methods 0.000 description 6
- 239000013256 coordination polymer Substances 0.000 description 5
- 230000001360 synchronised effect Effects 0.000 description 5
- 102100040862 Dual specificity protein kinase CLK1 Human genes 0.000 description 4
- 101000749294 Homo sapiens Dual specificity protein kinase CLK1 Proteins 0.000 description 4
- 101150110971 CIN7 gene Proteins 0.000 description 3
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 3
- 101150110298 INV1 gene Proteins 0.000 description 3
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 3
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- HCUOEKSZWPGJIM-YBRHCDHNSA-N (e,2e)-2-hydroxyimino-6-methoxy-4-methyl-5-nitrohex-3-enamide Chemical compound COCC([N+]([O-])=O)\C(C)=C\C(=N/O)\C(N)=O HCUOEKSZWPGJIM-YBRHCDHNSA-N 0.000 description 1
- MZAGXDHQGXUDDX-JSRXJHBZSA-N (e,2z)-4-ethyl-2-hydroxyimino-5-nitrohex-3-enamide Chemical compound [O-][N+](=O)C(C)C(/CC)=C/C(=N/O)/C(N)=O MZAGXDHQGXUDDX-JSRXJHBZSA-N 0.000 description 1
- 101001109689 Homo sapiens Nuclear receptor subfamily 4 group A member 3 Proteins 0.000 description 1
- 101000598778 Homo sapiens Protein OSCP1 Proteins 0.000 description 1
- 101001067395 Mus musculus Phospholipid scramblase 1 Proteins 0.000 description 1
- 102100022673 Nuclear receptor subfamily 4 group A member 3 Human genes 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
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- the present invention relates to an output buffer circuit for use in an integrated semiconductor circuit device, and more particularly to an output buffer circuit which is capable of adjusting the output impedance thereof according to control signals from an external source.
- DRAMs Dynamic Random Access Memories
- SDRAMs Synchronous DRAMs
- Japanese patent applications laid-open Nos. 05-175444 and 2-092019 propose arrangements for adjusting the driving capability of an output buffer circuit by changing the output impedance thereof.
- Proposals disclosed in Japanese patent applications laid-open Nos. 2001-68986 and 2000-332593 adjust the slew rate of an output buffer circuit by changing the ratio of tr(rise time)/tf(fall time) of an output pulse waveform.
- Integrated semiconductor circuit devices such as DDR (Double Data Rate)-SDRAMs receive data from a memory device which outputs data in timed relation to rising and falling edges of a system clock signal CLK (see FIG. 1 of the accompanying drawings).
- a cross-point CP between rising and falling waveforms shown in FIG. 1 is shifted a one-half period (tck/2) from the system clock signal CLK, then the integrated semiconductor circuit device fails to receive the transmitted data correctly.
- tck/2 one-half period
- the system fails to determine a logic level of “1” or “0” properly. Conversely, if the slew rate become higher, then high-frequency components increase to distort output pulses, thus increasing noise which tends to result in a system malfunction.
- the above problems may be solved by compensating for variations in the cross-point CP and the slew rate at the data transmission side.
- variations in the cross-point CP and the slew rate cannot be compensated for simply by adjusting the output impedance. Only adjusting the slew rate fails to achieve a compensation within the allowable range of variations of the system which operates at a high speed and under a low voltage because the cross-point CP and the slew rate depend on variations of both the output impedance and the power supply voltage.
- the output impedance of an output buffer circuit can easily be detected for fluctuations by monitoring the load current and output level of the output buffer circuit even when the output buffer circuit is incorporated in a system.
- the output buffer circuits disclosed in the above applications offer an arrangement for adjusting either one of the output impedance and the slew rate, and are disadvantageous in that variations in the cross-point CP and the slew rate of the disclosed output buffer circuits as they are incorporated in a system cannot sufficiently be compensated for against variations in the power supply voltage and the ambient temperature.
- phase synchronizing circuit such as a DLL (Delay Locked Loop) or a PLL (Phase Locked Loop) in order to synchronize data output from the output buffer circuit of the integrated semiconductor circuit device with the system clock signal.
- the phase synchronizing circuit uses a circuit having a delay similar to the delay in the output buffer circuit for monitoring the delay in the output buffer circuit.
- the phase synchronizing circuit generates a compensating clock signal for compensating for the monitored delay, and synchronizes the output from the output buffer circuit with the generated compensating clock signal.
- the data output timing of the output buffer circuit varies because of the adjustment of the output impedance and the slew rate thereof.
- an output buffer circuit has a main driver for driving a load and a predriver for driving the main driver.
- the main driver has at least a pair of a first p-channel MOS transistor and a first n-channel MOS transistor for driving a load according to the data, and at least a pair of a second p-channel MOS transistor and a second n-channel MOS transistor for driving the load in coaction with the first p-channel MOS transistor and the first n-channel MOS transistor.
- the predriver has at least a pair of a third p-channel MOS transistor and a third n-channel MOS transistor for driving the first p-channel MOS transistor according to the data, at least a pair of a fourth p-channel MOS transistor and a fourth n-channel MOS transistor for driving the first n-channel MOS transistor according to the data, at least one fifth n-channel MOS transistor for driving the first p-channel MOS transistor in coaction with the third n-channel MOS transistor, and at least one fifth p-channel MOS transistor for driving the first n-channel MOS transistor in coaction with the fourth p-channel MOS transistor.
- the number of transistors of the main driver for driving the load according to control signals and the number of transistors of the predriver are changed to simultaneously adjust the cross-point of output pulses and the slew rate as well as the output impedance with the same control signals. Consequently, the data receiving side connected to the output buffer circuit is prevented from malfunctioning, making it possible to achieve a system which operates normally even when the power supply voltage and the ambient temperature vary.
- the output impedance and the rise and fall times of output pulses are simultaneously controlled, the number of control signals and the steps of a testing process are made smaller than if the output impedance and the rise and fall times of output pulses were controlled independently of each other. Thus, the manufacturing cost of the output buffer circuit is prevented from increasing.
- the system incorporating the output buffer circuit has its performance capability increased because the slew rate is automatically improved by monitoring and adjusting only the output impedance of the output buffer circuit.
- Another output buffer circuit has a main driver which is identical to the main driver described above, and a predriver including at least a pair of a third p-channel MOS transistor and a third n-channel MOS transistor for driving the first p-channel MOS transistor according to the data, at least a pair of a fourth p-channel MOS transistor and a fourth n-channel MOS transistor for driving the first n-channel MOS transistor according to the data, at least one fifth n-channel MOS transistor for driving the first p-channel MOS transistor in coaction with the third n-channel MOS transistor, at least one fifth p-channel MOS transistor for driving the first p-channel MOS transistor in coaction with the third p-channel MOS transistor, at least one sixth p-channel MOS transistor for driving the first n-channel MOS transistor in coaction with the fourth p-channel MOS transistor, and at least one sixth n-channel MOS transistor for driving the first n-channel MOS transistor in coaction with the fourth p-channel MO
- An integrated semiconductor circuit device has the above output buffer circuit and a delay monitor circuit identical in circuit arrangement to the output buffer circuit and having transistors controlled according to the control signals in the same manner as with the output buffer circuit, the delay monitor circuit having an output terminal connected to a dummy load determined from an actual load of the output buffer circuit based on a transistor size ratio between the output buffer circuit and the delay monitor circuit.
- Another integrated semiconductor circuit device has the above output buffer circuit and a delay monitor circuit comprising a plurality of capacitors for delaying the data output from the output buffer circuit by respective delays, and a plurality of switches for selectively enabling and disabling the capacitors to delay the data according to the control signals, the delay monitor circuit having an output terminal connected to a dummy load determined from an actual load of the output buffer circuit based on a transistor size ratio between the output buffer circuit and the delay monitor circuit.
- the delay monitor circuit reflects the adjusted values of the output impedance of the output buffer circuit and the ratio tr/tf of output pulses, a system clock signal and the data output from the output buffer circuit can be synchronized more accurately with each other.
- FIG. 1 is a diagram illustrative of problems which arise when a conventional output buffer circuit is in operation
- FIG. 2 is a block diagram of a DRAM as an integrated semiconductor circuit device incorporating an output buffer circuit according to the present invention
- FIG. 3 is a circuit diagram of an output buffer circuit according to a first embodiment of the present invention.
- FIG. 4 is a circuit diagram of a modification of the output buffer circuit according to the first embodiment
- FIG. 5 is a waveform diagram showing the results of a simulation of output pulses produced when the ratio tr/tf of the output buffer circuit according to the first embodiment is controlled and when the ratio tr/tf is not controlled;
- FIG. 6 is a waveform diagram showing the results of a simulation of output pulses produced when the ratio tr/tf of the output buffer circuit according to the first embodiment is controlled and when the ratio tr/tf is not controlled;
- FIG. 7 is a circuit diagram of an output buffer circuit according to a second embodiment of the present invention.
- FIG. 8 is a circuit diagram of a portion of the output buffer circuit according to the present invention and waveform diagrams showing the manner in which that portion of the output buffer circuit operates;
- FIG. 9 is a block diagram of a phase synchronizing circuit which operates as shown in FIG. 1 ;
- FIGS. 10A and 10B are circuit diagrams showing examples in which a delay monitor circuit is used.
- FIG. 11 is a circuit diagram of a delay monitor circuit incorporated in the integrated semiconductor circuit device according to the present invention.
- a DRAM (including an SDRAM) as an example of an integrated semiconductor circuit device which incorporates an output buffer circuit according to the present invention will be described below.
- the DRAM comprises memory array 1 made up of a plurality of memory cells for storing data, X decoder (X-DEC) 2 and Y decoder (Y-DEC) 3 for decoding addresses Ai to access memory cells for writing data therein and reading data therefrom, ROW address buffer 4 and COLUMN address buffer 5 for temporarily holding addresses entered from an external source, control circuit 6 for controlling operation of the DRAM according to various control signals supplied from an external source, mode control circuit 7 for operating the DRAM in certain modes according to various control signals supplied from an external source, output buffer circuit 8 for outputting data read from memory array 1 from DQ terminal at a predetermined timing, and phase synchronizing circuit 9 for synchronizing the data output timing of output buffer circuit 8 with a system clock signal CLK.
- X-DEC X decoder
- Y-DEC Y decoder
- Data stored in memory array 1 are read by a sense amplifier (not shown) and transferred to output buffer circuit 8 .
- Data to be stored in the DRAM are input through DQ terminal, and written into memory cells corresponding to write addresses by a driver circuit (not shown).
- Control circuit 6 is supplied with various control signals including /RAS (Row Address Strobe command), /CAS (Column Address Strobe command), /WE (Write Enable), /CS (Chip Select), CKE (Clock Enable), CLK (Clock), /CLK, DM (input/output mask).
- /RAS Row Address Strobe command
- /CAS Cold Address Strobe command
- /WE Write Enable
- /CS Chip Select
- CKE Chip Enable
- CLK Chip
- CLK clock
- DM input/output mask
- Data read from memory array 1 by the non-illustrated sense amplifier is temporarily stored in a buffer memory (not shown), and output from output buffer circuit 8 through DQ terminal according to control signals that are generated by control circuit 6 and mode control circuit 7 .
- Data input from an external source through DQ terminal is temporarily stored in the non-illustrated buffer memory, and written through a write amplifier (not shown) into memory array 1 according to control signals that are generated by control circuit 6 and mode control circuit 7 .
- output buffer circuit 8 has its output impedance kept at a high level by a control signal from control circuit 6 .
- Phase synchronizing circuit 9 comprises a DLL, a PLL, or the like. Phase synchronizing circuit 9 uses a circuit (a delay monitor circuit to be described later on) having a delay similar to the delay in output buffer circuit 8 for monitoring the delay in output buffer circuit 8 . Phase synchronizing circuit 9 generates compensating clock signal CLKOE for compensating for the monitored delay from system clock CLK, and supplies generated compensating clock signal CLKOE to output buffer circuit 8 .
- a circuit a delay monitor circuit to be described later on
- Output buffer circuit 8 outputs data in synchronism with compensating clock signal CLKOE supplied from phase synchronizing circuit 9 .
- the circuit for monitoring the delay in output buffer circuit 8 has its output impedance and slew rate controlled, as with output buffer circuit 8 , by control signals ⁇ 1 through ⁇ N, / ⁇ 1 through / ⁇ N to be described later on.
- the output buffer circuit has main driver 11 for driving a load connected to DQ terminal, main driver 11 having an output impedance which can be changed, a predriver 12 for driving main driver 11 according to data (DATA) read from a sense amplifier and changing the ratio tr/tf of output pulses of main driver 11 , and a controller 13 for generating signals to change the output impedance of main driver 11 and the ratio tr/tf of output pulses according to control signals ⁇ 1 through ⁇ 6 from a control circuit, etc.
- Control signals / ⁇ 1 through / ⁇ 6 shown in FIG. 3 are inversions of signals ⁇ 1 through ⁇ 6. Inverters for inverting signals ⁇ 1 through ⁇ 6 are omitted from the illustration in FIG. 3 .
- control signals ⁇ 1 through ⁇ 6 are generated from a control circuit 6 according to commands supplied from an external integrated semiconductor circuit that contains an output buffer circuit shown in FIG. 3 .
- the data receiving the output buffer circuit shown in FIG. 3 is a signal which is synchronous with compensating clock signal CLKOE supplied from phase synchronizing circuit 9 shown in FIG. 2 .
- Main driver 11 comprises four p-channel MOS transistors (hereinafter referred to as “pMOS transistors”) QP 1 through QP 4 and four n-channel MOS transistors (hereinafter referred to as “nMOS transistors”) QN 1 through QN 4 .
- pMOS transistors p-channel MOS transistors
- nMOS transistors n-channel MOS transistors
- PMOSpMOS transistors QP 1 through QP 4 have respective sources connected to a power supply, and nMOS transistors QN 1 through QN 4 have respective sources connected to a ground potential.
- pMOS transistors QP 1 through QP 4 and nMOS transistors QN 1 through QN 4 have respective drains connected to DQ terminal.
- pMOS transistor QP 1 and nMOS transistor QN 1 have respective gates connected to predriver 12
- pMOS transistors QP 2 through QP 4 and nMOS transistors QN 2 through QN 4 have respective gates connected to controller 13 .
- PMOSpMOS transistors QP 2 through QP 4 as well as pMOS transistor QP 1 drive the load connected to DQ terminal to adjust the output impedance when high-level data is output from main driver 11 .
- nMOS transistors QN 2 through QN 4 as well as nMOS transistor NP 1 drive the load connected to DQ terminal to adjust the output impedance when low-level data is output from main driver 11 .
- pMOS transistors QP 2 through QP 4 and nMOS transistors QN 2 through QN 4 comprise transistors having a small device size (a narrow gate width) whose effect on the ratio tr/tf of output pulses is smaller than pMOS transistor QP 1 and nMOS transistor QN 1 .
- the number of pMOS transistors connected parallel to pMOS transistor QP 1 and the number of nMOS transistors connected parallel to nMOS transistor QN 1 are not limited to three, but at least one pMOS transistor may be connected parallel to pMOS transistor QP 1 and at least one nMOS transistor may be connected parallel to nMOS transistor QN 1 .
- Predriver 12 comprise pMOS transistor QP 11 and nMOS transistor QN 11 for driving pMOS transistor QP 1 of main driver 11 , nMOS transistors QN 12 through QN 14 for adjusting the driving capability of nMOS transistor QN 11 for driving pMOS transistor QP 1 , nMOS transistors QN 15 through QN 17 for turning on and off nMOS transistors QN 12 through QN 14 , pMOS transistor QP 21 and nMOS transistor QN 21 for driving nMOS transistor QN 1 of main driver 11 , pMOS transistors QP 22 through QP 24 for adjusting the driving capability of pMOS transistor QP 21 for driving nMOS transistor QN 1 , and pMOS transistors QP 25 through QP 27 for turning on and off pMOS transistors QP 22 through QP 24 .
- nMOS transistors QN 15 through QN 17 are controlled by respective control signals ⁇ 1 through ⁇ 3, and pMOS transistors PN 25 through QP 27 are controlled by respective control signals ⁇ 4 through ⁇ 6.
- predriver 12 has inverter INV 1 for driving pMOS transistor QP 11 and nMOS transistor QN 11 according to the data (DATA) supplied from an external source, and inverter INV 2 for driving pMOS transistor QP 21 and nMOS transistor QN 21 according to the data (DATA) supplied from the external source.
- inverters INV 1 , INV 2 may be dispensed with if no logic problem arises, or may be replaced with driver circuits which do not invert logic levels.
- nMOS transistors QN 12 through QN 14 as well as nMOS transistor QN 11 drive pMOS transistor QP 1 as a load to adjust the time for pMOS transistor QP 1 to be turned on from an OFF state, i.e., the rise time tr of an output pulse of main driver 11 .
- pMOS transistors QP 22 through QP 24 as well as PMOS pMOS transistor QP 21 drive nMOS transistor QN 1 as a load to adjust the time for nMOS transistor QN 1 to be turned on from an OFF state, i.e., the fall time tf of an output pulse of main driver 11 .
- the number of nMOS transistors connected to nMOS transistor QN 11 and the number of pMOS transistors connected to PMOS pMOS transistor QP 21 are not limited to three, but at least one nMOS transistor may be connected to nMOS transistor QN 11 and at least one pMOS transistor may be connected to pMOS transistor QP 21 .
- Controller 13 is a logic circuit which comprises OR gates NOR 1 through NOR 3 , AND gates NAND 1 through NAND 3 , and inverters INV 11 through INV 16 for generating signals for turning on and off pMOS transistors QP 2 through QP 4 and nMOS transistors QN 2 through QN 4 of main driver 11 and nMOS transistors QN 15 through QN 17 and pMOS transistors QP 25 through QP 27 of predriver 12 according to control signals ⁇ 1 through ⁇ 6,
- nMOS transistors QN 15 through QN 17 are controlled by control signals ⁇ 1 through ⁇ 3 thereby to drive nMOS transistors QN 12 through QN 14 as well as nMOS transistor QN 11
- the ON/OFF states of pMOS transistors QP 25 through QP 27 are controlled by control signals ⁇ 4 through ⁇ 6 thereby to drive pMOS transistors QP 22 through QP 24 as well as pMOS transistor QP 21 .
- predriver 12 may be arranged such that nMOS transistors QN 12 through QN 14 and pMOS transistors QP 22 through QP 24 are driven directly by control signals output from the logic circuit of controller 13 .
- main driver 11 may have pMOS transistors XP 2 through XP 4 connected in series to pMOS transistors QP 2 through QP 4 and nMOS transistors XN 2 through XN 4 connected in series to nMOS transistors QN 2 through QN 4 , and may be arranged such that the ON/OFF states of pMOS transistors XP 2 through XP 4 and nMOS transistors XN 2 through XN 4 are controlled by control signals output from the logic circuit of controller 13 .
- the level of control signals ⁇ 1 through ⁇ 3 is rendered low to turn on corresponding pMOS transistors QP 2 through QP 4 to lower the output impedance at the high-level data is output. At this time, the greater the number of pMOS transistors that are turned on, the smaller the output impedance.
- the level of control signals ⁇ 4 through ⁇ 6 is rendered high to turn on corresponding nMOS transistors QN 2 through QN 4 to lower the output impedance at the low-level data is output. At this time, the greater the number of nMOS transistors that are turned on, the smaller the output impedance.
- the level of control signals ⁇ 1 through ⁇ 3 is rendered high to turn on corresponding nMOS transistors QN 12 through QN 14 to shorten the rise time tr upon switching from the low-level data to the high-level data.
- the greater the number of nMOS transistors that are turned on the shorter the rise time tr.
- the level of control signals ⁇ 4 through ⁇ 6 is rendered low to turn on corresponding pMOS transistors QP 22 through QP 24 to shorten the fall time tf upon switching from the high-level data to the low-level data.
- the greater the number of pMOS transistors that are turned on the shorter the fall time tf.
- the output impedance is adjusted and the ratio tr/tf are adjusted simultaneously.
- control signal / ⁇ 1 when control signal / ⁇ 1 is rendered low and control signal ⁇ 4 is rendered high in order to lower the output impedance by one stage, control signal ⁇ 1 which is an inversion of control signal / ⁇ 1 goes high, turning on nMOS transistors QN 12 , QN 15 , and control signal / ⁇ 4 which is an inversion of control signal ⁇ 4 goes low, turning on pMOS transistors QP 22 , QP 25 . Therefore, the ratio tr/tf is reduced by one stage.
- the ratio tr/tf is reduced by two stages
- the ratio tr/tf is reduced by three stages.
- PMOS pMOS transistors QP 2 through QP 4 and nMOS transistors QN 2 through QN 4 comprise transistors having a small device size whose effect on the ratio tr/tf is smaller than pMOS transistor QP 1 and nMOS transistor QN 1 .
- the ratio tr/tf is adjusted using only pMOS transistor QP 1 and nMOS transistor QN 1 .
- pMOS transistors QP 2 through QP 4 and nMOS transistors QN 2 through QN 4 have a large device size, it is possible to adjust the ratio tr/tf with each of the transistors. In that case, however, the circuit scale is relatively large because it is necessary to add the same arrangement as predriver 12 in place of each of inverters INV 11 through INV 16 . Therefore, it is preferable as shown in FIG. 3 to adjust the ratio tr/tf with the pair of PMOS pMOS transistors QP 1 and nMOS transistor QN 1 .
- the number of stages for adjusting the output impedance and the number of stages for adjusting the ratio tr/tf are the same as each other.
- the number of stages for adjusting the output impedance and the number of stages for adjusting the ratio tr/tf are not required to be the same as each other, but may be different from each other.
- the main driver may have eight pairs of pMOS transistors and nMOS transistors for adjusting the output impedance in seven stages, and the ratio tr/tf may be adjusted in three stages as with the circuit shown in FIG. 3 .
- the ratio tr/tf of output pulses tends to be greater (longer). Therefore, if the relationship between changes in the output impedance of the output buffer circuit and changes in the ratio tr/tf is determined in advance, then, since a corrective quantity for the ratio tr/tf of output pulses is known for a corrective quantity for the output impedance, the output impedance and the ratio tr/tf can simultaneously be corrected by one control signal. Consequently, the data receiving side is prevented from malfunctioning, making it possible to achieve a system which operates normally even when the power supply voltage and the ambient temperature vary.
- the output buffer circuit is controlled to increase the output impedance and increase the ratio tr/tf to compensate for fluctuations in the output level of the output buffer circuit and the cross-point of the output signal.
- a range of variations of the cross-point of the ratio tr/tf is reduced to about 2 ⁇ 3 of the range of variations of the cross-point when the ratio tr/tf is not controlled.
- FIG. 5 shows the ratio tr/tf in best conditions when the ratio tr/tf is controlled and when the ratio tr/tf is not controlled against the ratio tr/tf in worst conditions.
- the output impedance is controlled both when the ratio tr/tf is controlled and when the ratio tr/tf is not controlled.
- FIG. 6 shows the results of a simulation which indicate that when the ratio tr/tf is controlled, the range of variations of the slew rate is reduced to about 1 ⁇ 3 of the range of variations of the slew rate when the ratio tr/tf is not controlled.
- FIG. 6 illustrates waveforms (a: Device worst) when the ratio tr/tf is not controlled, the power supply voltage is minimum, and the device is at a high temperature at which the slew rate is lowest, waveforms (b: Device best) when the ratio tr/tf is not controlled, the power supply voltage is maximum, and the device is at a low temperature at which the slew rate is highest, and waveforms (c: Device best) when the ratio tr/tf is controlled, the power supply voltage is maximum, and the device is at a low temperature at which the slew rate is highest.
- the output impedance is controlled both when the ratio tr/tf is controlled and when the ratio tr/tf is not controlled.
- the output impedance is adjusted and the ratio tr/tf of output pulses is controlled at the same time for thereby reducing the number of control signals and the number of testing steps. Accordingly, the manufacturing cost of the output buffer circuit is prevented from increasing, and it is not necessary to conduct a complex test unlike the situation where the output impedance and the ratio tr/tf of output pulses are controlled independently of each other. If only the output impedance of the output buffer circuit is monitored and adjusted, then since the slew rate is automatically improved, the performance of a system which employs the integrated semiconductor circuit device incorporating the output buffer circuit according to the present embodiment can be improved.
- the output buffer circuit according to the second embodiment includes, in addition to the components of the predriver of the output buffer circuit according to the first embodiment shown in FIG. 3 , pMOS transistors QP 31 through QP 33 for increasing the driving capability of the pMOS transistor QP 11 for driving the pMOS transistor QP 1 , pMOS transistors QP 34 through QP 36 for turning on and off pMOS transistors QP 31 through QP 33 , nMOS transistors QN 31 through QN 33 for increasing the driving capability of the nMOS transistor QN 21 for driving the nMOS transistor QN 1 , and nMOS transistors QN 34 through QN 36 for turning on and off nMOS transistors QN 31 through QN 33 .
- pMOS transistors QP 34 through QP 36 are controlled by respective control signals / ⁇ 1 through / ⁇ 3, and nMOS transistors QN 34 through QN 36 are controlled by respective control signals / ⁇ 4 ⁇ 4 through ⁇ 6. Therefore, the ON/OFF states of pMOS transistors QP 31 through QP 33 are controlled at the same timing as nMOS transistors QN 12 through QN 14 shown in FIG. 3 , and the ON/OFF states of nMOS transistors QN 31 through QN 33 are controlled at the same timing as pMOS transistors QP 22 through QP 24 shown in FIG. 3 .
- Other structural and operational details of the output buffer circuit according to the second embodiment are identical to those of the output buffer circuit according to the first embodiment, and will not be described below.
- nMOS transistor QP 11 and nMOS transistor QN 11 which are provided to drive pMOS transistor QP 1 of the main driver
- nMOS transistor QN 11 has its driving capability increased
- pMOS transistor QP 21 and nMOS transistor QN 21 which are provided to drive nMOS transistor QN 1 of the main driver
- only pMOS transistor QP 11 has its driving capability increased.
- pMOS transistors QP 31 through QP 36 are added to the arrangement shown in FIG. 3 to increase the driving capabilities of both pMOS transistor QP 11 and nMOS transistor QN 11 as shown in FIG. 8(b) .
- the arrangement according to the second embodiment offers the advantages of the output buffer circuit according to the first embodiment, and is additionally effective to prevent noise from being produced and the current consumption from being increased by the through current.
- nMOS transistors QN 31 through QN 36 are added to the arrangement shown in FIG. 3 to increase the driving capabilities of both pMOS transistor QP 21 and nMOS transistor QN 21 prevent noise from being produced and the current consumption from being increased by the through current.
- the number of stages for adjusting the output impedance and the number of stages for adjusting the ratio tr/tf are not required to be the same as each other, but may be different from each other as with the arrangement shown in FIG. 4 according to the first embodiment.
- the arrangements of the output buffer circuits according to the first and second embodiments are applied to another circuit.
- an integrated semiconductor circuit device such as a DDR-SDRAM or the like which operates at a high speed incorporates phase synchronizing circuit 9 for synchronizing data output from output buffer circuit 8 with system clock signal CLK, as shown in FIG. 9 .
- Phase synchronizing circuit 9 comprises a DLL as shown in FIG. 9 , for example.
- Phase synchronizing circuit 9 has input buffer circuit 21 for being supplied with system clock signal CLK, variable delay circuit 22 for delaying clock signal CLK 1 output from input buffer circuit 21 to generate compensating clock signal CLKOE for compensating for output data timing of output buffer circuit 8 , delay monitor circuit 23 for being supplied with compensating clock signal CLKOE and monitoring a delay of output buffer circuit 8 , input buffer replica circuit 24 for being supplied with an output signal from delay monitor circuit 23 and outputting feedback clock signal CLKFB as a monitored full delay, input buffer replica circuit 24 having a delay equal to the delay of input buffer circuit 21 , phase comparator (PD) 25 for outputting a value proportional to the phase difference between clock signal CLK 1 output from input buffer circuit 21 and feedback clock signal CLKFB, and counter (Counter) 26 for controlling the delay produced by variable delay circuit 22 according to the output value from phase comparator 25 .
- phase comparator (PD) 25 for outputting a value proportional to the phase
- phase synchronizing circuit 9 operates to bring clock signal CLK 1 output from input buffer circuit 21 into phase with feedback clock signal CLKFB (precisely, feedback clock signal CLKFB is in phase with clock signal CLK 1 with a one period delay)
- compensating clock signal CLKOE output from variable delay circuit 22 has phase information for canceling out delays caused by delay monitor circuit 23 and input buffer replica circuit 24 .
- Delay monitor circuit 23 having the same delay as output buffer circuit 8 may comprise an extra output buffer circuit incorporated in the integrated semiconductor circuit device for monitoring the delay.
- a circuit replica circuit which is identical in construction to the output buffer circuit and which has transistors reduced in size.
- the output terminal of the replica circuit may be connected to a dummy load determined from an actual load (represented by a simulated value) based on the ratio of transistor sizes of the output buffer circuit and the replica circuit for monitoring changes in the delay of the output buffer circuit due to variations in the ambient temperature and the power supply voltage.
- the dummy load is included in the replica circuit (delay monitor circuit 9 ).
- the dummy load may have a load resistance (R T of 250 ⁇ ) which is ten times the load resistance of the actual load, a load capacitance (C L of 3 pF) which is 1/10 of the load capacitance of the actual load, and an interconnection resistance (R S of 250 ⁇ ) which is ten times the actual interconnection resistance.
- the dummy load does not need to have a circuit (e.g., a load replica) whose resistance and capacitance vary depending on variations in the ambient temperature and the power supply voltage, and may be arranged to be unsusceptible to such variations.
- pMOS transistor WP 1 shown in FIGS. 10A and 10B represents all pMOS transistors QP 1 through QP 4 of the main driver shown in FIG. 3 .
- nMOS transistor WN 1 shown in FIGS. 10A and 10B represents all nMOS transistors QN 1 through QN 4 of the main driver shown in FIG. 3 .
- inverters WP 2 , WN 2 shown in FIGS. 10A and 10B represent all pMOS transistors QP 11 , QP 31 through QP 36 , nMOS transistors QN 11 through QN 17 of the predrivers shown in FIGS. 3 and 7
- inverters WP 3 , WN 3 shown in FIGS. 10A and 10B represent all pMOS transistors QP 21 through QP 27 , nMOS transistors QN 21 , QN 31 through QN 36 of the predrivers shown in FIGS. 3 and 7 .
- FIGS. 10A and 10B the controllers shown in FIGS. 3 and 7 , and control signals ⁇ 1 through ⁇ 6, ⁇ 1 through / ⁇ 6 ⁇ 1 through ⁇ 6, / ⁇ 1 through/ ⁇ 6 which are supplied from the controller to pMOS transistors QP 2 through QP 4 and nMOS transistors QN 2 through QN 4 of the main driver, and pMOS transistors QP 25 through QP 27 , pMOS transistors QP 34 through QP 36 , nMOS transistors QN 15 through QN 17 , and nMOS transistors QN 34 through QN 36 of the predriver are omitted from the illustration.
- the circuit arrangement shown in FIGS. 10A and 10B has those controller and control signals as with the circuit arrangements shown in FIGS. 3 and 7 .
- delay monitor circuit 23 shown in FIG. 9 is of the same arrangement as the output buffer circuit according to the first embodiment or the second embodiment, and is made up of transistors whose device size is smaller than those of the output buffer circuit.
- the transistors are operated by control signals ⁇ 1 through ⁇ N, / ⁇ 1 through / ⁇ N (N is a positive integer) to control the output impedance of delay monitor circuit 23 and the ratio tr/tf of output pulses.
- the numbers of stages for adjusting the output impedance of the delay monitor circuit and the output buffer circuit and the numbers of stages for adjusting the ratio tr/tf thereof are not required to be the same as each other.
- the numbers of adjusting stages for the delay monitor circuit may be smaller than the numbers of adjusting stages for the output buffer circuit.
- delay monitor circuit 23 reflects the adjusted values of the output impedance of output buffer circuit 8 and the ratio tr/tf of output pulses, system clock signal CLK and the data output from the output buffer circuit can be synchronized more accurately with each other using phase synchronizing circuit 9 .
- the delay caused by each of the capacitors may be equalized to a delay after the output impedance of the output buffer circuit and the ratio tr/tf of output pulses have been adjusted for achieving the above advantages.
- Each of PMOS pMOS transistor WP 1 and nMOS transistor WN 1 shown in FIG. 11 may comprise a single MOS transistor, unlike the arrangement shown in FIG. 3 , and each of inverters (WP 2 , WN 2 ), (WP 3 , WN 3 ) may comprise a set of pMOS and nMOS transistors unlike the arrangement shown in FIG. 3 .
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Abstract
Description
Claims (16)
Priority Applications (1)
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US11/798,773 USRE43539E1 (en) | 2001-12-19 | 2007-05-16 | Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit |
Applications Claiming Priority (4)
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JP2001-386126 | 2001-12-19 | ||
JP2001386126A JP3667690B2 (en) | 2001-12-19 | 2001-12-19 | Output buffer circuit and semiconductor integrated circuit device |
US10/320,059 US6894547B2 (en) | 2001-12-19 | 2002-12-16 | Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit |
US11/798,773 USRE43539E1 (en) | 2001-12-19 | 2007-05-16 | Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit |
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US10/320,059 Reissue US6894547B2 (en) | 2001-12-19 | 2002-12-16 | Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit |
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USRE43539E1 true USRE43539E1 (en) | 2012-07-24 |
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US10/320,059 Ceased US6894547B2 (en) | 2001-12-19 | 2002-12-16 | Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit |
US11/798,773 Expired - Lifetime USRE43539E1 (en) | 2001-12-19 | 2007-05-16 | Output buffer circuit and integrated semiconductor circuit device with such output buffer circuit |
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Citations (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6238616A (en) | 1985-08-14 | 1987-02-19 | Hitachi Ltd | Output circuit |
US4719369A (en) | 1985-08-14 | 1988-01-12 | Hitachi, Ltd. | Output circuit having transistor monitor for matching output impedance to load impedance |
JPH01154622A (en) | 1987-11-05 | 1989-06-16 | Texas Instr Inc <Ti> | Circuit for changing output driving characteristics |
JPH0292019A (en) | 1988-09-28 | 1990-03-30 | Nec Corp | Complementary mos output buffer circuit |
US5140194A (en) | 1988-09-24 | 1992-08-18 | Mitsubishi Denki Kabushiki Kaisha | Driver circuit apparatus with means for reducing output ringing |
JPH0547186A (en) | 1991-08-08 | 1993-02-26 | Ricoh Co Ltd | Output circuit in semiconductor memory |
JPH05160707A (en) | 1991-12-06 | 1993-06-25 | Nec Corp | Output circuit |
JPH05175444A (en) | 1991-12-26 | 1993-07-13 | Sony Corp | Mos output circuit |
JPH076587A (en) | 1992-12-16 | 1995-01-10 | Hyundai Electron Ind Co Ltd | Data output buffer circuit |
US5500610A (en) | 1993-10-08 | 1996-03-19 | Standard Microsystems Corp. | Very high current integrated circuit output buffer with short circuit protection and reduced power bus spikes |
JPH0993111A (en) | 1995-09-28 | 1997-04-04 | Toshiba Microelectron Corp | Slew rate type buffer circuit |
US5773999A (en) | 1995-09-28 | 1998-06-30 | Lg Semicon Co., Ltd. | Output buffer for memory circuit |
JPH10242835A (en) | 1997-02-27 | 1998-09-11 | Hitachi Ltd | Output circuit, semiconductor integrated circuit and electronic circuit device |
US5850159A (en) | 1997-05-12 | 1998-12-15 | Ind Tech Res Inst | High and low speed output buffer with controlled slew rate |
JPH1117516A (en) | 1997-06-10 | 1999-01-22 | Ind Technol Res Inst | High and low speed output buffer having controlled slew rate |
US5914618A (en) | 1997-03-11 | 1999-06-22 | Vlsi Technology, Inc. | Optimum noise isolated I/O with minimized footprint |
US5917758A (en) | 1996-11-04 | 1999-06-29 | Micron Technology, Inc. | Adjustable output driver circuit |
US6066958A (en) | 1998-06-03 | 2000-05-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit |
JP2000332593A (en) | 1999-05-21 | 2000-11-30 | Mitsubishi Electric Corp | Output buffer circuit |
JP2001007695A (en) | 1999-06-18 | 2001-01-12 | Mitsubishi Electric Corp | Output buffer circuit |
JP2001068986A (en) | 1999-08-30 | 2001-03-16 | Nec Ic Microcomput Syst Ltd | Output buffer circuit for semiconductor device |
US6288563B1 (en) | 1998-12-31 | 2001-09-11 | Intel Corporation | Slew rate control |
US6320433B1 (en) | 1999-09-21 | 2001-11-20 | Texas Instruments Incorporated | Output driver |
US6466487B2 (en) | 2000-09-18 | 2002-10-15 | Kabushiki Kaisha Toshiba | Semiconductor device with impedance controllable output buffer |
US6483340B2 (en) | 2000-06-20 | 2002-11-19 | Nec Corporation | High integration-capable output buffer circuit unaffected by manufacturing process fluctuations or changes in use |
US6559676B1 (en) | 2001-11-30 | 2003-05-06 | Oki Electric Industry Co., Ltd. | Output buffer circuit |
US6573753B1 (en) | 2001-07-20 | 2003-06-03 | Cypress Semiconductor Corporation | Microcontroller input/output nodes with both programmable pull-up and pull-down resistive loads and programmable drive strength |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002107798A (en) * | 2000-07-25 | 2002-04-10 | Olympus Optical Co Ltd | Flash light emitting device and device for moving camera |
-
2001
- 2001-12-19 JP JP2001386126A patent/JP3667690B2/en not_active Expired - Lifetime
-
2002
- 2002-12-16 US US10/320,059 patent/US6894547B2/en not_active Ceased
-
2007
- 2007-05-16 US US11/798,773 patent/USRE43539E1/en not_active Expired - Lifetime
Patent Citations (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6238616A (en) | 1985-08-14 | 1987-02-19 | Hitachi Ltd | Output circuit |
US4719369A (en) | 1985-08-14 | 1988-01-12 | Hitachi, Ltd. | Output circuit having transistor monitor for matching output impedance to load impedance |
JPH01154622A (en) | 1987-11-05 | 1989-06-16 | Texas Instr Inc <Ti> | Circuit for changing output driving characteristics |
US4855623A (en) | 1987-11-05 | 1989-08-08 | Texas Instruments Incorporated | Output buffer having programmable drive current |
US5140194A (en) | 1988-09-24 | 1992-08-18 | Mitsubishi Denki Kabushiki Kaisha | Driver circuit apparatus with means for reducing output ringing |
JPH0292019A (en) | 1988-09-28 | 1990-03-30 | Nec Corp | Complementary mos output buffer circuit |
JPH0547186A (en) | 1991-08-08 | 1993-02-26 | Ricoh Co Ltd | Output circuit in semiconductor memory |
JPH05160707A (en) | 1991-12-06 | 1993-06-25 | Nec Corp | Output circuit |
JPH05175444A (en) | 1991-12-26 | 1993-07-13 | Sony Corp | Mos output circuit |
JPH076587A (en) | 1992-12-16 | 1995-01-10 | Hyundai Electron Ind Co Ltd | Data output buffer circuit |
US5929668A (en) | 1992-12-16 | 1999-07-27 | Hyundai Electronice Industries Co., Ltd. | Data output buffer circuit |
US5500610A (en) | 1993-10-08 | 1996-03-19 | Standard Microsystems Corp. | Very high current integrated circuit output buffer with short circuit protection and reduced power bus spikes |
JPH0993111A (en) | 1995-09-28 | 1997-04-04 | Toshiba Microelectron Corp | Slew rate type buffer circuit |
US5773999A (en) | 1995-09-28 | 1998-06-30 | Lg Semicon Co., Ltd. | Output buffer for memory circuit |
US5917758A (en) | 1996-11-04 | 1999-06-29 | Micron Technology, Inc. | Adjustable output driver circuit |
JPH10242835A (en) | 1997-02-27 | 1998-09-11 | Hitachi Ltd | Output circuit, semiconductor integrated circuit and electronic circuit device |
US5914618A (en) | 1997-03-11 | 1999-06-22 | Vlsi Technology, Inc. | Optimum noise isolated I/O with minimized footprint |
US5850159A (en) | 1997-05-12 | 1998-12-15 | Ind Tech Res Inst | High and low speed output buffer with controlled slew rate |
JPH1117516A (en) | 1997-06-10 | 1999-01-22 | Ind Technol Res Inst | High and low speed output buffer having controlled slew rate |
US6066958A (en) | 1998-06-03 | 2000-05-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit |
US6288563B1 (en) | 1998-12-31 | 2001-09-11 | Intel Corporation | Slew rate control |
JP2000332593A (en) | 1999-05-21 | 2000-11-30 | Mitsubishi Electric Corp | Output buffer circuit |
JP2001007695A (en) | 1999-06-18 | 2001-01-12 | Mitsubishi Electric Corp | Output buffer circuit |
JP2001068986A (en) | 1999-08-30 | 2001-03-16 | Nec Ic Microcomput Syst Ltd | Output buffer circuit for semiconductor device |
US6320433B1 (en) | 1999-09-21 | 2001-11-20 | Texas Instruments Incorporated | Output driver |
US6483340B2 (en) | 2000-06-20 | 2002-11-19 | Nec Corporation | High integration-capable output buffer circuit unaffected by manufacturing process fluctuations or changes in use |
US6466487B2 (en) | 2000-09-18 | 2002-10-15 | Kabushiki Kaisha Toshiba | Semiconductor device with impedance controllable output buffer |
US6573753B1 (en) | 2001-07-20 | 2003-06-03 | Cypress Semiconductor Corporation | Microcontroller input/output nodes with both programmable pull-up and pull-down resistive loads and programmable drive strength |
US6559676B1 (en) | 2001-11-30 | 2003-05-06 | Oki Electric Industry Co., Ltd. | Output buffer circuit |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8565032B2 (en) | 2010-04-09 | 2013-10-22 | Elpida Memory, Inc. | Semiconductor device |
US9071243B2 (en) | 2011-06-30 | 2015-06-30 | Silicon Image, Inc. | Single ended configurable multi-mode driver |
US9240784B2 (en) | 2011-06-30 | 2016-01-19 | Lattice Semiconductor Corporation | Single-ended configurable multi-mode driver |
US9281969B2 (en) * | 2011-06-30 | 2016-03-08 | Silicon Image, Inc. | Configurable multi-dimensional driver and receiver |
Also Published As
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JP2003188705A (en) | 2003-07-04 |
US6894547B2 (en) | 2005-05-17 |
US20030112042A1 (en) | 2003-06-19 |
JP3667690B2 (en) | 2005-07-06 |
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