JP2019110382A - Driving circuit - Google Patents

Abstract

To make rise transition time of voltage to be applied to a load different from fall transition time in a driving circuit.SOLUTION: A driving circuit including a plurality of switching sections each having a gate terminal to which a gate signal for controlling switching timing is applied includes: a first circuit unit including two switching sections connected in series and forming a first external connection terminal between the two switching sections; a second circuit unit including two switching sections connected in series and forming a second external connection terminal between the two switching sections; and a control unit for generating gate signals to be supplied to the gate terminals of the respective switching sections. In the driving circuit, the control unit makes the rise transition time of an external output signal in at least either one of the first external connection terminal and the second external terminal different from the fall transition time of the external output signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a drive circuit.

Conventionally, an example using an H-type bridge circuit is known as a drive circuit for supplying power to a load (see, for example, Patent Documents 1 and 2).
Patent Document 1 Japanese Patent Application Publication No. 2013-110862 Patent Document 2 Japanese Patent Application Publication No. 2013-110863

  It may be preferable in some cases to make the transition time of the rise of the voltage applied to the load different from the transition time of the fall. For example, in a smooth impact drive mechanism used for driving a lens of a camera, a process of moving an object by friction force by slowly expanding (or contracting) the piezoelectric element and contracting (or expanding) the piezoelectric element rapidly And repeating the steps of expanding and contracting the piezoelectric element without moving the object. The applied voltage for expanding and contracting the piezoelectric element in such a smooth impact drive mechanism preferably has different rising transition time and falling transition time.

  In order to solve the above-mentioned subject, in one mode of the present invention, a drive circuit provided with a plurality of switching parts which have a gate terminal to which a gate signal which controls switching timing is applied is provided. The drive circuit may include a first circuit unit including two switching units connected in series, and a first external connection terminal provided between the two switching units. The drive circuit may include a second circuit unit including two switching units connected in series, and a second external connection terminal provided between the two switching units. The drive circuit may include a control unit that generates a gate signal to be supplied to the gate terminal of each switching unit. The control unit may make the transition time of the rise of the external output signal at least one of the first external connection terminal and the second external connection terminal different from the transition time of the fall according to the gate signal.

  The control unit may set the falling transition time of the external output signal to be longer than the rising transition time of the external output signal.

  At least one switching unit may have a plurality of MOS transistors connected in parallel. The control unit controls at least one MOS transistor of the plurality of MOS transistors included in one switching unit at a timing different from that of the other MOS transistors, thereby making the transition time of the rise of the external output signal and the fall of The transition time may be different.

  The control unit may adjust the rising or falling slope of the external output signal by controlling the timing at which each MOS transistor is turned on or off.

  The first circuit unit and the second circuit unit may be provided between the high voltage side wiring and the low voltage side wiring. In each of the first circuit unit and the second circuit unit, the switching unit disposed on the low voltage side wiring side may have a plurality of MOS transistors.

  At least one switching unit includes a MOS transistor, a gate resistor provided in a path for transmitting a gate signal to the gate of the MOS transistor, and a bypass switch for controlling whether to transmit the gate signal by bypassing the gate resistor. You may have The control unit may make the rising transition time of the external output signal different from the falling transition time by controlling the bypass switch.

  The first circuit unit and the second circuit unit may be provided between the high voltage side wiring and the low voltage side wiring. In each of the first circuit unit and the second circuit unit, the switching unit disposed on the low voltage side wiring side may have a MOS transistor, a gate resistor, and a bypass switch.

  In each of the first circuit unit and the second circuit unit, one of the switching units has a P-channel type MOS transistor, and the other switching unit has an N-channel type MOS transistor, and each of the switching units is The gate resistor connected to the P-channel type MOS transistor has a gate resistor connected to the gate terminal of the MOS transistor and a bypass switch for controlling whether to connect both ends of the gate resistor by bypass. The resistance value may be smaller than the gate resistance connected to the N channel type MOS transistor.

  The control unit may adjust the rising or falling slope of the external output signal by controlling the ratio of the on time and the off time of the bypass switch at the time of transition of the external output signal.

  The control unit may make the transition time of the rising edge of the external output signal different from the transition time of the falling edge by controlling the ratio of the on time and the off time of the at least one switching unit.

  Note that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a subcombination of these feature groups can also be an invention.

It is a figure showing an example of drive circuit 100 concerning a 1st example. FIG. 5 is a diagram showing an example of waveform patterns of a gate signal GS and an external output signal OUT in the example of FIG. 1. It is a figure showing an example of a waveform of gate signal GS4 between time t3 to t4. FIG. 5 is a diagram showing an example of waveform patterns of a gate signal GS and an external output signal OUT in the example of FIG. 1. It is a figure which shows an example of the drive circuit 100 which concerns on 2nd Example. FIG. 6 is a diagram showing an example of waveform patterns of a gate signal GS and an external output signal OUT in the example of FIG. 5. FIG. 6 is a diagram showing an example of waveform patterns of a gate signal GS and an external output signal OUT in the example of FIG. 5. FIG. 6 is a diagram showing another configuration example of the drive circuit 100. FIG. 6 is a diagram showing another configuration example of the drive circuit 100. It is a figure which shows an example of the drive circuit 100 which concerns on 3rd Example. FIG. 6 is a view showing an example of the configuration of a bypass switch 26. FIG. 11 is a diagram showing an example of waveform patterns of the gate signal GS and the external output signal OUT in the example of FIG. 10. FIG. 11 is a diagram showing an example of waveform patterns of the gate signal GS and the external output signal OUT in the example of FIG. 10. FIG. 11 is a diagram showing an example of waveform patterns of the gate signal GS and the external output signal OUT in the example of FIG. 10. FIG. 11 is a diagram showing an example of waveform patterns of the gate signal GS and the external output signal OUT in the example of FIG. 10.

  Hereinafter, the present invention will be described through the embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Moreover, not all combinations of features described in the embodiments are essential to the solution of the invention.

(First embodiment)
FIG. 1 is a diagram showing an example of a drive circuit 100 according to an embodiment of the present invention. The drive circuit 100 supplies power to the load 200. The load 200 is a load having a capacitive component as an example. The load 200 may have an inductive component. As a more specific example, the load 200 is a smooth impact drive mechanism that moves the object by expanding and contracting the piezoelectric element according to the applied voltage.

  The drive circuit 100 includes a first circuit unit 10-1, a second circuit unit 10-2, and a control unit 50. The first circuit unit 10-1 and the second circuit unit 10-2 are provided between the high voltage side wire 16 and the low voltage side wire 18.

  The first circuit unit 10-1 includes two switching units 20-1 and 20-2 connected in series between the high voltage side wiring 16 and the low voltage side wiring 18. A first external connection terminal 14-1 is provided between the switching unit 20-1 and the switching unit 20-2.

  The second circuit unit 10-2 includes two switching units 20-3 and a switching unit 20-4 connected in series between the high voltage side wire 16 and the low voltage side wire 18. A second external connection terminal 14-2 is provided between the switching unit 20-3 and the switching unit 20-4.

  Each switching unit 20 has a gate terminal G to which a gate signal for controlling switching timing is applied. In this example, each switching unit 20 includes one or more MOS transistors 22 each having a gate terminal G. The MOS transistor 22 may be provided with a parasitic diode.

  In each circuit unit 10, the polarity of the channel may be different between the MOS transistor 22 included in the switching unit 20 on the high voltage side wire 16 side and the MOS transistor 22 included in the switching unit 20 on the low voltage side wire 18 side. In the example of FIG. 1, the MOS transistor 22 of the switching unit 20 on the high voltage side wire 16 side is a P-channel type, and the MOS transistor 22 of the switching unit 20 on the low voltage side wire 18 is an N channel type. The P channel type MOS transistor 22 is provided between the high voltage side wiring 16 and the external connection terminal 14, and the N channel type MOS transistor 22 is provided between the external connection terminal 14 and the low voltage side wiring 18.

  A load 200 is connected between the first external connection terminal 14-1 and the second external connection terminal 14-2. The external output signal at the first external connection terminal 14-1 is OUT1, and the external output signal at the second external connection terminal 14-2 is OUT2. The external output signal is, for example, a voltage signal.

  The control unit 50 generates a gate signal GS supplied to the gate terminal of each switching unit 20 (in this example, the gate terminal G of the MOS transistor 22). As an example, the control unit 50 may include a digital circuit that generates a digital signal indicating a logic value pattern that each gate signal should have, and a driver circuit that generates an analog gate signal GS according to the digital signal. .

  Control unit 50 generates gate signal GS for each switching unit 20. The control unit 50 in the example of FIG. 1 generates gate signals GS1 to GS4 for the switching units 20-1 to 20-4.

  The control unit 50 controls the respective switching units 20 by the gate signal GS to control the voltage and current supplied to the load 200. As one example, two switching units 20 included in each circuit unit 10 operate in a complementary manner. When the switching unit 20-1 is turned on in the first circuit unit 10-1 and the switching unit 20-2 is turned off, the first external connection terminal 14-1 is connected to the high voltage side wiring 16, so an external output signal is output. OUT1 is at the H level voltage. In addition, when the switching unit 20-1 is turned off and the switching unit 20-2 is turned on in the first circuit unit 10-1, the first external connection terminal 14-1 is connected to the low voltage side wiring 18, so The output signal OUT1 is at the L level voltage. The L level voltage is, for example, the ground potential. The H level voltage is a voltage higher than the L level voltage. The H level voltage and the L level voltage may be different for each signal.

  Similarly, in the second circuit unit 10-2, when the switching unit 20-3 is turned on and the switching unit 20-4 is turned off, the second external connection terminal 14-2 is connected to the high voltage side wiring 16 The external output signal OUT2 is at the H level voltage. In addition, when the switching unit 20-3 is turned off and the switching unit 20-4 is turned on in the second circuit unit 10-2, the second external connection terminal 14-2 is connected to the low voltage side wiring 18, so The output signal OUT2 is at the L level voltage. The control unit 50 controls the voltage waveform of each external output signal OUT by controlling the state of each switching unit 20 by the gate signal GS.

  In addition, the control unit 50 controls the waveform of the gate signal GS to make the transition time of the rising of the external output signal OUT at least one of the first external connection terminal 14-1 and the second external connection terminal 14-2; Make the transition time of falling fall different. Thereby, for example, the smooth impact drive mechanism can be driven efficiently.

  FIG. 2 is a diagram showing an example of waveform patterns of the gate signal GS and the external output signal OUT in the example of FIG. The horizontal axis in FIG. 2 is a time axis. The control unit 50 of this example makes the transition time of the rising edge different from the transition time of the falling edge in the external output signal OUT2. The transition time refers to the time from when the voltage level of the signal starts to change with respect to L level (or H level) until it reaches H level (or L level).

  At time t0, gate signals GS1 and GS2 attain L level, and gate signals GS3 and GS4 attain H level. Thereby, the MOS transistors 22-1 and 22-4 are turned on, and the MOS transistors 22-3 and 22-2 are turned off. As a result, the external output signal OUT1 becomes H level and OUT2 becomes L level.

  Next, at time t1, gate signals GS1 and GS2 become H level. Thereby, the MOS transistor 22-1 is turned off, and the MOS transistor 22-2 is turned on. As a result, the external output signal OUT1 becomes L level.

  Next, at time t2, gate signals GS3 and GS4 attain L level. Thereby, the MOS transistor 22-3 is turned on, and the MOS transistor 22-4 is turned off. As a result, the external output signal OUT2 becomes H level.

  Next, at time t3, the gate signals GS3 and GS4 become H level. As a result, the MOS transistor 22-3 is turned off, and the MOS transistor 22-4 is turned on. As a result, the external output signal OUT2 becomes L level.

  However, the control unit 50 of this example generates the gate signal GS4 in which the voltage level repeats the H level and the L level alternately from time t3 to t4. More specifically, control unit 50 performs pulse width modulation of gate signal GS4 from time t3 to time t4 to gradually increase the period of H level of gate signal GS4. That is, the control unit 50 controls the ratio of the on time and the off time of the switching unit 20-4 between time t3 and time t4. Thereby, the transition time of the rising edge 30 of the external output signal OUT2 and the transition time of the falling edge 32 can be made different. In this example, the transition time of the falling edge 32 can be longer than the transition time of the rising edge 30.

  At time t5, gate signals GS1 and GS2 attain L level. Thereby, the MOS transistor 22-1 is turned on, and the MOS transistor 22-2 is turned off. As a result, the external output signal OUT1 becomes H level. After t5, the patterns of t1 to t5 are repeated.

  FIG. 3 is a diagram showing an example of the waveform of the gate signal GS4 between times t3 and t4. As described above, the control unit 50 performs pulse width modulation on the gate signal GS4 in a period from time t3 to time t4 when the gate signal GS3 changes to the H level. In the gate signal GS4 of this example, the duty ratio (the ratio of H level in a predetermined period) immediately after time t3 is 0%. The control unit 50 gradually increases the duty ratio of the gate signal GS4 between time t3 and t4, and gradually increases the period in which the gate signal GS4 is H level. The gate signal GS4 of this example has a duty ratio of 100% after time t4.

  By such control, the falling edge 32 of the external output signal OUT2 gradually falls from the H level to the L level from time t3 to time t4. The control unit 50 may adjust the inclination of the falling edge 32 by adjusting the timing of time t4 at which the duty ratio of the gate signal GS4 is 100%. The control unit 50 may adjust the timing for setting the duty ratio of the gate signal GS to 100% according to the length of the transition time to be set. The control unit 50 may linearly increase or non-linearly increase the duty ratio of the gate signal GS4 from time t3 to time t4. Further, the control unit 50 may adjust the inclination for each falling edge 32 of the external output signal OUT2.

  FIG. 4 is a diagram showing an example of waveform patterns of the gate signal GS and the external output signal OUT in the example of FIG. The control unit 50 of this example makes the transition time of the rising edge different from the transition time of the falling edge in the external output signal OUT1. For example, in the smooth impact drive mechanism, the direction in which the object moves differs between the pattern shown in FIG. 2 and the pattern shown in FIG. That is, the patterns of FIG. 2 and FIG. 4 can be used differently depending on whether the piezoelectric element is stretched slowly to contract rapidly or rapidly stretched to contract slowly. In the former case, the object moves in the extension direction of the piezoelectric element, and in the latter case the object moves in the contraction direction of the piezoelectric element. In any case, the object can be moved efficiently by adjusting the transition time of the edge of the corresponding external output signal OUT.

  In the example of FIG. 4, at time t10, the gate signals GS3 and GS4 become L level, and the gate signals GS1 and GS2 become H level. Thereby, MOS transistors 22-3 and 22-2 are turned on, and MOS transistors 22-1 and 22-4 are turned off. As a result, the external output signal OUT1 becomes L level and OUT2 becomes H level.

  Next, at time t11, gate signals GS3 and GS4 become H level. As a result, the MOS transistor 22-3 is turned off, and the MOS transistor 22-4 is turned on. As a result, the external output signal OUT2 becomes L level.

  Next, at time t12, gate signals GS1 and GS2 attain L level. Thereby, the MOS transistor 22-1 is turned on, and the MOS transistor 22-2 is turned off. As a result, the external output signal OUT1 becomes H level.

  Next, at time t13, gate signals GS1 and GS2 attain H level. Thereby, the MOS transistor 22-1 is turned off, and the MOS transistor 22-2 is turned on. As a result, the external output signal OUT1 becomes L level.

  However, the control unit 50 of this example pulse-width modulates the gate signal GS2 from time t13 to t14 in the same manner as the gate signal GS4 from time t3 to t4 in FIG. 2 to gradually increase the H level period of the gate signal GS2. increase. The transition time of the rising edge 30 of the external output signal OUT1 and the transition time of the falling edge 32 can be made different. In this example, the transition time of the falling edge 32 can be longer than the transition time of the rising edge 30.

  Next, at time t15, gate signals GS3 and GS4 attain L level. Thereby, the MOS transistor 22-3 is turned on, and the MOS transistor 22-4 is turned off. As a result, the external output signal OUT2 becomes H level. The pattern of t11 to t15 is repeated after t15.

  In the examples of FIGS. 1 to 4, the control unit 50 performs pulse width modulation on the gate signal GS2 or GS4. In another example, the control unit 50 may perform pulse width modulation on the gate signal GS1 or GS3. For example, the control unit 50 can perform pulse width modulation on the gate signal GS3 within a predetermined period from time t2 in FIG. In this case, the slope of the rising edge 30 of the external output signal OUT2 can be adjusted. The control unit 50 can also pulse-width modulate the gate signal GS1 within a predetermined period from time t12 in FIG. In this case, the slope of the rising edge 30 of the external output signal OUT1 can be adjusted.

  The control unit 50 can adjust the inclination of each edge of each external output signal OUT by pulse width modulating the corresponding gate signal GS. For example, the rising edge of the external output signal OUTn (where n is 1 or 2) corresponds to the gate signal GS of the switching unit 20 on the high voltage side wire 16 side of the nth circuit unit 10-n. The gate signal GS of the switching unit 20 on the low-voltage side wire 18 side of the nth circuit unit 10-n corresponds to the falling edge. In addition, the control unit 50 may perform pulse width modulation on two or more gate signals GS. Thereby, the slopes of two or more edges of the external output signal OUT can be adjusted.

Second Embodiment
FIG. 5 is a diagram showing another example of the drive circuit 100. As shown in FIG. The drive circuit 100 of this example differs from the drive circuit 100 shown in FIG. 1 in the configuration of the switching units 20-2 and 20-4. The other configuration may be identical to that of the drive circuit 100 shown in FIG.

  Each of switching units 20-2 and 20-4 has a plurality of MOS transistors 22 connected in parallel. The switching unit 20-2 of this example includes MOS transistors 22-2 and 22-6 provided in parallel with each other between the first external connection terminal 14-1 and the low voltage side wire 18. The switching unit 20-4 of this example includes the MOS transistors 22-4 and 22-8 provided in parallel with each other between the second external connection terminal 14-2 and the low voltage side wire 18. Each switching unit 20-2 may have more MOS transistors 22.

  The control unit 50 supplies independent gate signals GS to the gate terminals of the plurality of MOS transistors 22 included in each switching unit 20. The control unit 50 of this example supplies the gate signal GS6 to the MOS transistor 22-6 and supplies the gate signal GS8 to the MOS transistor 22-8.

  The control unit 50 controls at least one MOS transistor 22 of the plurality of MOS transistors 22 included in one switching unit 20 at a timing different from that of the other MOS transistors 22 by the gate signal GS. Thereby, the transition time of the rising of the external output signal OUT is made different from the transition time of the falling.

  FIG. 6 is a diagram showing an example of waveform patterns of the gate signal GS and the external output signal OUT in the example of FIG. In this example, the patterns of the gate signals GS1, GS3 and GS2 are the same as the patterns of the gate signals GS1, GS3 and GS2 shown in FIG. The pattern of the gate signal GS6 is the same as the pattern of the gate signal GS2. The pattern of the gate signal GS4 from time t0 to t3 is the same as the pattern of the gate signal GS4 shown in FIG.

  The pattern of the gate signal GS8 from time t0 to t3 is the same as the pattern of the gate signal GS4. That is, until time t3, the plurality of MOS transistors 22 in the switching unit 20-4 transition to the same state at the same timing.

  Among the gate signals GS supplied to the switching unit 20-4 at time t3, at least one gate signal GS (GS8 in this example) transitions to the H level. Thereby, at least one MOS transistor 22 (in the present example, the MOS transistor 22-8) among the plurality of MOS transistors 22 included in the switching unit 20-4 is turned on. Thereby, the voltage of the external output signal OUT2 starts to decrease.

  The control unit 50 sequentially shifts the gate signal GS supplied to the switching unit 20-4 to the H level from time t3 to time t4. Thereby, the plurality of MOS transistors 22 included in the switching unit 20-4 are sequentially turned on. At time t4, the control unit 50 may control all the MOS transistors 22 included in the switching unit 20-4 to the on state. The pattern of the gate signals GS4 and GS8 after time t4 may be the same as the pattern of the gate signal GS4 shown in FIG.

  By such control, the transition time of the rising edge 30 of the external output signal OUT2 and the transition time of the falling edge 32 can be made different. In this example, the transition time of the falling edge 32 can be longer than the transition time of the rising edge 30.

  The number of MOS transistors 22 included in the switching unit 20 may be three or more. As the number of MOS transistors 22 increases, the shape of the edge of the external output signal OUT can be controlled with high accuracy. The control unit 50 may adjust the rising or falling slope of the external output signal OUT by controlling the timing at which each of the MOS transistors 22 included in one switching unit 20 is turned on or off. For example, the control unit 50 can extend the transition time of the edge of the external output signal OUT by widening the interval at which the MOS transistors 22 are sequentially turned on or off. The control unit 50 may adjust the timing of controlling each of the MOS transistors 22 in accordance with the length of the transition time set.

  FIG. 7 is a diagram showing an example of waveform patterns of the gate signal GS and the external output signal OUT in the example of FIG. The control unit 50 of this example makes the transition time of the rising edge different from the transition time of the falling edge in the external output signal OUT1. In this example, the patterns of the gate signals GS1, GS3 and GS4 are the same as the patterns of the gate signals GS1, GS3 and GS4 shown in FIG. The pattern of the gate signal GS8 is the same as the pattern of the gate signal GS4. The pattern of the gate signal GS2 from time t10 to t13 is the same as the pattern of the gate signal GS2 shown in FIG.

  The pattern of the gate signal GS6 from time t10 to t13 is the same as the pattern of the gate signal GS2. That is, until time t13, the plurality of MOS transistors 22 in the switching unit 20-2 transition to the same state at the same timing.

  Among the gate signals GS supplied to the switching unit 20-2 at time t13, at least one gate signal GS (GS6 in this example) transitions to the H level. As a result, at least one MOS transistor 22 (in the present example, the MOS transistor 22-6) among the plurality of MOS transistors 22 included in the switching unit 20-2 is turned on. As a result, the voltage of the external output signal OUT1 starts to decrease.

  The control unit 50 sequentially shifts the gate signal GS supplied to the switching unit 20-2 to the H level from time t13 to time t14. As a result, the plurality of MOS transistors 22 included in the switching unit 20-2 are sequentially turned on. At time t14, the control unit 50 may control all the MOS transistors 22 included in the switching unit 20-2 to be in the on state. The pattern of the gate signals GS2 and GS6 after time t14 may be the same as the pattern of the gate signal GS2 shown in FIG.

  By such control, the transition time of the rising edge 30 of the external output signal OUT1 and the transition time of the falling edge 32 can be made different. In this example, the transition time of the falling edge 32 can be longer than the transition time of the rising edge 30.

  In the examples of FIGS. 5 to 7, in each of the first circuit unit 10-1 and the second circuit unit 10-2, the switching unit 20 disposed on the low voltage side wiring 18 side (in this example, the switching unit 20-2) And 20-4) have a plurality of MOS transistors 22. In another example, one or more of the switching units 20 may include a plurality of MOS transistors 22. The transition time of the corresponding edge of the external output signal OUT can be adjusted by having any one of the switching units 20 have a plurality of MOS transistors 22.

  FIG. 8 is a diagram showing another configuration example of the drive circuit 100. In FIG. In the drive circuit 100 of this example, in each of the first circuit part 10-1 and the second circuit part 10-2, the switching part 20 disposed on the high voltage side wiring 16 side (in this example, the switching parts 20-1 and 20). 3) has a plurality of MOS transistors 22. Such a configuration makes it possible to adjust the transition time of the rising edge of each external output signal OUT.

  FIG. 9 is a diagram showing another configuration example of the drive circuit 100. In FIG. In the drive circuit 100 of this example, all the switching units 20 have a plurality of MOS transistors 22. Such a configuration makes it possible to adjust the transition time of any edge of each external output signal OUT.

  In the examples of FIGS. 5 to 9, the control unit 50 may perform pulse width modulation on any one or more of the gate signals GS as in the examples of FIGS. 1 to 4. Thereby, the inclination of the edge of the external output signal OUT can be controlled more accurately.

Third Embodiment
FIG. 10 is a diagram showing another configuration example of the drive circuit 100. In FIG. The drive circuit 100 of this example differs from the drive circuit 100 shown in FIGS. 1 to 9 in the configuration of the switching units 20-2 and 20-4. Other configurations may be identical to the drive circuit 100 of any of the aspects shown in FIGS. 1-9.

  Each of the switching units 20-2 and 20-4 has one or more MOS transistors 22, a gate resistor 24 provided for each MOS transistor 22, and a bypass provided for each MOS transistor 22. A switch 26 is provided.

  The gate resistor 24 is provided in a path for transmitting the gate signal GS to the gate terminal G of the MOS transistor 22. The path connects the gate terminal G of the MOS transistor 22 and the control unit 50.

  The bypass switch 26 bypasses the gate resistor 24 and controls whether to transmit the gate signal GS to the gate terminal G or not. The bypass switch 26 is provided in a path which shorts both ends of the gate resistor 24. The resistance value in the path is smaller than the resistance value of the gate resistor 24. That is, the bypass switch 26 changes the path through which the gate signal GS is transmitted, thereby changing the gate resistance value of each MOS transistor 22, and changing the time constant of the path through which the gate signal GS passes. The change of the time constant changes the transition time of the gate voltage at the gate terminal G. Specifically, as the gate resistance value increases, the time constant increases, and the transition time of the gate voltage at the gate terminal G increases.

  The control unit 50 controls the bypass switch 26 to make the rising transition time of the external output signal OUT different from the falling transition time. The control unit 50 generates control signals SWP2, SWN2, SWP4, and SWN4 for controlling the bypass switch 26. As an example, in any one of the external output signals OUT, the control unit 50 makes the path through which the gate signal passes at the time of rise different from the path through which the gate signal GS passes at the time of fall.

  FIG. 11 is a view showing a configuration example of the bypass switch 26. As shown in FIG. The bypass switch 26 in this example has a P-channel MOS transistor 27 -P and an N-channel MOS transistor 27 -N. MOS transistors 27 -P and 27 -N are provided in parallel with each other between MOS transistor 22 and control unit 50. That is, the source terminals and the drain terminals of the MOS transistors 27-P and 27-N are connected to each other.

  The control signal SWP from the control unit 50 is input to the gate terminal of the MOS transistor 27 -P. The control signal SWN from the control unit 50 is input to the gate terminal of the MOS transistor 27-N. Since the bypass switch 26 includes the MOS transistors 27-P and 27-N in parallel, the gate resistor 24 can be bypassed regardless of the level of the gate signal GS.

  FIG. 12 is a diagram showing an example of waveform patterns of the gate signal GS and the external output signal OUT in the example of FIG. In this example, the control unit 50 adjusts the transition time of the falling edge 32 of the external output signal OUT2. In this example, the patterns of the gate signals GS1, GS3 and GS2 are the same as the patterns of the gate signals GS1, GS3 and GS2 shown in FIG. The pattern of the gate signal GS4 is the same as the pattern of the gate signal GS4 shown in FIG.

  The control unit 50 sets the control signal SWP2 to the L level and sets the control signal SWN2 to the H level throughout the entire period of this example. As a result, the bypass switch 26-2 is turned on. Therefore, the gate signal GS2 passes through a path having a relatively low resistance value through the bypass switch 26-2.

  The control unit 50 sets the control signal SWP4 to the L level and sets the control signal SWN4 to the H level during a period from time t0 to t3. As a result, the bypass switch 26-4 is turned on. Therefore, the gate signal GS4 passes through a path having a relatively low resistance value through the bypass switch 26-4.

  During a period from time t3 to t4 (that is, a transition period of the falling edge 32 of the external output signal OUT2), the control unit 50 sets the control signal SWP4 to the H level and sets the control signal SWN4 to the L level. Thereby, the bypass switch 26-4 is turned off. For this reason, the gate signal GS4 passes through the relatively high resistance path through the gate resistor 24-4. As a result, the gate voltage at the gate terminal G of the MOS transistor 22-4 rises relatively slowly. Therefore, the voltage of the external output signal OUT2 gradually decreases during the period from time t3 to t4.

  Thus, by making the gate resistance value at the rise time of the external output signal OUT different from the gate resistance value at the fall time, the transition time at the rise time of the external output signal OUT and the transition time at the fall time Can be different.

  During a period from time t4 to t5, the control unit 50 sets the control signal SWP4 to the L level and sets the control signal SWN4 to the H level. As a result, the bypass switch 26-4 is turned on.

  The gate resistor 24 may be a variable resistor. The control unit 50 may control the resistance value of the gate resistor 24. Thereby, the inclination of the edge of the external output signal OUT can be adjusted.

  FIG. 13 is a diagram showing an example of waveform patterns of the gate signal GS and the external output signal OUT in the example of FIG. In this example, the control unit 50 adjusts the transition time of the falling edge 32 of the external output signal OUT1. In this example, the patterns of the gate signals GS1, GS3 and GS2 are the same as the patterns of the gate signals GS1, GS3 and GS2 shown in FIG. The pattern of the gate signal GS4 is the same as the pattern of the gate signal GS4 shown in FIG.

  The control unit 50 sets the control signal SWP4 to the L level and sets the control signal SWN4 to the H level throughout the entire period of this example. As a result, the bypass switch 26-4 is turned on. Therefore, the gate signal GS4 passes through a path having a relatively low resistance value through the bypass switch 26-4.

  During a period from time t10 to t13, control unit 50 sets control signal SWP2 to the L level and sets control signal SWN2 to the H level. As a result, the bypass switch 26-2 is turned on. Therefore, the gate signal GS2 passes through a path having a relatively low resistance value through the bypass switch 26-2.

  During a period from time t13 to t14 (that is, a transition period of the falling edge 32 of the external output signal OUT1), the control unit 50 sets the control signal SWP2 to the H level and sets the control signal SWN2 to the L level. Thereby, the bypass switch 26-2 is turned off. Therefore, the gate signal GS2 passes through the relatively high resistance path through the gate resistor 24-2. As a result, the gate voltage at the gate terminal G of the MOS transistor 22-2 rises relatively slowly. Therefore, the voltage of the external output signal OUT1 gradually decreases during the period from time t13 to t14.

  During a period from time t14 to time t15, control unit 50 sets control signal SWP2 to the L level and sets control signal SWN2 to the H level. As a result, the bypass switch 26-2 is turned on.

  In the examples of FIGS. 10 to 13, in each of the first circuit unit 10-1 and the second circuit unit 10-2, the switching unit 20 disposed on the low voltage side wiring 18 side (in this example, the switching unit 20-2) And 20-4) had the gate resistor 24 and the bypass switch 26. In another example, one or more of the switching units 20 may include the gate resistor 24 and the bypass switch 26. The provision of the gate resistor 24 and the bypass switch 26 in any of the switching units 20 can adjust the transition time of the corresponding edge of the external output signal OUT.

  In each of the first circuit unit 10-1 and the second circuit unit 10-2, in the drive circuit 100, the switching unit 20 disposed on the high voltage side wiring 16 side (in this example, the switching units 20-1 and 20-3) May have the gate resistor 24 and the bypass switch 26. Such a configuration makes it possible to adjust the transition time of the rising edge of each external output signal OUT.

  Further, in the drive circuit 100, all the switching units 20 may have the gate resistor 24 and the bypass switch 26. Such a configuration makes it possible to adjust the transition time of any edge of each external output signal OUT.

  Moreover, the resistance value of the gate resistance 24 in each switching part 20 may be the same, and may differ. The gate resistance 24 connected to the P-channel MOS transistor 22 may have a smaller resistance value than the gate resistance 24 connected to the N-channel MOS transistor 22. In general, the on-resistance of the element itself of the P-channel MOS transistor 22 is larger than the on-resistance of the element itself of the N-channel MOS transistor 22 of the same element size. This makes it possible to equalize the absolute value of the slope of each edge of the external output signal.

  Also in the examples of FIGS. 10 to 13, the control unit 50 may perform pulse width modulation on any one or more of the gate signals GS as in the examples of FIGS. 1 to 4. Thereby, the inclination of the edge of the external output signal OUT can be controlled more accurately. When pulse-modulating the gate signal GS in the example of FIGS. 10 to 13, it is preferable to turn on the corresponding bypass switch 26.

  Also in the examples of FIGS. 10 to 13, any one or more of the switching units 20 may have a plurality of MOS transistors 22. In this case, a gate resistor 24 and a bypass switch 26 may be provided for each MOS transistor 22, and a common gate resistor 24 and a bypass switch 26 may be provided for two or more MOS transistors 22.

  FIG. 14 is a diagram showing an example of waveform patterns of the gate signal GS and the external output signal OUT in the example of FIG. Each signal waveform of this example is the same as each signal waveform of FIG. 12 except that the control signals SWP4 and SWN4 from time t3 to t4 are pulse width modulated.

  The control unit 50 pulse width modulates the control signals SWP4 and SWN4 to control the ratio of the on time and the off time of the bypass switch 26-4 when the external output signal OUT2 falls. As a result, the falling slope of the external output signal OUT2 can be further adjusted. The aspect of the pulse width modulation of control signals SWP4 and SWN4 may be similar to the aspect of the pulse width modulation of gate signal GS shown in FIG.

  FIG. 15 is a diagram showing an example of waveform patterns of the gate signal GS and the external output signal OUT in the example of FIG. Each signal waveform of this example is the same as each signal waveform of FIG. 13 except that the control signals SWP2 and SWN2 from time t13 to t14 are pulse width modulated.

  The control unit 50 pulse width modulates the control signals SWP2 and SWN2 to control the ratio of the on time and the off time of the bypass switch 26-4 when the external output signal OUT1 falls. As a result, the falling slope of the external output signal OUT1 can be further adjusted.

  In the first embodiment, the gate signal GS is pulse width modulated. The control unit 50 preferably includes a circuit such as a PLL capable of generating a high frequency clock signal. In the second and third embodiments, the control unit 50 may not have a circuit such as a PLL. Therefore, the circuit size of the control unit 50 can be reduced.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It is apparent to those skilled in the art that various changes or modifications can be added to the above embodiment. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the present invention.

  The execution order of each process such as operations, procedures, steps, and steps in the apparatuses, systems, programs, and methods shown in the claims, the specification, and the drawings is particularly “before”, “preceding” It is to be noted that “it is not explicitly stated as“ etc. ”and can be realized in any order as long as the output of the previous process is not used in the later process. With regard to the flow of operations in the claims, the specification and the drawings, even if it is described using “first,” “next,” etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

DESCRIPTION OF SYMBOLS 10 ... Circuit part, 14 ... External connection terminal, 16 ... High voltage | pressure side wiring, 18 ... Low voltage | pressure side wiring, 20 ... Switching part, 22 ... MOS transistor, 24 ... Gate Resistance 26: bypass switch 27 MOS transistor 30: rising edge 32: falling edge 50: control unit 100: drive circuit 200: load

Claims (10)

A drive circuit comprising: a plurality of switching units having gate terminals to which gate signals for controlling switching timing are applied,
A first circuit unit including two switching units connected in series, and a first external connection terminal provided between the two switching units;
A second circuit unit including two switching units connected in series, and a second external connection terminal provided between the two switching units;
A control unit that generates a gate signal to be supplied to the gate terminal of each of the switching units;
The control circuit is a drive circuit which makes the transition time of the rise of the external output signal at least one of the first external connection terminal and the second external connection terminal different from the transition time of the fall according to the gate signal. The drive circuit according to claim 1, wherein the control unit makes a transition time of falling of the external output signal longer than a transition time of rising of the external output signal. At least one of the switching units includes a plurality of MOS transistors connected in parallel;
The control unit controls at least one MOS transistor of the plurality of MOS transistors included in one switching unit at a timing different from that of the other MOS transistor, thereby to provide a transition time of rising of the external output signal; The drive circuit according to claim 1, wherein the transition time of falling is made different. 4. The drive circuit according to claim 3, wherein the control unit adjusts a rising or falling slope of the external output signal by controlling a timing at which each of the MOS transistors is turned on or off. The first circuit unit and the second circuit unit are provided between the high voltage side wiring and the low voltage side wiring,
5. The drive circuit according to claim 3, wherein in each of the first circuit unit and the second circuit unit, a switching unit disposed on the low voltage side wiring side includes the plurality of MOS transistors. At least one of the switching units is
MOS transistors,
A gate resistor provided in a path for transmitting the gate signal to the gate terminal of the MOS transistor;
And a bypass switch for controlling whether or not to transmit the gate signal by bypassing the gate resistor.
The drive circuit according to any one of claims 1 to 5, wherein the control unit controls the bypass switch to make the transition time of the rising edge of the external output signal different from the transition time of the falling edge. The first circuit unit and the second circuit unit are provided between the high voltage side wiring and the low voltage side wiring,
7. The drive circuit according to claim 6, wherein in each of the first circuit unit and the second circuit unit, a switching unit disposed on the low voltage side wiring side includes the MOS transistor, the gate resistor, and the bypass switch. . In each of the first circuit unit and the second circuit unit,
One of the switching units has a P-channel MOS transistor,
The other switching unit has an N channel type MOS transistor,
Each switching unit has a gate resistance connected to the gate terminal of the MOS transistor, and a bypass switch for controlling whether or not to connect both ends of the gate resistance.
The drive circuit according to claim 6, wherein the gate resistance connected to the P-channel MOS transistor has a resistance value smaller than that of the gate resistance connected to the N-channel MOS transistor. 9. The control unit adjusts a slope of rising or falling of the external output signal by controlling a ratio of on time and off time of the bypass switch at transition of the external output signal. The drive circuit according to any one of the preceding claims. 10. The control unit makes the transition time of the rising edge of the external output signal different from the transition time of the falling edge by controlling the ratio of the on time and the off time of at least one of the switching units. The drive circuit according to any one of the preceding claims.