JP6794240B2 - Buck-boost DC / DC converter - Google Patents

Description

The present invention relates to a buck-boost DC / DC converter that boosts or lowers the input voltage and outputs it.

As a DC / DC converter that converts a DC voltage into a DC voltage having a predetermined potential as an input voltage and outputs the DC / DC converter, there is a buck-boost DC / DC converter that can output by boosting or lowering the input voltage. Conventionally, as inventions relating to such a buck-boost DC / DC converter, for example, there are those described in Patent Document 1 and Patent Document 2.

FIG. 11 shows the configuration of the buck-boost DC / DC converter disclosed in Patent Document 1. This buck-boost DC / DC converter consists of nMOS transistors Q3 and Q4 connected in series between the input terminal to which the DC voltage Vin supplied from a DC power source such as a battery is applied and the grounding point, and the smoothing capacitor C3. Consists of nMOS transistors Q1 and Q2 connected in series between the connected output terminal and the ground point, and a feedback voltage generation circuit FB (resistors R1 and R2) that divides the output voltage Vout to generate a feedback voltage Vfb. ), An error amplifier AMP1 that outputs a voltage VA corresponding to the potential difference between the feedback voltage Vfb and the reference voltage Vref1, and a phase compensation circuit PC (resistor R3 and capacitor C1) that sets the gain and frequency characteristics of the output VA of the error amplifier. Configuration), an inverting amplifier AMP2 (adjusting the output VA with resistors R4 and R5) that inverts the output VA of the error amplifier, and a triangular wave voltage Vtri used to control the output voltage Vout by PWM (pulse width modulation). It includes a triangular wave generation circuit TWG, and a pair of first comparator CMP1 and second comparator CMP2 that input the generated triangular wave voltage Vtri and the output VA of the error amplifier AMP1 or its inverting voltage VB.

Then, an inductor (coil) L is connected between the connection node VN1 of the nMOS transistors Q1 and Q2 and the connection node VN2 of the nMOS transistors Q3 and Q4, and the nMOS transistor Q2 is connected by the output Vcmp1 of the first comparator CMP1. The nMOS transistor Q4 is driven on and off by the output Vcmp2 of the second comparator CMP2, respectively. On the other hand, the nMOS transistor Q1 turns on the output Vcmp1 of the first PWM comparator CMP1 by the inverting signal via the inverter In1, and the nMOS transistor Q3 turns on the output Vcmp2 of the second comparator CMP2 by the inverting signal via the inverter In2. , Driven off.

The buck-boost DC / DC converter shown in FIG. 12 uses the nMOS transistor Q3 when the input voltage Vin is higher than the target output voltage, that is, when the output VA of the error amplifier is higher than the peak voltage of the triangular wave voltage Vtri. In the continuous on state, the nMOS transistor Q4 is continuously turned off, and the nMOS transistors Q1 and Q2 are driven by PWM pulses to output the output voltage Vout in which the input voltage Vin is boosted. When the input voltage Vin is higher than the target output voltage, that is, when the inverting error output voltage VB inverted based on the error output voltage VA of the error amplifier AMP1 is lower than the peak voltage of the triangular wave, Q1 is continuously turned on. The nMOS transistors Q3 and Q4 are driven by PWM pulses while Q2 is continuously turned off to output the output voltage Vout whose input voltage Vin is stepped down. A section called an overlap section is provided in the middle of switching from the step-up mode to the step-down mode. In the overlap section, step-up and step-down are operating alternately or at the same time. By providing such a section, switching between step-up mode and step-down mode becomes smooth, and a stable output voltage Vout can be supplied. it can.

FIG. 12 is a diagram showing signal waveforms of the main nodes of the conventional buck-boost DC / DC converter 110 shown in FIG. The triangular wave voltage Vtri is generated by the triangular wave generation circuit TWG. The triangular wave generation circuit TWG is prepared for operating the buck-boost DC / DC converter 110 under PWM control, that is, for generating a PWM signal in which the duty ratio changes. The error output voltage VA occurs at the output of the error amplifier AMP1, and the inverting error output voltage VB occurs at the output of the inverting amplifier AMP2. The inverting reference voltage Vref2 is applied to the non-inverting input terminal (+) of the inverting amplifier AMP2.

The output Vcmp1 and the output Vcmp1 are taken out from the first comparator CMP1 and the second comparator CMP2, respectively. The output Vcmp1 is generated by comparing the inversion error output voltage VB and the triangular wave voltage Vtri in the first comparator CMP1, and the output Vcmp2 is generated by comparing the error output voltage VA and the triangular wave voltage Vtri in the second comparator CMP2. ..

The switching voltage VN1 is the common connection point of the nMOS transistor Q1 and the nMOS transistor Q2 constituting the boost switching means, and the switching voltage VN2 is the common connection point of the nMOS transistor Q3 and the nMOS transistor Q4 constituting the step-down switching means. Is output to each of the nodes N2.

Whether the buck-boost DC / DC converter 110 is operating in the step-up mode or the step-down mode can be determined by looking at the duty ratio of the switching voltage VN1 and the switching voltage VN2. That is, the section SD in which the duty ratio of the switching voltage VN1 is 100% is in the step-down mode, and the section SU in which the duty ratio of the switching voltage VN2 is 100% is in the step-up mode. This is because, due to the circuit configuration, the nMOS transistors Q1 and Q2 repeat on / off operations in the boost mode, but the nMOS transistor Q3 to which the input voltage Vin is supplied must be kept on at all times. The state in which the nMOS transistor Q3 is placed on is when the potential (VN2) of the node N2 becomes the high level “H”. Therefore, the section SU is in the boost mode. On the other hand, the section SD in which the duty ratio of the switching voltage VN1 is 100% is in the step-down mode. This is because, due to the circuit configuration, the nMOS transistors Q3 and Q4 repeatedly turn on / off each other in the step-down mode, but the nMOS transistor Q1 connected to the output voltage Vout at that time must be kept on at all times. The state in which the nMOS transistor Q1 is turned on is when the potential (VN1) of the node N1 becomes the high level “H”. Therefore, the section SD is in the step-down mode.

The buck-boost DC / DC converter disclosed in Patent Document 2 relates to a control circuit of a step-up type, step-down type or buck-boost type switching power supply including a switching element. The control circuit includes an error amplifier that generates an error signal voltage according to an error between a feedback signal indicating the electrical state of the switching power supply and a predetermined reference voltage, and a first oscillator that generates a first cycle signal of the first frequency. , The second oscillator that generates the second cycle signal of the second frequency lower than the first frequency having the slope part, and the pulse width according to the error signal voltage based on the signal corresponding to the error signal voltage and the first cycle signal. A first pulse modulator that generates a first pulse signal having a first frequency and clamps the pulse width of the first pulse signal with a predetermined first minimum pulse width, and an error signal voltage. By comparing the signal with the second period signal, a second pulse modulator that generates a second pulse signal having a pulse width corresponding to the error signal voltage, and the first pulse signal and the second pulse signal are combined and driven. It includes a synthesizer that generates a pulse signal and a driver that drives a switching element in response to the drive pulse signal.

In the heavy load state, the pulse width of the first pulse signal is adjusted, and in the light load state, the pulse width of the first pulse signal is fixed to the first minimum pulse width, and the second pulse signal is adjusted according to the load. The pulse width of is changed and the first pulse signal is masked. As a result, in the light load state, the number of pulses can be reduced, the efficiency can be improved, and the switching frequency can be fixed to the second frequency.

Japanese Patent No. 3953443 Japanese Patent No. 5625369

However, as in Patent Document 1, in the buck-boost DC / DC converter 110, it can be seen that there is an overlap section OL that is neither of the step-up mode section SU and the step-down mode section SD. The longer the overlap section OL, the longer it takes to switch between the step-up mode section SU and the step-down mode section SD, which causes a problem that the responsiveness of switching becomes slower.

Further, in the overlap section, step-up and step-down are operating alternately or simultaneously. That is, in the overlap section, the four nMOS transistors Q1 to Q4 are turned on / off, which causes a problem that the switching loss increases.

On the other hand, it is difficult to accurately align the upper limit value, the lower limit value, and the amplitude value of the two triangular wave voltages as in Patent Document 2.

The present invention has been made by paying attention to the above-mentioned problems, and an object of the present invention is to make a step-up / down operation seamlessly switch between a step-up mode and a step-down mode by a relatively simple circuit configuration. The purpose is to reduce switching loss and improve power efficiency.

A buck-boost DC / DC converter that outputs an output voltage whose input voltage is boosted or stepped down, and generates an error signal voltage that generates an error signal voltage according to the difference between the voltage corresponding to the output voltage and a predetermined reference voltage. A circuit, a lamp wave generation circuit that generates a lamp wave voltage, a first comparator that compares the error signal voltage and the lamp wave voltage, and a second comparator that compares the error signal voltage and the lamp wave voltage. A comparator, a logic calculation circuit that performs a logic calculation based on the output of the first comparator and the output of the second comparator, a step-down switching means and a step-up switching controlled by a plurality of outputs of the logic calculation circuit. A means, an inductor that switches between storage and release of energy by turning on / off one of the step-up switching means and the step-down switching means, and a smoothing means that receives the energy released from the inductor and smoothes the output voltage. A buck-boost DC / DC converter characterized by:

The logical operation circuit includes a first logical operation circuit and a second logical operation circuit that perform logical operations based on the output of the first comparator and the output of the second comparator, respectively.
The step-down switching means is controlled by the output of the first logical operation circuit and the output of one of the second logical operation circuits.
The boost switching means is controlled by the output of the first logical operation circuit and the other output of the second logical operation circuit.

The first logic circuit outputs the OR operation result, and the second logic circuit outputs the AND operation result.

The first logic circuit is a OR circuit, and the second logic circuit is a AND circuit.

The first logic circuit outputs the result of the NOR operation, and the second logic output the result of the operation of the negative logic.

The first logic circuit is a NOR circuit, and the second logic circuit is a shear fatigue circuit.

The first logic circuit and the second logic circuit are multiplexers, and the selection signals of the first logic circuit and the multiplexer constituting the second logic circuit are reference to the ramp wave voltage and the inverting signal voltage generation circuit. Produced by a third comparator that compares the voltage.

The ramp wave is generated by an oscillator circuit that outputs a first clock signal to the multiplexer, a frequency dividing portion that generates a second clock obtained by dividing the first clock signal, and the second clock. ..

The second comparator includes an inverting voltage generation circuit that generates an inverting voltage obtained by inverting the error signal voltage with reference to a predetermined inverting reference voltage, and the second comparator compares the inverting voltage with the ramp wave voltage, and the first Comparator compares the error signal voltage with the ramp wave voltage.

The inverting reference voltage is set between the maximum value and the minimum value of the ramp wave voltage.

The step-down switching means is a synchronous rectification type in which a first switching element and a second switching element are connected in series in this order between the input voltage and the ground potential, and the step-up switching means is said. It is a synchronous rectification type in which the third switching element and the fourth switching element are connected in series in this order between the output voltage and the ground potential.

The step-down switching means is a diode rectification method in which a switching element and a first rectifying diode in the opposite direction are connected in series between the input voltage and the ground potential in this order, and the step-up switching means is It is a diode rectification method in which a second rectifying diode in the opposite direction and a switching element are connected in series in this order between the output voltage and the ground potential.

The step-down switching means is a synchronous rectification type in which a first switching element and a second switching element are connected in series in this order between the input voltage and the ground potential, and the step-up switching means is said. It is characterized by a diode rectification system in which a second rectifying diode in the opposite direction and a switching element are connected in series in this order between the output voltage and the ground potential.

The step-down switching means is a diode rectification method in which a switching element and a first rectifying diode in the opposite direction are connected in series between the input voltage and the ground potential in this order, and the step-up switching means is The third switching element and the fourth switching element are connected in series between the output voltage and the ground potential in this order, which is a synchronous rectification type.

According to the above means of the present invention, it is possible to provide a buck-boost DC / DC converter capable of seamlessly switching between a step-down mode and a step-up mode and reducing power loss at the time of switching.

It is a circuit block diagram which shows 1st Embodiment of the buck-boost DC / DC converter to which this invention is applied. It is a circuit block diagram which shows the 2nd Embodiment of the buck-boost DC / DC converter to which this invention is applied. It is a figure which shows the signal waveform of the main node of FIG. 1 and FIG. It is a figure which shows the signal waveform of the main node of FIG. 1 and FIG. It is a circuit block diagram which shows the 3rd Embodiment of the buck-boost DC / DC converter to which this invention is applied. It is a figure which shows the signal waveform of the main node of FIG. It is a circuit block diagram which shows the 4th Embodiment of the buck-boost DC / DC converter to which this invention is applied. It is a figure which shows the signal waveform of the main node of FIG. It is a circuit block diagram which shows the 5th Embodiment of the buck-boost DC / DC converter to which this invention is applied. It is a figure which shows the on / off state of each transistor which constitutes a switching means in the step-down mode and the step-up mode of the 1st to 5th embodiments which concerns on this invention. It is a circuit block diagram which shows the structural example of the conventional (Patent Document 1) buck-boost DC / DC converter. It is a signal waveform diagram of the main node in the buck-boost DC / DC converter of FIG.

(First Embodiment of the present invention)
FIG. 1 is a circuit configuration diagram showing a first embodiment of a buck-boost DC / DC converter to which the present invention is applied. An embodiment of the present invention will be described below with reference to the drawings. The output voltage of a DC power source such as a battery (not shown) is the input voltage Vin of the buck-boost DC / DC converter 10 shown in FIG. The input terminal IN to which the input voltage Vin is applied is connected to the source of the switching element T1. The drain of the switching element T1 is connected to the drain of the inductor L1 and the switching element T2. The source of the switching element T2 is grounded. The switching elements T1 to T4 repeatedly turn on and off to function as switching transistors that control the current flowing through the inductor L1. The switching elements T1 and T3 are p-channel type MOS field effect transistors (hereinafter referred to as pMOS transistors), and the switching elements T2 and T4 are n-channel type MOS field effect transistors (hereinafter referred to as nMOS transistors).

One end of the inductor L1 is connected to the drain of the switching element T1 and the drain of the switching element T2. The other end of the inductor L1 is connected to the drain of the switching element T3 and the drain of the switching element T4. The source of the switching element T3 is connected to the output terminal OUT, and the source of the switching element T4 is grounded.

The output terminal OUT is connected to one end of the resistor R1 and the capacitor C2. The other end of the resistor R1 is grounded via the resistor R2.

The feedback voltage generation circuit FB is composed of resistors R1 and R2 connected in series between the output terminal OUT and the ground, and outputs a feedback voltage Vfb to each other's connection nodes. The feedback voltage Vfb is input to the inverting input terminal (−) of the error amplifier AMP1. The error comparison voltage Vref1 is input to the non-inverting input terminal (+) of the error amplifier AMP1. Then, the output terminal of the error amplifier AMP1 is connected to the phase compensation circuit PC composed of the resistor R3 and the capacitor C1, the resistor R4, and the non-inverting input terminal (+) of the first comparator.

Further, the output terminal of the error amplifier AMP1 is connected to one end of the resistor R4, and the other end of the resistor R4 is connected to the inverting input terminal (−) of the inverting amplifier AMP2 and one end of the resistor R5. The other end of the resistor R5 is connected to the output of the inverting amplifier AMP2 and the inverting input terminal (−) of the second comparator CMP2. A lamp wave voltage VR is applied to the inverting input terminal (−) of the second comparator CMP2 from the lamp wave generation circuit RWG. The non-inverting input terminal (+) of the first comparator CMP1 is connected to one end of the resistor R4, and the lamp wave voltage VR is applied to the inverting input terminal (−) of the first comparator CMP1. One end of the resistor R4 becomes the input end of the inverting amplifier, and the other end of the resistor R4 is connected to the inverting input terminal (−) of the inverting amplifier AMP2 and one end of the resistor R5. Further, the inverting comparison voltage Vref2 is connected to the non-inverting input terminal (+) of the inverting amplifier AMP2. The connection node between the other end of the resistor R5 and the output terminal of the inverting amplifier AMP2 is the output end of the inverting amplifier. The output end of the inverting amplifier is connected to the inverting input terminal (-) of the second comparator CMP2.

The ramp wave generation circuit RWG is connected to the inverting input terminal (−) of the first comparator CMP1 and the non-inverting input terminal (+) of the second comparator CMP2. The output terminals of the first comparator CMP1 and the second comparator CMP2 are connected to the OR circuit 1 and the AND circuit 2. The output terminal of the OR circuit 1 is connected to the gates of the switching elements T1 and T2 via the inverters 3 and 4, and performs a step-down operation by operating complementarily. Further, the gates of the switching elements T3 and T4 are connected to the output terminals of the AND circuit 2, and perform a boosting operation by operating complementarily.

From the viewpoint of miniaturization and cost reduction, all parts other than the inductor L1 and the capacitor C2 are mounted on the semiconductor integrated circuit device, and the inductor L1 and the capacitor C2 are externally attached to the semiconductor integrated circuit device. Is desirable.

When the load current is large, it is desirable that the switching elements T1 to T4 be externally attached from the viewpoint of cost reduction and safety.

The operation of the buck-boost DC / DC converter having such a configuration will be described below. The resistors R1 and R2 constituting the feedback voltage generation circuit FB divide the output voltage Vout output from the output terminal OUT to generate a feedback voltage Vfb and send it to the error amplifier AMP1. The error amplifier AMP1 outputs an error signal voltage Vc1 according to the difference between the feedback voltage Vfb and the error comparison voltage Vref1. The capacitor C1 and the resistor R3 constituting the phase compensation circuit PC set the gain and frequency characteristics of the error amplifier AMP1. The inverting amplifier consisting of the resistor R4, the resistor R5, the inverting amplifier AMP2, and the inverting comparison voltage Vref2 outputs the inverting signal voltage Vc2 which is the inverting voltage of the error signal voltage Vc1 output from the error amplifier AMP1 with reference to the inverting reference voltage Vref2. To do. That is, the inverting reference voltage Vref2 is an intermediate voltage between the error signal voltage Vc1 and the inverting signal voltage Vc2.

The first comparator CMP1 outputs a switch control voltage Vcmp1 according to the difference between the error signal voltage Vc1 output from the error amplifier AMP1 and the lamp wave VR output from the lamp wave generation circuit RWG. The second comparator CMP2 outputs a switch control voltage Vcmp2 according to the difference between the inverting signal voltage Vc2 output from the inverting amplifier and the lamp wave VR output from the lamp wave generation circuit RWG.

The OR circuit 1 performs an OR operation on the outputs Vcmp1 and Vcmp2 output from the first comparator CMP1 and the second comparator CMP2, and outputs the OR output 1o. The OR circuit 1 is referred to as a first logic circuit in this document. The switching elements T1 and T2 are complementarily switched on / off based on the OR output 1o.

In the logical product circuit 2, the logical product operation of the outputs Vcmp1 and Vcmp2 output from the first comparator CMP1 and the second comparator CMP2 is performed, and the logical product output 2o is output. The logical product circuit 2 is referred to as a second logic circuit in this document. The switching elements T3 and T4 are complementarily switched on / off based on the logical product output 2o.

Subsequently, the operation in switching between the step-up mode and the step-down mode will be described. Here, the operation when switching from the step-up mode to the step-down mode will be described with reference to FIGS. 1, 3 and 4. 3 and 4 are diagrams showing voltage waveforms of each part of the signal voltage generating unit when the step-up mode of the step-up / down pressure DC / DC converters 10 and 20 of the first and second embodiments to which the present invention is applied is switched from the step-up mode to the step-down mode. Is. In addition, in FIG. 3 and FIG. 4, the same voltage as in FIG. 1 is designated by the same reference numeral.

The input voltage Vin and the output voltage Vout intersect at the switching line C, and when the input voltage Vin is higher than the output voltage Vout, the mode is switched to the step-down mode, and when the input voltage Vin is lower than the output voltage Vout, the mode is switched to the step-up mode. The error comparison voltage Vref1 is always constant.

When the error signal voltage Vc1 is smaller than the ramp wave VR and the inverting signal voltage Vc2 is larger than the ramp wave VR, T1 is turned off and T2 is turned on. When the error signal voltage Vc1 is larger than the ramp wave VR or the inverting signal voltage Vc2 is smaller than the ramp wave VR, T1 is turned on and T2 is turned off.

When the error signal voltage Vc1 is smaller than the ramp wave VR or the inverted signal voltage Vc2 is larger than the ramp wave VR, T3 is turned on and T4 is turned off. When the error signal voltage Vc1 is larger than the ramp wave VR and the inverting signal voltage Vc2 is smaller than the ramp wave VR, T3 is turned off and T4 is turned on.

When the inverting signal voltage Vc2 is larger than the error signal voltage Vc1 and at least one of the error signal voltage Vc1 or the inverting signal voltage Vc2 takes a value between the minimum value and the maximum value of the ramp wave VR, the states 1 and 3 and. This is a step-down operation in which the two switch states of state 2 and state 3 are alternately transitioned. In the buck-boost DC / DC converter 10 in the step-down mode, when the switching element T1 which is a pMOS transistor is on and the switching element T2 which is an nMOS transistor is off, a current flows from the input terminal IN to the capacitor C2 via the inductor L1. Flow, magnetic energy is stored. On the contrary, when the switching element T1 is in the off state and the switching element T2 is in the on state, the magnetic energy stored in the inductor L1 is released by the current flowing through the capacitor C2 via the switching element T2 and the inductor L1. .. The switching element T3 is always on regardless of the states of the switching elements T1 and T2 in the step-down mode. By such an operation, the input voltage Vin is stepped down, and the output voltage Vout is output from the output terminal OUT.

When the inverting signal voltage Vc2 is smaller than the error signal voltage Vc1 and at least one of the error signal voltage Vc1 or the inverting signal voltage Vc2 takes a value between the minimum and maximum values of the ramp wave VR, the states 2 and 3, and It is a boosting operation that alternately transitions between the two switch states of state 2 and state 4. In the buck-boost DC / DC converter 10 in the step-up mode, when the switching element T3 which is a pMOS transistor is off and the switching element T4 which is an nMOS transistor is on, a current flows through the inductor L1 and magnetic energy is stored. On the contrary, when the switching element T1 is on and the switching element T2 is off, the magnetic energy stored in the inductor L1 is released by the current flowing from the input terminal IN to the capacitor C2 via the inductor L1. .. The switching element T1 is always on regardless of the states of the switching elements T3 and T4 in the step-up mode. By such an operation, the input voltage Vin is boosted to become the output voltage Vout, which is output from the output terminal OUT.

By setting the value of the inverting reference voltage Vref2, which is the intermediate voltage between the error signal voltage Vc1 and the inverting signal voltage Vc2, to be larger than the minimum value of the lamp wave VR and smaller than the maximum value of the lamp wave VR, the step-up mode can be changed to the step-down mode. A section where both the error signal voltage Vc1 and the inverting signal voltage Vc2 intersect with the ramp wave VR can be provided during the switching. By providing the OR circuit 1 and the AND circuit 2, the switching duty of the switching node SW1 and the switching duty of the switching node SW2 change seamlessly when switching from the step-up mode to the step-down mode with reference to the switching line C. Therefore, it is possible to reduce the switching loss when switching between the step-up mode and the step-down mode. Further, even when the input voltage Vin fluctuates, the step-up operation and the step-down operation change continuously, so that a stable output voltage Vout can always be output. As a result, the power conversion efficiency of the buck-boost DC / DC converter 10 is increased. Further, in order to make the DC / DC converter respond stably and at high speed, it is desirable that the switching duty of the switching node SW1 and the switching duty of the switching node SW2 change at a constant ratio with respect to the change of the error signal voltage Vc1. That is, it is desirable that the value of the inverting reference voltage Vref2 is set to an intermediate value between the maximum value and the minimum value of the lamp wave VR, and the duties of the first comparator output Vcmp1 and the second comparator output Vcmp2 are made equal.

In the buck-boost DC / DC converter 10, since there is a delay from the change in the error signal voltage Vc1 until the output voltage follows, oscillation occurs when the fluctuation of the output voltage is fed back to the error signal voltage Vc1 at high speed. Therefore, a compensation circuit PC using a resistor R3 and a capacitor C1 is provided for the purpose of limiting the response speed of the error signal voltage Vc1.

The switching voltage Vsw1 operates as a step-down mode by complementarily repeating on / off of the switching elements T1 and T2 on the left part of the switching line C, and always turns on the switching element T1 on the right part of the switching line C, and the switching element T2. Is always off. The switching voltage Vsw2 operates as a step-up mode by complementarily repeating on / off of the switching elements T3 and T4 on the right part of the switching line C, and always turns on the switching element T3 on the left part of the switching line C, and the switching element T4. Is always off.

(Second Embodiment of the present invention)
FIG. 2 is a circuit configuration diagram showing a second embodiment of a buck-boost DC / DC converter to which the present invention is applied. The second embodiment of FIG. 2 differs from the first embodiment shown in FIG. 1 in that the switching elements are replaced and the arrangements of the inverters 3 and 4 are changed. Other circuit parts are the same. Here, the different circuit units of FIGS. 1 and 2 will be described.

The switching elements T5 and T6 in FIG. 2 are nMOS transistors. The switching elements T5 and T6 replace the switching elements T1 and T3, which are pMOS transistors in FIG. 1, respectively. The output of the OR circuit 1 is connected to the gate of the switching element T2 via the inverter 3 and is directly connected to the gate of the switching element T5. Further, the output of the AND circuit 2 is connected to the gate of the switching element T6 via the inverter 4 and is directly connected to the gate of the switching element T4. The inverters 3 and 4 receive the outputs of the OR circuit 1 and the AND circuit 2, respectively, and invert the input signals and output them.

The switching elements T5 and T2 are complementarily switched on / off based on the output of the OR circuit 1. Therefore, when the buck-boost DC / DC converter 20 in the step-down mode is in the on state of the switching element T5 which is an nMOS transistor and the switching element T2 which is an nMOS transistor is in the off state, it is transferred from the input terminal IN to the capacitor C2 via the inductor L1. Current flows and magnetic energy is stored. On the contrary, when the switching element T5 is in the off state and the switching element T2 is in the on state, the magnetic energy stored in the inductor L1 is released by the current flowing through the capacitor C2 via the switching element T2 and the inductor L1. .. The switching element T6 is always on regardless of the states of the switching elements T5 and T2 in the step-down mode. By such an operation, the input voltage Vin is stepped down, becomes the output voltage Vout, and is output from the output terminal OUT.

The switching elements T6 and T4 are complementarily switched on / off based on the output of the AND circuit 2. Therefore, in the buck-boost DC / DC converter 20 in the step-up mode, when the switching element T6 which is an nMOS transistor is off and the switching element T4 which is an nMOS transistor is on, a current flows through the inductor L1 and magnetic energy is stored. .. On the contrary, when the switching element T1 is on and the switching element T2 is off, the magnetic energy stored in the inductor L1 is released by the current flowing from the input terminal IN to the capacitor C2 via the inductor L1. .. The switching element T5 is always on regardless of the states of the switching elements T6 and T4 in the step-up mode. By such an operation, the input voltage Vin is boosted to become the output voltage Vout, which is output from the output terminal OUT.

In the first comparator CMP1 and the second comparator CMP2, the switch control voltages Vcmp1 and Vcmp2 are output by comparing the error signal voltage Vc1 and the inverting signal voltage Vc2 with the lamp wave VR, respectively. The result of each calculation obtained by performing the logical sum and the logical product of the switch control voltages Vcmp1 and Vcmp2 is output as the logical sum output 1o and the logical product output 2o, respectively.

The input voltage Vin is supplied to the drain of the switching element T5. The output voltage Vout is taken out from the drain of the switching element T6, that is, the output terminal OUT. When the input voltage Vin and the output voltage Vout become equal, the step-down mode and the step-up mode are switched. The switching timing C between the step-down mode and the step-up mode is set by the error comparison voltage Vref1. The error comparison voltage Vref1 is applied to the non-inverting input terminal (+) of the error amplifier AMP1. When the output voltage Vout is lower than the input voltage Vin, the buck-boost DC / DC converter 20 operates in the step-down mode, and when the output voltage Vout is higher than the input voltage Vin, the buck-boost DC / DC converter 20 operates in the step-up mode. Works with. FIG. 4 shows an error signal voltage Vc1, an inverting signal voltage Vc2, an inverting reference voltage Vref2, and a ramp wave voltage VR, respectively. The error signal voltage Vc1 is output from the error amplifier AMP1, and the inverting signal voltage Vc2 is output from the inverting amplifier AMP2. The inverting reference voltage Vref2 is applied to the non-inverting input terminal (+) of the inverting amplifier AMP2. The lamp wave voltage VR is generated by the lamp wave generation circuit RWG, and is applied to the inverting input terminal (−) of the first comparator CMP1 and the non-inverting input terminal (+) of the second comparator CMP2, respectively. The inverting reference voltage Vref2 is selected so as to be an intermediate value between the upper limit value VRH and the lower limit value VRL of the lamp wave voltage VR, that is, Vref2 = (VRH + VRL) / 2. Based on the error signal voltage Vc1, the inverting signal voltage Vc2, the inverting reference voltage Vref2, and the ramp wave voltage VR shown in FIG. 4, the PWM signal used in the step-down mode and the step-up mode is generated.

FIG. 5 is a circuit configuration diagram showing a third embodiment of a buck-boost DC / DC converter to which the present invention is applied. The buck-boost DC / DC converter 50 differs from that of FIG. 2 in the following points. First, the ramp wave voltage VR is applied to the non-inverting input terminal (+) of the first comparator CMP1 and the inverting input terminal (−) of the comparator CMP2. This is different from the one in which the ramp wave voltage VR is applied to the inverting input terminal (−) of the first comparator CMP1 and the non-inverting input terminal (+) of the comparator CMP2 in FIG. It is common that the lamp wave voltage VR is applied to the input terminals having opposite polarities to the first comparator CMP1 and the comparator CMP2. Next, the output 1xo of the negative logic product circuit 1x is applied to the gate of the switching element T1 constituting the step-down switching means, and the output 2xo of the NOR circuit 2x is applied to the gate of the switching element T4 constituting the step-up switching means. doing. That is, the step-down switching means is controlled by the output of the negative logic product circuit 1x, and the step-up switching means is controlled by the output of the negative logic sum circuit 2x. Such a difference differs depending on whether the lamp wave voltage VR is applied to the inverting input terminal (−) of the first comparator CMP1 and the second comparator CMP2 or to the non-inverting input terminal (+). Such a difference is one of the design matters. Since the other circuit configurations in FIG. 5 are the same as those in FIG. 2, the description thereof will be omitted.

FIG. 6 is a diagram showing signal waveforms of the main nodes of the buck-boost DC / DC converter 50 of FIG. The input voltage Vin is supplied to the drain of the switching element T5. The output voltage Vout is taken out from the drain of the switching element T6, that is, the output terminal OUT. When the input voltage Vin and the output voltage Vout become equal, the step-down mode and the step-up mode are switched. The switching timing C between the step-down mode and the step-up mode is set by the error comparison voltage Vref1. The error comparison voltage Vref1 is applied to the non-inverting input terminal (+) of the error amplifier AMP1. When the output voltage Vout is lower than the input voltage Vin, the buck-boost DC / DC converter 50 operates in the step-down mode, and when the output voltage Vout is higher than the input voltage Vin, the buck-boost DC / DC converter 50 operates in the step-up mode. Works with.

FIG. 6 shows an error signal voltage Vc1, an inverting signal voltage Vc2, an inverting reference voltage Vref2, and a ramp wave voltage VR, respectively. The error signal voltage Vc1 is output from the error amplifier AMP1, and the inverting signal voltage Vc2 is output from the inverting amplifier AMP2. The inverting reference voltage Vref2 is applied to the non-inverting input terminal (+) of the inverting amplifier AMP2. The lamp wave voltage VR is generated by the lamp wave generation circuit RWG, and is applied to the non-inverting input terminal (+) of the first comparator CMP1 and the inverting input terminal (−) of the second comparator CMP2, respectively. The inverting reference voltage Vref2 is selected so as to be an intermediate value between the upper limit value VRH and the lower limit value VRL of the lamp wave voltage VR, that is, Vref2 = (VRH + VRL) / 2. Based on the error signal voltage Vc1, the inverting signal voltage Vc2, the inverting reference voltage Vref2, and the ramp wave voltage VR shown in FIG. 6, the PWM signal used in the step-down mode and the boosting mode is generated.

In FIG. 6, the output signal Vcmp1 is output from the first comparator CMP1 and applied to the first input terminal of the negative logical product circuit 1x and the first input terminal of the OR circuit 1. The output signal Vcmp2 is output from the second comparator CMP2 and applied to the second input end of the OR circuit 1 and the second input end of the negative OR circuit 1x, respectively. The negative logical product circuit 1x and the negative logical sum circuit 2x are referred to as a first logical operation circuit and a second logical operation circuit, respectively, in this document.

The output 1xo is obtained by the negative logic product operation of the output signal Vcmp1 and the output signal Vcmp2 in the negative logic product circuit 1x. The output 1xo becomes a low level “0” when both the output signal Vcmp1 and the output signal Vcmp2 are high level “1”, and becomes a high level “1” in other combinations. The output 1xo acts as a so-called PWM signal in which the duty ratio changes in the step-down mode with the switching point C between the step-down mode and the step-up mode as a boundary, and the duty ratio becomes 100% in the step-up mode.

The output 1xo is applied to the gate of the switching element T5 constituting the step-down switching means, and the output 2xo is applied to the gate of the switching element T4 constituting the step-up switching means.

The output 2xo is obtained by a NOR operation of the output signal Vcmp1 and the output signal Vcmp2 in the NOR circuit 2x. The output 2xo becomes a low level "0" when either the output signal Vcmp1 or the output signal Vcmp2 is a high level "1", and becomes a high level "1" when both of them are at a low level "0". The output 2xo acts as a so-called PWM signal in which the duty ratio of the output 2xo is 0% in the step-down mode and the duty ratio changes in the step-up mode, with the switching timing C between the step-down mode and the step-up mode as a boundary. Such a state becomes clear when compared with FIG. 4, but the relationship between the duty ratios in the step-down mode and the step-up mode is reversed.

The switching voltage Vsw1 is output to the switching node SW1, and the switching voltage Vsw2 is output to the switching node SW2. The switching voltage Vsw1 has the same polarity as the output 1xo, and the switching voltage Vsw2 has the opposite polarity to the output 2xo. The switching voltages Vsw1 and Vsw2 switch between storage and release of energy with respect to the inductor L1.

FIG. 7 is a circuit configuration diagram showing a fourth embodiment of a buck-boost DC / DC converter to which the present invention is applied. The buck-boost DC / DC converter 70 replaces the OR circuit 1 and the logical product circuit 2 shown in the buck-boost DC / DC converter 20 in FIG. 2 with a multiplexer M1 and a multiplexer M2, respectively, and further, a selection signal SEL of the multiplexers M1 and M2. The difference is that a third comparator CMP3 is provided to generate the above. Multiplexers are also commonly referred to as selectors. The internal circuit of the multiplexer is composed of, for example, a combination of a AND circuit AND, a OR circuit OR, and an inverter, or a combination of a negative AND circuit NAND and an inverter. The multiplexer M1 and the multiplexer M2 are also referred to in this document as a first logical operation circuit and a second logical operation circuit, respectively.

The multiplexers M1 and M2 according to the present invention output either the switch control voltage Vcmp1 or the switch control voltage Vcmp2 by the selection signal SEL. The multiplexers M1 and M2 have an input terminal A and an input terminal B, and when the selection signal SEL is at a high level “1”, the voltage received at the input terminal A is received by the selection signal SEL at a low level “0”. At that time, the voltage received at the input terminal B is output. For example, the multiplexer M1 outputs the switch control voltage Vcmp1 when the selection signal SEL is at the low level “0” and the switch control voltage Vcmp2 when the selection signal SEL is at the high level “1” as the multiplexer output m1.

The multiplexer M2 also outputs either the output Vcmp1 or the output Vcmp2 by the selection signal SEL. For example, the multiplexer M2 outputs the output Vcmp2 when the selection signal SEL is at the low level “0” and the output Vcmp1 when the selection signal SEL is at the high level “1” as the multiplexer output m2.

The selection signal SEL that controls the multiplexers M1 and M2 has, for example, an inverting reference voltage Vref2 at the inverting input terminal (-) of the third comparator CMP3, and a ramp wave voltage VR at the non-inverting input terminal (+) of the third comparator CMP3. Is obtained by applying. That is, since the circuit unit used in the present invention is used, it is sufficient to newly prepare a third comparator CMP3.

In the buck-boost DC / DC converter 60 of FIG. 7, the multiplexer output m1 of the multiplexer M1 is a switching element T1 constituting a step-down switching means, and the multiplexer output m2 of the multiplexer M2 is a switching element T4 constituting a boost switching means. Is applied to each. However, these signal supply paths differ depending on whether the lamp wave voltage VR is applied to the input terminal of the first comparator CMP1 or the second comparator CMP2. Unlike the signal supply path shown in FIG. 7, when the ramp wave voltage VR is applied to the non-inverting input terminal (+) of the first comparator CMP1 and the inverting input terminal (-) of the second comparator CMP2, respectively, The multiplexer output m1 of the multiplexer M1 supplies the multiplexer output m2 of the multiplexer M2 to the switching element T4 to the switching element T4.

FIG. 8 shows the signal waveforms of the main nodes of the buck-boost DC / DC converter 70 shown in FIG. In FIG. 7, a lamp wave voltage VR, an inverting reference voltage Vref2, and a selection signal SEL are added to the signal waveform diagram shown in FIG. The signal waveforms added in this way are useful for explaining the circuit operation of the multiplexers M1 and M2.

In FIG. 8, the lamp wave voltage VR and the inverting reference voltage Vref2 are shown in the uppermost stage. The lamp wave voltage VR is generated by the lamp wave voltage generation circuit RWG in FIG. 7. The inverting reference voltage Vref2 is applied to the inverting input terminal (−) of the third comparator CMP3 and the non-inverting input terminal (+) of the inverting amplifier AMP2. The magnitude of the inverting reference voltage Vref2 is selected as an intermediate value between the upper limit value VRH and the lower limit value VRL of the lamp wave voltage VR.

The selection signal SEL is generated by comparing the inverting reference voltage Vref2 and the lamp wave voltage VR in FIG. 7 with the third comparator CMP3. The selection signal SEL becomes a high level “1” in a section where the lamp wave voltage VR exceeds the inverting reference voltage Vref2, and becomes a low level “0” in a section below the inverting reference voltage Vref2.

The multiplexer M1 is configured to output the signal Vcmp1 when the selection signal SEL is “0” and the signal Vcmp2 when the selection signal SEL is “1”. Therefore, the output 1o shown in FIG. 8 is output to the output of the multiplexer M1. Such an output 1o is the same as that shown in FIG. Therefore, it becomes the same as the output 1o of the OR circuit 1 shown in FIG.

The multiplexer M2 is configured to output the signal Vcmp2 when the selection signal SEL is “0” and the signal Vcmp1 when the selection signal SEL is “1”. Therefore, the output 2o shown in FIG. 8 is output to the output of the multiplexer M2. Such an output 2o is the same as that shown in FIG. Therefore, it is the same as the output 2o of the AND circuit 2 shown in FIG.

The switching voltages Vsw1 and Vsw2 shown in FIG. 8 are also the same as those shown in FIG. 4, that is, the circuits of the multiplexers M1 and M2 and the third comparator CMP3 constituting the buck-boost DC / DC converter 70 shown in FIG. It can be seen that the configuration has the same circuit functions as the OR circuit 1 and the AND circuit 2 in FIG. 2, for example.

Further, the multiplexers M1 and M2 connect the first clock signal to the output oscillator circuit and operate based on the first clock signal. Further, a frequency dividing section is provided in which a first clock signal is input and a second clock signal divided from the first clock signal is generated, and the lamp wave generation circuit RWG receives the second clock signal. The ramp wave voltage VR may be generated.

FIG. 9 shows a diode rectification type buck-boost DC / DC converter 100 according to the present invention. The diode rectification type buck-boost DC / DC converter replaces the synchronous rectification type buck-boost DC / DC converter 20 shown in FIG. 2 with a diode rectification method. It differs from FIG. 2 in that the switching element T2 and the switching element T6 are replaced with the rectifying diode D2 and the rectifying diode D6, respectively, and the inverters 3 and 4 are not used. In such a buck-boost DC / DC converter 100, the logical sum output 1o and the negative logical product output 2o shown in FIG. 7 are applied to the switching element T5 and the switching element T4, respectively. As a matter of course, the diode rectification type buck-boost DC / DC converter 100 according to the present invention can also be applied to the one shown in FIG. 7 using a multiplexer.

In the buck-boost DC / DC converters 10, 20, 50, 70, 90 according to the present invention, a synchronous rectification method can be applied to the step-down switching means and a diode rectification method can be applied to the step-up switching means. Similarly, in the buck-boost DC / DC converters 10, 20, 50, 70, 90, a diode rectification method can be applied to the step-down switching means, and a synchronous rectification method can be applied to the step-up switching means.

FIG. 10 summarizes the on / off states of the step-down switching means of the buck-boost DC / DC converter according to the present invention and the switching elements constituting the step-up switching means described so far. In the step-down mode, the switching elements T1 and T5 constituting the step-down switching means repeat the on / off operation according to the duty ratio of the PWM signal on / off. Similarly, the switching element T2 also repeats a so-called complementary operation of turning off when the switching elements T1 and T5 are on and turning on when the switching element T1 is off, according to the duty ratio of off / on. In the step-down mode, a signal having a duty ratio of 100% is applied to the gates of the switching elements T3 and T6. Therefore, the switching elements T3 and T6 are always kept on. In the step-down mode, a signal having a duty ratio of 0%, that is, a low level is applied to the gate of the switching element T4, so that the gate is always kept off.

In the step-down mode of FIG. 10, in the step-down mode, the switching elements T1 and T5 constituting the step-down switching means are always placed in the on state. The switching element T2 is always left in the off state. Since a PWM signal for changing the on / off duty ratio is applied to the gates of the switching elements T3 and T6, the on / off operation is repeated. The switching element T4 operates complementaryly with the switching elements T3 and T6. That is, the switching element T4 is in the off state when the switching elements T3 and T6 are on, and is placed in the on state when the switching elements T3 and T6 are off.

In FIG. 10, the switch operation at the time of shifting from the step-down mode to the step-up mode or from the step-up mode to the step-down mode becomes a problem, but in the control method in which the step-up operation and the step-down operation overlap as in Patent Document 1, the step-up operation is performed. However, the switching of the step-down operation is slow and the response speed is suppressed. However, in the buck-boost DC / DC converter according to the present invention, there is no overlap section, and the response speed is improved. Further, in the configuration of Patent Document 1, since both the step-up operation and the step-down operation are performed under the condition that the values of the input voltage Vi and the output voltage Vo are close to each other, the switch loss is large. However, the buck-boost DC / DC according to the present invention. In the converter, the switch loss due to either step-up or step-down operation is reduced.

As described above, the buck-boost DC / DC converter according to the present invention aims to speed up the switching time between the step-down mode and the step-up mode by simply adding a relatively simple circuit configuration, and consumes almost no power in the switching section. Since it can be set to 0, its industrial utility value is extremely high.

1 OR circuit (first logic circuit)
2 Negative AND circuit (second logic circuit)
3,4 Inverter 10, 20, 50, 70, 90, 110 Buck-boost DC / DC converter 1x Negative logic circuit (first logic circuit)
2x NOR OR circuit (second logic circuit)
M1 multiplexer circuit (first logic circuit)
M2 multiplexer circuit (second logic circuit)
Vin Input voltage Vout Output voltage IN Input terminal OUT Output terminal AMP1 Error amplifier AMP2 Inversion amplifier CMP1 1st comparator CMP2 2nd comparator CMP3 3rd comparator FB Feedback voltage generation circuit PC Phase compensation circuit RWG Lamp wave voltage generation circuit T1 to T6 Switching element C1 to C3 Capacitor R1 to R5 Resistor L1 Inverter Vfb Feedback voltage Vc1 Error signal voltage Vc2 Inverted signal voltage VR Lamp wave Vcmp1, Vcmp2 Switch control voltage SEL Selected signal voltage 1o Logical sum output 2o Negative logical product output 1xo Negative logical product output 2xo Negative Logical sum output m1, m2 Comparator output Vref1 Error comparison voltage Vref2 Inversion reference voltage Vsw1, Vsw2 Switching voltage SW1, SW2 Switching node C Switching timing

Claims (7)

A buck-boost DC / DC converter that outputs an output voltage whose input voltage has been boosted or stepped down.
An error signal voltage generation circuit that generates an error signal voltage according to the difference between the voltage corresponding to the output voltage and a predetermined reference voltage, and
A lamp wave generation circuit that generates a lamp wave voltage and
An inverting voltage generation circuit that generates an inverting voltage obtained by inverting the error signal voltage with reference to a predetermined inverting reference voltage.
A first comparator that compares the error signal voltage with the ramp wave voltage,
A second comparator that compares the inverting voltage with the ramp wave voltage,
A logical operation circuit that performs logical operations based on the output of the first comparator and the output of the second comparator, and
A step-down switching means and a step-up switching means controlled by a plurality of outputs of the logical operation circuit,
An inductor that switches between energy storage and release by turning on / off either the step-up switching means or the step-down switching means.
A smoothing means that receives the energy emitted from the inductor and smoothes the output voltage.
With
The logical operation circuit includes a first logical operation circuit and a second logical operation circuit that perform logical operations based on the output of the first comparator and the output of the second comparator, respectively.
The step-down switching means is controlled by the output of the first logical operation circuit and the output of one of the second logical operation circuits.
The boost switching means is controlled by the output of the first logical operation circuit and the other output of the second logical operation circuit.
The first logical operation circuit and the second logical operation circuit are multiplexers.
The selection signal of the multiplexer constituting the first logical operation circuit and the second logical operation circuit is generated by a third comparator that compares the ramp wave voltage with the inverting reference voltage. Pressure DC / DC converter. A buck-boost DC / DC converter that outputs an output voltage whose input voltage has been boosted or stepped down.
An error signal voltage generation circuit that generates an error signal voltage according to the difference between the voltage corresponding to the output voltage and a predetermined reference voltage, and
A lamp wave generation circuit that generates a lamp wave voltage and
An inverting voltage generation circuit that generates an inverting voltage obtained by inverting the error signal voltage with reference to a predetermined inverting reference voltage.
A first comparator that compares the error signal voltage with the ramp wave voltage,
A second comparator that compares the inverting voltage with the ramp wave voltage,
A logical operation circuit that performs logical operations based on the output of the first comparator and the output of the second comparator, and
A step-down switching means and a step-up switching means controlled by a plurality of outputs of the logical operation circuit,
An inductor that switches between energy storage and release by turning on / off either the step-up switching means or the step-down switching means.
A smoothing means that receives the energy emitted from the inductor and smoothes the output voltage.
With
The logical operation circuit includes a first logical operation circuit and a second logical operation circuit that perform logical operations based on the output of the first comparator and the output of the second comparator, respectively.
The step-down switching means is controlled by the output of the first logical operation circuit and the output of one of the second logical operation circuits.
The boost switching means is controlled by the output of the first logical operation circuit and the other output of the second logical operation circuit.
The first logical operation circuit and the second logical operation circuit are multiplexers.
An oscillator circuit that outputs a first clock signal to the multiplexer,
A frequency dividing section that generates a second clock signal obtained by dividing the first clock signal, and
With more
A buck-boost DC / DC converter characterized in that the ramp wave voltage is generated by the second clock signal . The buck-boost DC / DC converter according to claim 1 or 2 , wherein the inverting reference voltage is set between the maximum value and the minimum value of the ramp wave voltage. The step-down switching means is a synchronous rectification type in which a first switching element and a second switching element are connected in series in this order between the input voltage and the ground potential, and the step-up switching means is said. The invention according to any one of claims 1 to 3 , wherein the third switching element and the fourth switching element are connected in series between the output voltage and the ground potential in this order, which is a synchronous rectification type. Buck-boost DC / DC converter. The step-down switching means is a diode rectification method in which a switching element and a first rectifying diode in the opposite direction are connected in series between the input voltage and the ground potential in this order, and the step-up switching means is One of claims 1 to 3 , wherein a second rectifying diode in the opposite direction and a switching element are connected in series between the output voltage and the ground potential in this order. The buck-boost DC / DC converter according to item 1. The step-down switching means is a synchronous rectification type in which a first switching element and a second switching element are connected in series in this order between the input voltage and the ground potential, and the step-up switching means is said. Any one of claims 1 to 3 , characterized in that the second rectifying diode in the opposite direction between the output voltage and the ground potential and the switching element are connected in series in this order in a diode rectifying system. The buck-boost DC / DC converter according to. The step-down switching means is a diode rectification method in which a switching element and a first rectifying diode in the opposite direction are connected in series between the input voltage and the ground potential in this order, and the step-up switching means is Any one of claims 1 to 3 , characterized in that the third switching element and the fourth switching element are connected in series in this order between the output voltage and the ground potential. The buck-boost DC / DC converter according to.

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